Pinned Loading

1. RTL_TO_GDS RTL_TO_GDS Public

   Learning RTL to GDSII flow using Mod-N conditional counter design

   Verilog

2. RISCV32_PROC RISCV32_PROC Public

   RISCV processor single cycle implementation using RV32I instruction set in verilog

   Verilog

3. AirZoneComfort AirZoneComfort Public

   C

4. STM32_DHT11_interfacing STM32_DHT11_interfacing Public

   C

5. Geoguide Geoguide Public

   Jupyter Notebook