Merge timing fixes to master

src/main/scala/coupledL2/AcquireUnit.scala

@@ -29,85 +29,25 @@ class AcquireUnit(implicit p: Parameters) extends L2Module {
   val io = IO(new Bundle() {
     val sourceA = DecoupledIO(new TLBundleA(edgeOut.bundle))
     val task = Flipped(DecoupledIO(new SourceAReq))
-    val pbRead = DecoupledIO(new PutBufferRead)
-    val pbResp = Flipped(ValidIO(new PutBufferEntry))
   })
 
   val a = io.sourceA
-  val a_out = Wire(a.cloneType)
-  val a_acquire = Wire(a.cloneType)
-  val a_put = Wire(a.cloneType)
   val task = io.task.bits
-  val put = task.opcode === PutFullData || task.opcode === PutPartialData
-  val busy = RegInit(false.B)
 
-  when (io.task.fire() && put) {
-    busy := true.B
-  }
-
-  val s1_ready = Wire(Bool())
-  val s1_valid = RegInit(false.B)
-
-  // S0: read putBuffer
-  val s0_task = RegEnable(task, 0.U.asTypeOf(task), io.task.fire() && put)
-  val s0_count = RegInit(0.U(beatBits.W))
-  val s0_last = s0_count === Mux(s0_task.size === log2Ceil(blockBytes).U, (beatSize-1).U, 0.U) // TODO
-  val s0_valid = io.pbRead.fire()
-
-  when(io.pbRead.fire()) {
-    s0_count := s0_count + 1.U
-    when (s0_last) {
-      busy := false.B
-      s0_count := 0.U
-    }
-  }
-
-  // S1: get putBuffer and transfer to outer A
-  val s1_latch = s0_valid && s1_ready
-  val s1_task = RegEnable(s0_task, 0.U.asTypeOf(s0_task), s1_latch)
-  val s1_cango = a_put.ready
-  val s1_pb_latch = HoldUnless(io.pbResp.bits, RegNext(s1_latch, false.B))
-
-  s1_ready := s1_cango || !s1_valid
-
-  when (s1_valid && s1_cango) { s1_valid := false.B }
-  when (s1_latch) { s1_valid := true.B }
-
-  a_acquire.valid := io.task.valid && !put
-  a_acquire.bits.opcode := task.opcode
-  a_acquire.bits.param := task.param
-  a_acquire.bits.size := offsetBits.U
-  a_acquire.bits.source := task.source
-  a_acquire.bits.address := Cat(task.tag, task.set, 0.U(offsetBits.W))
-  a_acquire.bits.mask := Fill(edgeOut.manager.beatBytes, 1.U(1.W))
-  a_acquire.bits.data := 0.U((edgeOut.manager.beatBytes * 8).W)
-  a_acquire.bits.echo.lift(DirtyKey).foreach(_ := true.B)
-  a_acquire.bits.user.lift(PreferCacheKey).foreach(_ := false.B)
-  a_acquire.bits.user.lift(utility.ReqSourceKey).foreach(_ := task.reqSource)
-  a_acquire.bits.corrupt := false.B
-
-  a_put.valid := s1_valid
-  a_put.bits.opcode := s1_task.opcode
-  a_put.bits.param := s1_task.param
-  a_put.bits.size := s1_task.size // TODO
-  a_put.bits.source := s1_task.source
-  a_put.bits.address := Cat(s1_task.tag, s1_task.set, s1_task.off)
-  a_put.bits.echo.lift(DirtyKey).foreach(_ := true.B)
-  a_put.bits.user.lift(PreferCacheKey).foreach(_ := false.B)
-  a_put.bits.user.lift(utility.ReqSourceKey).foreach(_ := MemReqSource.NoWhere.id.U) //Ignore: where does Put comes from
-  a_put.bits.mask := s1_pb_latch.mask
-  a_put.bits.data := s1_pb_latch.data.data
-  a_put.bits.corrupt := false.B
-
-  TLArbiter.lowest(edgeOut, a_out, a_put, a_acquire)
-  io.sourceA <> a_out
-  io.sourceA.valid := a_out.valid && !(a_acquire.valid && !a_put.valid && busy)
-
-  io.task.ready := a_acquire.ready && !busy
-
-  io.pbRead.valid := busy && s1_ready
-  io.pbRead.bits.idx := s0_task.pbIdx
-  io.pbRead.bits.count := s0_count
+  a.bits.opcode := task.opcode
+  a.bits.param := task.param
+  a.bits.size := offsetBits.U
+  a.bits.source := task.source
+  a.bits.address := Cat(task.tag, task.set, 0.U(offsetBits.W))
+  a.bits.mask := Fill(edgeOut.manager.beatBytes, 1.U(1.W))
+  a.bits.data := DontCare
+  a.bits.echo.lift(DirtyKey).foreach(_ := true.B)
+  a.bits.user.lift(PreferCacheKey).foreach(_ := false.B)
+  a.bits.user.lift(utility.ReqSourceKey).foreach(_ := task.reqSource)
+  a.bits.corrupt := false.B
+
+  a.valid := io.task.valid
+  io.task.ready := a.ready
 
   dontTouch(io)
 }

src/main/scala/coupledL2/Common.scala

@@ -60,9 +60,6 @@ class TaskBundle(implicit p: Parameters) extends L2Bundle with HasChannelBits {
   val aliasTask = aliasBitsOpt.map(_ => Bool()) // Anti-alias
   val useProbeData = Bool()               // data source, true for ReleaseBuf and false for RefillBuf
 
-  // For Put
-  val pbIdx = UInt(mshrBits.W)
-
   // For Intent
   val fromL2pft = prefetchOpt.map(_ => Bool()) // Is the prefetch req from L2(BOP) or from L1 prefetch?
                                           // If true, MSHR should send an ack to L2 prefetcher.
@@ -128,7 +125,6 @@ class MSHRStatus(implicit p: Parameters) extends L2Bundle with HasChannelBits {
 //  val alias = aliasBitsOpt.map(_ => UInt(aliasBitsOpt.get.W))
 //  val aliasTask = aliasBitsOpt.map(_ => Bool())
 //  val needProbeAckData = Bool() // only for B reqs
-//  val pbIdx = UInt(mshrBits.W)
 //  val fromL2pft = prefetchOpt.map(_ => Bool())
 //  val needHint = prefetchOpt.map(_ => Bool())
 
@@ -220,7 +216,6 @@ class SourceAReq(implicit p: Parameters) extends L2Bundle {
   val param = UInt(aWidth.W)
   val size = UInt(msgSizeBits.W)
   val source = UInt(mshrBits.W)
-  val pbIdx = UInt(mshrBits.W)
   val reqSource = UInt(MemReqSource.reqSourceBits.W)
 }
 
@@ -247,17 +242,6 @@ class NestedWriteback(implicit p: Parameters) extends L2Bundle {
   val c_set_dirty = Bool()
 }
 
-// Put Buffer
-class PutBufferRead(implicit p: Parameters) extends L2Bundle {
-  val idx = UInt(mshrBits.W)
-  val count = UInt(beatBits.W)
-}
-
-class PutBufferEntry(implicit p: Parameters) extends L2Bundle {
-  val data = new DSBeat
-  val mask = UInt(beatBytes.W)
-}
-
 class PrefetchRecv extends Bundle {
   val addr = UInt(64.W)
   val addr_valid = Bool()

src/main/scala/coupledL2/CoupledL2.scala

@@ -54,8 +54,8 @@ trait HasCoupledL2Parameters {
   val bufBlocks = 4 // hold data that flows in MainPipe
   val bufIdxBits = log2Up(bufBlocks)
 
-  val releaseBufWPorts = 3 // sinkC and mainpipe s5, s6
-  
+  val releaseBufWPorts = 3 // sinkC & mainPipe s5 & mainPipe s3 (nested)
+
   // Prefetch
   val prefetchOpt = cacheParams.prefetch
   val hasPrefetchBit = prefetchOpt.nonEmpty && prefetchOpt.get.hasPrefetchBit
@@ -82,6 +82,9 @@ trait HasCoupledL2Parameters {
   // id of 1XXXX refers to reqs that do not enter mshr
   // require(isPow2(idsAll))
 
+  val grantBufSize = mshrsAll
+  val grantBufInflightSize = mshrsAll //TODO: lack or excessive? !! WARNING
+
   // width params with bank idx (used in prefetcher / ctrl unit)
   lazy val fullAddressBits = edgeOut.bundle.addressBits
   lazy val fullTagBits = fullAddressBits - setBits - offsetBits