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chore(TestTop): support for upwards CMO for CHI TestTop #267

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Oct 29, 2024
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18 changes: 18 additions & 0 deletions src/test/scala/chi/TestTop.scala
Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,9 @@ class TestTop_CHIL2(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, iss
}
}

val l1cmo_req_nodes = (0 until numCores).map(i => BundleBridgeSource(Some(() => DecoupledIO(new CMOReq))))
val l1cmo_resp_nodes = (0 until numCores).map(i => BundleBridgeSink(Some(() => DecoupledIO(new CMOResp))))

// val l2 = LazyModule(new TL2CHICoupledL2())
val l2_nodes = (0 until numCores).map(i => LazyModule(new TL2CHICoupledL2()(new Config((site, here, up) => {
case L2ParamKey => cacheParams.copy(
Expand Down Expand Up @@ -99,6 +102,9 @@ class TestTop_CHIL2(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, iss
TLLogger(s"L2_L1[${i}].UL[${j}]", !cacheParams.FPGAPlatform && cacheParams.enableTLLog) :=
l1i
}

l2.cmo_sink_node.foreach(_ := l1cmo_req_nodes(i))
l2.cmo_source_node.foreach(l1cmo_resp_nodes(i) := _)

l2.managerNode :=
TLXbar() :=*
Expand Down Expand Up @@ -146,6 +152,15 @@ class TestTop_CHIL2(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, iss
node.makeIOs()(ValName(s"mmio_port_$i"))
}

if (cacheParams.hasCMO) {
l1cmo_req_nodes.zipWithIndex.foreach { case (node, i) =>
node.makeIOs()(ValName(s"cmo_req_$i"))
}
l1cmo_resp_nodes.zipWithIndex.foreach { case (node, i) =>
node.makeIOs()(ValName(s"cmo_resp_$i"))
}
}

val io = IO(Vec(numCores, new Bundle() {
val chi = new PortIO()(p.alterPartial { case CHIIssue => issue })
}))
Expand Down Expand Up @@ -193,6 +208,9 @@ object TestTopCHIHelper {
elaboratedTopDown = false,
FPGAPlatform = onFPGAPlatform,

// CMO
hasCMO = true,

// prefetch
prefetch = Seq(BOPParameters()),

Expand Down
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