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Misc: Split tagArray SRAM & Revert Queue_SRAM #233

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merged 2 commits into from
Sep 4, 2024
Merged

Misc: Split tagArray SRAM & Revert Queue_SRAM #233

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5ca84f8
misc: Split tagArray SRAM in Chisel
Sep 4, 2024
ec00601
revert Queue_SRAM to Queue
Sep 4, 2024
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10 changes: 9 additions & 1 deletion src/main/scala/coupledL2/Directory.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -129,7 +129,15 @@ class Directory(implicit p: Parameters) extends L2Module {
val metaWen = io.metaWReq.valid
val replacerWen = WireInit(false.B)

val tagArray = Module(new SRAMTemplate(UInt(tagBits.W), sets, ways, singlePort = true))
// val tagArray = Module(new SRAMTemplate(UInt(tagBits.W), sets, ways, singlePort = true))
val tagArray = Module(new SplittedSRAM(
gen = UInt(tagBits.W),
set = sets,
way = ways,
waySplit = 2,
singlePort = true,
readMCP2 = false
))
val metaArray = Module(new SRAMTemplate(new MetaEntry, sets, ways, singlePort = true))
val tagRead = Wire(Vec(ways, UInt(tagBits.W)))
val metaRead = Wire(Vec(ways, new MetaEntry()))
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5 changes: 2 additions & 3 deletions src/main/scala/coupledL2/GrantBuffer.scala
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Expand Up @@ -24,7 +24,6 @@ import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tilelink.TLMessages._
import coupledL2.prefetch.PrefetchResp
import coupledL2.utils.Queue_SRAM

// record info of those with Grant sent, yet GrantAck not received
// used to block Probe upwards
Expand Down Expand Up @@ -113,8 +112,8 @@ class GrantBuffer(implicit p: Parameters) extends L2Module {
// val grantQueue = Module(new Queue(new GrantQueueTask(), entries = mshrsAll))
// Use customized SRAM: dual_port, max 256bits:
val grantQueue = Module(new Queue(new GrantQueueTask(), entries = mshrsAll))
val grantQueueData0 = Module(new Queue_SRAM(new GrantQueueData(), entries = mshrsAll, useSyncReadMem = true))
val grantQueueData1 = Module(new Queue_SRAM(new GrantQueueData(), entries = mshrsAll, useSyncReadMem = true))
val grantQueueData0 = Module(new Queue(new GrantQueueData(), entries = mshrsAll))
val grantQueueData1 = Module(new Queue(new GrantQueueData(), entries = mshrsAll))

val inflightGrant = RegInit(VecInit(Seq.fill(grantBufInflightSize){
0.U.asTypeOf(Valid(new InflightGrantEntry))
Expand Down
5 changes: 2 additions & 3 deletions src/main/scala/coupledL2/tl2chi/TXDAT.scala
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Expand Up @@ -22,7 +22,6 @@ import chisel3.util._
import utility._
import org.chipsalliance.cde.config.Parameters
import coupledL2.{TaskWithData, TaskBundle, DSBlock, DSBeat}
import coupledL2.utils.Queue_SRAM

class TXDATBlockBundle(implicit p: Parameters) extends TXBlockBundle {
val blockSinkBReqEntrance = Bool()
Expand All @@ -47,8 +46,8 @@ class TXDAT(implicit p: Parameters) extends TL2CHIL2Module {
// TODO: an mshrsAll-entry queue is too much, evaluate for a proper size later
// Use customized SRAM: dual_port, max 256bits:
val queue = Module(new Queue(new TaskBundle(), entries = mshrsAll, flow = true))
val queueData0 = Module(new Queue_SRAM(new DSBeat(), entries = mshrsAll, flow = true, useSyncReadMem = true))
val queueData1 = Module(new Queue_SRAM(new DSBeat(), entries = mshrsAll, flow = true, useSyncReadMem = true))
val queueData0 = Module(new Queue(new DSBeat(), entries = mshrsAll, flow = true))
val queueData1 = Module(new Queue(new DSBeat(), entries = mshrsAll, flow = true))
queue.io.enq.valid := io.in.valid
queue.io.enq.bits := io.in.bits.task
io.in.ready := queue.io.enq.ready
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5 changes: 2 additions & 3 deletions src/main/scala/coupledL2/tl2tl/SourceC.scala
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Expand Up @@ -24,7 +24,6 @@ import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tilelink._
import coupledL2._
import huancun.DirtyKey
import coupledL2.utils.Queue_SRAM

//class SourceC(implicit p: Parameters) extends L2Module {
// val io = IO(new Bundle() {
Expand Down Expand Up @@ -139,8 +138,8 @@ class SourceC(implicit p: Parameters) extends L2Module {
// We must keep SourceC FIFO, so a queue is used
// Use customized SRAM: dual_port, max 256bits:
val queue = Module(new Queue(new TaskBundle(), entries = mshrsAll, flow = true))
val queueData0 = Module(new Queue_SRAM(new DSBeat(), entries = mshrsAll, flow = true, useSyncReadMem = true))
val queueData1 = Module(new Queue_SRAM(new DSBeat(), entries = mshrsAll, flow = true, useSyncReadMem = true))
val queueData0 = Module(new Queue(new DSBeat(), entries = mshrsAll, flow = true))
val queueData1 = Module(new Queue(new DSBeat(), entries = mshrsAll, flow = true))
queue.io.enq.valid := io.in.valid
queue.io.enq.bits := io.in.bits.task
io.in.ready := queue.io.enq.ready
Expand Down
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