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MSHR: set w_grantlast only when both response and data are received
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The CompAck must only be sent after a CompData or RespSepData (instead
of DataSepResp) is received. Therefore `w_grant.*` should be set after
RespSepData is received, otherwise CompAck might be sent before
RespSepData if RespSepData arrives in RN after DataSepResp.

Also, extra logics besides `w_grant.*` are necessary to make sure that
Grant upwards is sent only after both response and data are received.
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linjuanZ committed Jul 30, 2024
1 parent 48ccb0e commit ebbd500
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Showing 2 changed files with 5 additions and 7 deletions.
6 changes: 5 additions & 1 deletion src/main/scala/coupledL2/tl2chi/MSHR.scala
Original file line number Diff line number Diff line change
Expand Up @@ -78,6 +78,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module {
val probeDirty = RegInit(false.B)
val probeGotN = RegInit(false.B)
val timer = RegInit(0.U(64.W)) // for performance analysis
val beatCnt = RegInit(0.U(log2Ceil(beatSize).W))

val req_valid = RegInit(false.B)
val req = RegInit(0.U.asTypeOf(new TaskBundle()))
Expand Down Expand Up @@ -132,6 +133,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module {
probeDirty := false.B
probeGotN := false.B
timer := 1.U
beatCnt := 0.U

gotRetryAck := false.B
gotPCrdGrant := false.B
Expand Down Expand Up @@ -831,8 +833,9 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module {
when (rxdat.valid) {
when (rxdat.bits.chiOpcode.get === DataSepResp) {
require(beatSize == 2) // TODO: This is ugly
beatCnt := beatCnt + 1.U
state.w_grantfirst := true.B
state.w_grantlast := state.w_grantfirst
state.w_grantlast := state.w_grantfirst && beatCnt === (beatSize - 1).U
state.w_grant := req.off === 0.U || state.w_grantfirst // TODO? why offset?
gotT := rxdatIsU || rxdatIsU_PD
gotDirty := gotDirty || rxdatIsU_PD
Expand All @@ -855,6 +858,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module {
// RXRSP for dataless
when (rxrsp.valid) {
when (rxrsp.bits.chiOpcode.get === RespSepData) {
state.w_grantfirst := true.B
srcid := rxrsp.bits.srcID.getOrElse(0.U)
homenid := rxrsp.bits.srcID.getOrElse(0.U)
dbid := rxrsp.bits.dbID.getOrElse(0.U)
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6 changes: 0 additions & 6 deletions src/main/scala/coupledL2/tl2chi/chi/Opcode.scala
Original file line number Diff line number Diff line change
Expand Up @@ -235,12 +235,6 @@ object CHIOpcode {

def width(implicit p: Parameters) = width_map(p(CHIIssue))

def DataL2RdData(implicit p: Parameters) = 0x0.U(width.W)
def DataL2RdDataFwded(implicit p: Parameters) = 0x1.U(width.W)
def DataL2RdDataCancel(implicit p: Parameters) = 0x2.U(width.W)
def DataL2RdDataFwdedCancel(implicit p: Parameters) = 0x3.U(width.W)
def DataL2RdDataFwdedCancel2(implicit p: Parameters) = 0x4.U(width.W)

def DataLCrdReturn(implicit p: Parameters) = 0x0.U(width.W)
def SnpRespData(implicit p: Parameters) = 0x1.U(width.W)
def CopyBackWrData(implicit p: Parameters) = 0x2.U(width.W)
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