Support ctrl/meta-decoupled temporal prefetcher (#74)

* bump huancun

* mainpipe: enhance prefetch-train bundle

* perf: add tp rollingperf

* prefetch: support ctrl/meta-decoupled temporal prefetcher

src/main/scala/coupledL2/CoupledL2.scala

@@ -30,6 +30,7 @@ import org.chipsalliance.cde.config.Parameters
 import scala.math.max
 import coupledL2.prefetch._
 import coupledL2.utils.XSPerfAccumulate
+import huancun.{TPmetaReq, TPmetaResp}
 
 trait HasCoupledL2Parameters {
   val p: Parameters
@@ -212,6 +213,16 @@ class CoupledL2(implicit p: Parameters) extends LazyModule with HasCoupledL2Para
       Some(BundleBridgeSink(Some(() => new PrefetchRecv)))
     case _ => None
   }
+  val tpmeta_source_node = prefetchOpt match {
+    case Some(param: PrefetchReceiverParams) =>
+      if (param.hasTPPrefetcher) Some(BundleBridgeSource(() => DecoupledIO(new TPmetaReq))) else None
+    case _ => None
+  }
+  val tpmeta_sink_node = prefetchOpt match {
+    case Some(param: PrefetchReceiverParams) =>
+      if (param.hasTPPrefetcher) Some(BundleBridgeSink(Some(() => ValidIO(new TPmetaResp)))) else None
+    case _ => None
+  }
 
   class CoupledL2Imp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
     val banks = node.in.size
@@ -284,6 +295,17 @@ class CoupledL2(implicit p: Parameters) extends LazyModule with HasCoupledL2Para
         }
     }
 
+    tpmeta_source_node match {
+      case Some(x) =>
+        x.out.head._1 <> prefetcher.get.tpio.tpmeta_port.get.req
+      case None =>
+    }
+    tpmeta_sink_node match {
+      case Some(x) =>
+        prefetcher.get.tpio.tpmeta_port.get.resp <> x.in.head._1
+      case None =>
+    }
+
     def restoreAddress(x: UInt, idx: Int) = {
       restoreAddressUInt(x, idx.U)
     }

src/main/scala/coupledL2/MainPipe.scala

@@ -418,8 +418,9 @@ class MainPipe(implicit p: Parameters) extends L2Module {
       train.bits.source := Mux(req_s3.mergeA, req_s3.aMergeTask.sourceId, req_s3.sourceId)
       train.bits.vaddr.foreach(_ := Mux(req_s3.mergeA, req_s3.aMergeTask.vaddr.getOrElse(0.U), req_s3.vaddr.getOrElse(0.U)))
       train.bits.hit := Mux(req_s3.mergeA, true.B, dirResult_s3.hit)
-      train.bits.prefetched := Mux(req_s3.mergeA, true.B, meta_s3.prefetch.get(false.B))
+      train.bits.prefetched := Mux(req_s3.mergeA, true.B, meta_s3.prefetch.getOrElse(false.B))
       train.bits.pfsource := meta_s3.prefetchSrc.getOrElse(PfSource.NoWhere.id.U) // TODO
+      train.bits.reqsource := req_s3.reqSource
   }
 
   /* ======== Stage 4 ======== */

src/main/scala/coupledL2/TopDownMonitor.scala

@@ -164,6 +164,7 @@ class TopDownMonitor()(implicit p: Parameters) extends L2Module {
   )
   val l2prefetchLate = io.latePF
 
+  // PF Accuracy
   XSPerfRolling(
     cacheParams, "L2PrefetchAccuracy",
     PopCount(l2prefetchUseful), PopCount(l2prefetchSent),
@@ -179,6 +180,11 @@ class TopDownMonitor()(implicit p: Parameters) extends L2Module {
     PopCount(l2prefetchUsefulSMS), PopCount(l2prefetchSentSMS),
     1000, clock, reset
   )
+  XSPerfRolling(
+    cacheParams, "L2PrefetchAccuracyTP",
+    PopCount(l2prefetchUsefulTP), PopCount(l2prefetchSentTP),
+    1000, clock, reset
+  )
   XSPerfRolling(
     cacheParams, "L2PrefetchAccuracyStride",
     PopCount(l2prefetchUsefulStride), PopCount(l2prefetchSentStride),
@@ -194,11 +200,15 @@ class TopDownMonitor()(implicit p: Parameters) extends L2Module {
     PopCount(l2prefetchUsefulTP), PopCount(l2prefetchSentTP),
     1000, clock, reset
   )
+
+  // PF Late
   XSPerfRolling(
     cacheParams, "L2PrefetchLate",
     PopCount(l2prefetchLate), PopCount(l2prefetchUseful),
     1000, clock, reset
   )
+
+  // PF Coverage
   XSPerfRolling(
     cacheParams, "L2PrefetchCoverage",
     PopCount(l2prefetchUseful), PopCount(l2demandRequest),
@@ -214,6 +224,11 @@ class TopDownMonitor()(implicit p: Parameters) extends L2Module {
     PopCount(l2prefetchUsefulSMS), PopCount(l2demandRequest),
     1000, clock, reset
   )
+  XSPerfRolling(
+    cacheParams, "L2PrefetchCoverageTP",
+    PopCount(l2prefetchUsefulTP), PopCount(l2demandRequest),
+    1000, clock, reset
+  )
   XSPerfRolling(
     cacheParams, "L2PrefetchCoverageStride",
     PopCount(l2prefetchUsefulStride), PopCount(l2demandRequest),

src/main/scala/coupledL2/prefetch/PrefetchReceiver.scala

@@ -31,6 +31,7 @@ case class PrefetchReceiverParams(n: Int = 32) extends PrefetchParameters {
   override val hasPrefetchBit:  Boolean = true
   override val hasPrefetchSrc:  Boolean = true
   override val inflightEntries: Int = n
+  val hasTPPrefetcher: Boolean = true
 }
 
 class PrefetchReceiver()(implicit p: Parameters) extends PrefetchModule {

src/main/scala/coupledL2/prefetch/Prefetcher.scala

@@ -57,6 +57,7 @@ class PrefetchTrain(implicit p: Parameters) extends PrefetchBundle {
   val hit = Bool()
   val prefetched = Bool()
   val pfsource = UInt(PfSource.pfSourceBits.W)
+  val reqsource = UInt(MemReqSource.reqSourceBits.W)
 
   def addr: UInt = Cat(tag, set, 0.U(offsetBits.W))
 }
@@ -123,6 +124,9 @@ class PrefetchQueue(implicit p: Parameters) extends PrefetchModule {
 
 class Prefetcher(implicit p: Parameters) extends PrefetchModule {
   val io = IO(new PrefetchIO)
+  val tpio = IO(new Bundle() {
+    val tpmeta_port = prefetchOpt.map(_ => new tpmetaPortIO)
+  })
   /* io_l2_pf_en:
    * chicken bits for whether L2 prefetchers are enabled
    * it will control BOP and TP prefetchers
@@ -184,6 +188,9 @@ class Prefetcher(implicit p: Parameters) extends PrefetchModule {
       pipe.io.in <> pftQueue.io.deq
       io.req <> pipe.io.out
 
+      // tpmeta interface
+      tp.io.tpmeta_port <> tpio.tpmeta_port.get
+
       XSPerfAccumulate(cacheParams, "prefetch_req_fromSMS", pfRcv.io.req.valid)
       XSPerfAccumulate(cacheParams, "prefetch_req_fromBOP", l2_pf_en && bop.io.req.valid)
       XSPerfAccumulate(cacheParams, "prefetch_req_fromTP", l2_pf_en && tp.io.req.valid)