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log: use XMR instead of boring utils for logging
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@Tang-Haojin
Tang-Haojin committed Sep 13, 2023
1 parent 45bf238 commit 96077ef
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Showing 5 changed files with 75 additions and 46 deletions.
2 changes: 1 addition & 1 deletion HuanCun
Submodule HuanCun updated 9 files
+0 −4 Makefile
+1 −1 Utility
+2 −1 src/main/scala/huancun/HuanCun.scala
+5 −2 src/main/scala/huancun/noninclusive/MSHR.scala
+1 −0 src/main/scala/huancun/noninclusive/SliceCtrl.scala
+7 −2 src/main/scala/huancun/prefetch/PrefetchReceiver.scala
+18 −0 src/main/scala/huancun/prefetch/Prefetcher.scala
+17 −26 src/main/scala/huancun/utils/XSPerfAccumulate.scala
+50 −12 src/test/scala/huancun/TestTop.scala
5 changes: 0 additions & 5 deletions Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,23 +7,18 @@ compile:

test-top-l2:
mill -i CoupledL2.test.runMain coupledL2.TestTop_L2 -td build
mv build/TestTop_L2.v build/TestTop.v

test-top-l2standalone:
mill -i CoupledL2.test.runMain coupledL2.TestTop_L2_Standalone -td build
mv build/TestTop_L2_Standalone.v build/TestTop.v

test-top-l2l3:
mill -i CoupledL2.test.runMain coupledL2.TestTop_L2L3 -td build
mv build/TestTop_L2L3.v build/TestTop.v

test-top-l2l3l2:
mill -i CoupledL2.test.runMain coupledL2.TestTop_L2L3L2 -td build
mv build/TestTop_L2L3L2.v build/TestTop.v

test-top-fullsys:
mill -i CoupledL2.test.runMain coupledL2.TestTop_fullSys -td build
mv build/TestTop_fullSys.v build/TestTop.v

clean:
rm -rf ./build
Expand Down
56 changes: 17 additions & 39 deletions src/main/scala/coupledL2/utils/L2PerfCounterUtils.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,26 +18,22 @@
package coupledL2.utils

import chisel3._
import chisel3.util.experimental.BoringUtils
import coupledL2.L2Param
import utility.ChiselDB
import utility.{ChiselDB, LogPerfHelper, LogPerfIO}

object XSPerfAccumulate {
def apply(params: L2Param, perfName: String, perfCnt: UInt) = {
if (params.enablePerf && !params.FPGAPlatform) {
val logTimestamp = WireInit(0.U(64.W))
val perfClean = WireInit(false.B)
val perfDump = WireInit(false.B)
BoringUtils.addSink(logTimestamp, "logTimestamp")
BoringUtils.addSink(perfClean, "XSPERF_CLEAN")
BoringUtils.addSink(perfDump, "XSPERF_DUMP")
val helper = Module(new LogPerfHelper)
val perfClean = helper.io.clean
val perfDump = helper.io.dump

val counter = RegInit(0.U(64.W))
val next_counter = counter + perfCnt
counter := Mux(perfClean, 0.U, next_counter)

when(perfDump) {
XSPerfPrint(p"$perfName, $next_counter\n")
XSPerfPrint(p"$perfName, $next_counter\n")(helper.io)
}
}
}
Expand All @@ -58,12 +54,9 @@ object XSPerfHistogram {
right_strict: Boolean = false
) = {
if (params.enablePerf && !params.FPGAPlatform) {
val logTimestamp = WireInit(0.U(64.W))
val perfClean = WireInit(false.B)
val perfDump = WireInit(false.B)
BoringUtils.addSink(logTimestamp, "logTimestamp")
BoringUtils.addSink(perfClean, "XSPERF_CLEAN")
BoringUtils.addSink(perfDump, "XSPERF_DUMP")
val helper = Module(new LogPerfHelper)
val perfClean = helper.io.clean
val perfDump = helper.io.dump

// drop each perfCnt value into a bin
val nBins = (stop - start) / step
Expand Down Expand Up @@ -96,7 +89,7 @@ object XSPerfHistogram {
}

when(perfDump) {
XSPerfPrint(p"${perfName}_${binRangeStart}_${binRangeStop}, $counter\n")
XSPerfPrint(p"${perfName}_${binRangeStart}_${binRangeStop}, $counter\n")(helper.io)
}
}
}
Expand All @@ -106,19 +99,16 @@ object XSPerfHistogram {
object XSPerfMax {
def apply(params: L2Param, perfName: String, perfCnt: UInt, enable: Bool) = {
if (params.enablePerf && !params.FPGAPlatform) {
val logTimestamp = WireInit(0.U(64.W))
val perfClean = WireInit(false.B)
val perfDump = WireInit(false.B)
BoringUtils.addSink(logTimestamp, "logTimestamp")
BoringUtils.addSink(perfClean, "XSPERF_CLEAN")
BoringUtils.addSink(perfDump, "XSPERF_DUMP")
val helper = Module(new LogPerfHelper)
val perfClean = helper.io.clean
val perfDump = helper.io.dump

val max = RegInit(0.U(64.W))
val next_max = Mux(enable && (perfCnt > max), perfCnt, max)
max := Mux(perfClean, 0.U, next_max)

when(perfDump) {
XSPerfPrint(p"${perfName}_max, $next_max\n")
XSPerfPrint(p"${perfName}_max, $next_max\n")(helper.io)
}
}
}
Expand Down Expand Up @@ -149,12 +139,6 @@ object XSPerfRolling {
if (params.enablePerf && !params.FPGAPlatform) {
val tableName = perfName + "_rolling_0" // TODO: support naming hart id
val rollingTable = ChiselDB.createTable(tableName, new RollingEntry(), basicDB=true)
val logTimestamp = WireInit(0.U(64.W))
val perfClean = WireInit(false.B)
val perfDump = WireInit(false.B)
ExcitingUtils.addSink(logTimestamp, "logTimestamp")
ExcitingUtils.addSink(perfClean, "XSPERF_CLEAN")
ExcitingUtils.addSink(perfDump, "XSPERF_DUMP")

val xAxisCnt = RegInit(0.U(64.W))
val yAxisCnt = RegInit(0.U(64.W))
Expand Down Expand Up @@ -187,12 +171,6 @@ object XSPerfRolling {
if (params.enablePerf && !params.FPGAPlatform) {
val tableName = perfName + "_rolling_0" // TODO: support naming hart id
val rollingTable = ChiselDB.createTable(tableName, new RollingEntry(), basicDB=true)
val logTimestamp = WireInit(0.U(64.W))
val perfClean = WireInit(false.B)
val perfDump = WireInit(false.B)
ExcitingUtils.addSink(logTimestamp, "logTimestamp")
ExcitingUtils.addSink(perfClean, "XSPERF_CLEAN")
ExcitingUtils.addSink(perfDump, "XSPERF_DUMP")

val xAxisCnt = RegInit(0.U(64.W))
val yAxisCnt = RegInit(0.U(64.W))
Expand Down Expand Up @@ -227,11 +205,11 @@ object TransactionLatencyCounter {
}

object XSPerfPrint {
def apply(fmt: String, data: Bits*): Any =
apply(Printable.pack(fmt, data: _*))
def apply(fmt: String, data: Bits*)(ctrlInfo: LogPerfIO): Any =
apply(Printable.pack(fmt, data: _*))(ctrlInfo)

def apply(pable: Printable): Any = {
val commonInfo = p"[PERF ][time=${GTimer()}] 9527: "
def apply(pable: Printable)(ctrlInfo: LogPerfIO): Any = {
val commonInfo = p"[PERF ][time=${ctrlInfo.timer}] 9527: "
printf(commonInfo + pable)
}
}
Expand Down
56 changes: 56 additions & 0 deletions src/test/scala/TestTop.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ class TestTop_L2()(implicit p: Parameters) extends LazyModule {
* L2
*/

override lazy val desiredName: String = "TestTop"
val delayFactor = 0.5
val cacheParams = p(L2ParamKey)

Expand Down Expand Up @@ -62,6 +63,16 @@ class TestTop_L2()(implicit p: Parameters) extends LazyModule {
l2.node :=* xbar

lazy val module = new LazyModuleImp(this){
val timer = WireDefault(0.U(64.W))
val logEnable = WireDefault(false.B)
val clean = WireDefault(false.B)
val dump = WireDefault(false.B)

dontTouch(timer)
dontTouch(logEnable)
dontTouch(clean)
dontTouch(dump)

master_nodes.zipWithIndex.foreach{
case (node, i) =>
node.makeIOs()(ValName(s"master_port_$i"))
Expand All @@ -77,6 +88,8 @@ class TestTop_L2L3()(implicit p: Parameters) extends LazyModule {
* |
* L3
*/

override lazy val desiredName: String = "TestTop"
val delayFactor = 0.2
val cacheParams = p(L2ParamKey)

Expand Down Expand Up @@ -161,6 +174,16 @@ class TestTop_L2L3()(implicit p: Parameters) extends LazyModule {
l2 :=* xbar

lazy val module = new LazyModuleImp(this) {
val timer = WireDefault(0.U(64.W))
val logEnable = WireDefault(false.B)
val clean = WireDefault(false.B)
val dump = WireDefault(false.B)

dontTouch(timer)
dontTouch(logEnable)
dontTouch(clean)
dontTouch(dump)

master_nodes.zipWithIndex.foreach {
case (node, i) =>
node.makeIOs()(ValName(s"master_port_$i"))
Expand All @@ -178,6 +201,7 @@ class TestTop_L2_Standalone()(implicit p: Parameters) extends LazyModule {
* L3 (fake, used for tl-test with salve)
*/

override lazy val desiredName: String = "TestTop"
val delayFactor = 0.5
val cacheParams = p(L2ParamKey)

Expand Down Expand Up @@ -241,6 +265,16 @@ class TestTop_L2_Standalone()(implicit p: Parameters) extends LazyModule {
l2.node :=* xbar

lazy val module = new LazyModuleImp(this){
val timer = WireDefault(0.U(64.W))
val logEnable = WireDefault(false.B)
val clean = WireDefault(false.B)
val dump = WireDefault(false.B)

dontTouch(timer)
dontTouch(logEnable)
dontTouch(clean)
dontTouch(dump)

master_nodes.zipWithIndex.foreach{
case (node, i) =>
node.makeIOs()(ValName(s"master_port_$i"))
Expand All @@ -259,6 +293,7 @@ class TestTop_L2L3L2()(implicit p: Parameters) extends LazyModule {
* L3
*/

override lazy val desiredName: String = "TestTop"
val delayFactor = 0.2
val cacheParams = p(L2ParamKey)

Expand Down Expand Up @@ -337,6 +372,16 @@ class TestTop_L2L3L2()(implicit p: Parameters) extends LazyModule {
l3.node :=* xbar

lazy val module = new LazyModuleImp(this) {
val timer = WireDefault(0.U(64.W))
val logEnable = WireDefault(false.B)
val clean = WireDefault(false.B)
val dump = WireDefault(false.B)

dontTouch(timer)
dontTouch(logEnable)
dontTouch(clean)
dontTouch(dump)

master_nodes.zipWithIndex.foreach {
case (node, i) =>
node.makeIOs()(ValName(s"master_port_$i"))
Expand All @@ -353,6 +398,7 @@ class TestTop_fullSys()(implicit p: Parameters) extends LazyModule {
* L3
*/

override lazy val desiredName: String = "TestTop"
val delayFactor = 0.2
val cacheParams = p(L2ParamKey)

Expand Down Expand Up @@ -443,6 +489,16 @@ class TestTop_fullSys()(implicit p: Parameters) extends LazyModule {
l3.node :=* l2xbar

lazy val module = new LazyModuleImp(this) {
val timer = WireDefault(0.U(64.W))
val logEnable = WireDefault(false.B)
val clean = WireDefault(false.B)
val dump = WireDefault(false.B)

dontTouch(timer)
dontTouch(logEnable)
dontTouch(clean)
dontTouch(dump)

master_nodes.zipWithIndex.foreach {
case (node, i) =>
node.makeIOs()(ValName(s"master_port_$i"))
Expand Down
2 changes: 1 addition & 1 deletion utility
Submodule utility updated 2 files
+37 −0 src/main/scala/utility/LogPerfHelper.scala
+3 −0 src/main/scala/utility/ResetGen.scala

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