Merge branch 'master' into testtop-chi-cmo

Makefile

@@ -1,16 +1,11 @@
 ISSUE ?= B
-
-TEST_TOP_SUFFIX := UNKNOWN
-ifeq ($(ISSUE), B)
-TEST_TOP_SUFFIX :=
-endif
-ifeq ($(ISSUE), E.b)
-TEST_TOP_SUFFIX := _Eb
-endif
-
-ifeq ($(TEST_TOP_SUFFIX), UNKNOWN)
-$(error "Unknown CHI Issue specified: $(ISSUE)")
-endif
+NUM_CORE ?= 2
+NUM_TL_UL ?= 0
+NUM_SLICE ?= 4
+WITH_CHISELDB ?= 1
+WITH_TLLOG ?= 1
+WITH_CHILOG ?= 1
+FPGA ?= 0
 
 init:
 	git submodule update --init
@@ -19,55 +14,57 @@ init:
 compile:
 	mill -i CoupledL2.compile
 
+CHI_PASS_ARGS = ISSUE=$(ISSUE) NUM_CORE=$(NUM_CORE) NUM_TL_UL=$(NUM_TL_UL) NUM_SLICE=$(NUM_SLICE) \
+			    WITH_CHISELDB=$(WITH_CHISELDB) WITH_TLLOG=$(WITH_TLLOG) WITH_CHILOG=$(WITH_CHILOG) \
+			    FPGA=$(FPGA)
+
 TOP = TestTop
+CHI_TOP_ARGS = --issue $(ISSUE) --core $(NUM_CORE) --tl-ul $(NUM_TL_UL) --bank $(NUM_SLICE) \
+		   	   --chiseldb $(WITH_CHISELDB) --tllog $(WITH_TLLOG) --chilog $(WITH_CHILOG) \
+		       --fpga $(FPGA)
 BUILD_DIR = ./build
 TOP_V = $(BUILD_DIR)/$(TOP).v
 SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(TOP):-o:$(TOP).v.conf
 MEM_GEN = ./scripts/vlsi_mem_gen
 MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
 
-test-top:
+gen-test-top:
 	mill -i CoupledL2.test.runMain coupledL2.$(TOP)_$(SYSTEM) -td $(BUILD_DIR) $(SIM_MEM_ARGS)
 	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(BUILD_DIR)"
 
+gen-test-top-chi:
+	mill -i CoupledL2.test.runMain coupledL2.$(TOP)_$(SYSTEM) -td $(BUILD_DIR) $(SIM_MEM_ARGS) $(CHI_TOP_ARGS)
+	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(BUILD_DIR)"
+
 test-top-l2:
-	$(MAKE) test-top SYSTEM=L2
+	$(MAKE) gen-test-top SYSTEM=L2
 
 test-top-l2standalone:
-	$(MAKE) test-top SYSTEM=L2_Standalone
+	$(MAKE) gen-test-top SYSTEM=L2_Standalone
 
 test-top-l2l3:
-	$(MAKE) test-top SYSTEM=L2L3
+	$(MAKE) gen-test-top SYSTEM=L2L3
 
 test-top-l2l3l2:
-	$(MAKE) test-top SYSTEM=L2L3L2
+	$(MAKE) gen-test-top SYSTEM=L2L3L2
 
 test-top-fullsys:
-	$(MAKE) test-top SYSTEM=fullSys
+	$(MAKE) gen-test-top SYSTEM=fullSys
+
+test-top-chi:
+	$(MAKE) gen-test-top-chi SYSTEM=CHIL2 $(CHI_PASS_ARGS)
 
 test-top-chi-dualcore-0ul:
-	$(MAKE) test-top SYSTEM=CHI_DualCore_0UL$(TEST_TOP_SUFFIX)
+	$(MAKE) gen-test-top-chi SYSTEM=CHIL2 $(CHI_PASS_ARGS) NUM_CORE=2 NUM_TL_UL=0
 
 test-top-chi-dualcore-2ul:
-	$(MAKE) test-top SYSTEM=CHI_DualCore_2UL$(TEST_TOP_SUFFIX)
+	$(MAKE) gen-test-top-chi SYSTEM=CHIL2 $(CHI_PASS_ARGS) NUM_CORE=2 NUM_TL_UL=2
 
 test-top-chi-quadcore-0ul:
-	$(MAKE) test-top SYSTEM=CHI_QuadCore_0UL$(TEST_TOP_SUFFIX)
+	$(MAKE) gen-test-top-chi SYSTEM=CHIL2 $(CHI_PASS_ARGS) NUM_CORE=4 NUM_TL_UL=0
 
 test-top-chi-quadcore-2ul:
-	$(MAKE) test-top SYSTEM=CHI_QuadCore_2UL$(TEST_TOP_SUFFIX)
-
-test-top-chi-octacore-0ul:
-	$(MAKE) test-top SYSTEM=CHI_OctaCore_0UL$(TEST_TOP_SUFFIX)
-
-test-top-chi-octacore-2ul:
-	$(MAKE) test-top SYSTEM=CHI_OctaCore_2UL$(TEST_TOP_SUFFIX)
-
-test-top-chi-hexacore-0ul:
-	$(MAKE) test-top SYSTEM=CHI_HexaCore_0UL$(TEST_TOP_SUFFIX)
-
-test-top-chi-hexacore-2ul:
-	$(MAKE) test-top SYSTEM=CHI_HexaCore_2UL$(TEST_TOP_SUFFIX)
+	$(MAKE) gen-test-top-chi SYSTEM=CHIL2 $(CHI_PASS_ARGS) NUM_CORE=4 NUM_TL_UL=2
 
 clean:
 	rm -rf ./build

src/main/scala/coupledL2/L2Param.scala

@@ -100,6 +100,8 @@ case class L2Param(
   enableMonitor: Boolean = true,
   // TLLog
   enableTLLog: Boolean = true,
+  // CHILog
+  enableCHILog: Boolean = true,
   // TopDown
   elaboratedTopDown: Boolean = true,
   // env

src/main/scala/coupledL2/tl2chi/MMIOBridge.scala

@@ -38,7 +38,7 @@ class MMIOBridge()(implicit p: Parameters) extends LazyModule
     */
   val beuRange = AddressSet(0x38010000, 4096 - 1)
   val peripheralRange = AddressSet(
-    0x0, 0x7fffffff
+    0x0, 0xffffffffffffL
   ).subtract(beuRange)
 
   val mmioNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
@@ -232,7 +232,7 @@ class MMIOBridgeEntry(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CHIL2Mo
   io.pCrd.query.bits.pCrdType := pCrdType
   io.pCrd.query.bits.srcID := srcID
 
-  io.waitOnReadReceipt.foreach(_ := !w_readreceipt.get && (s_txreq || !allowRetry))
+  io.waitOnReadReceipt.foreach(_ := !w_readreceipt.get && s_txreq)
 }
 
 class MMIOBridgeImp(outer: MMIOBridge) extends LazyModuleImp(outer)

src/main/scala/coupledL2/tl2chi/TL2CHICoupledL2.scala

@@ -39,7 +39,7 @@ abstract class TL2CHIL2Module(implicit val p: Parameters) extends Module
 
 class TL2CHICoupledL2(implicit p: Parameters) extends CoupledL2Base {
 
-  val addressRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL)) // TODO: parameterize this
+  val addressRange = Seq(AddressSet(0x00000000L, 0xffffffffffffL)) // TODO: parameterize this
   val managerParameters = TLSlavePortParameters.v1(
     managers = Seq(TLSlaveParameters.v1(
       address = addressRange,

src/main/scala/coupledL2/tl2chi/TXDAT.scala

@@ -69,8 +69,11 @@ class TXDAT(implicit p: Parameters) extends TL2CHIL2Module {
   val inflightCnt = PopCount(Cat(pipeStatus_s3_s5.map(s => s.valid && s.bits.toTXDAT && (s.bits.fromB || s.bits.mshrTask)))) +
     PopCount(Cat(pipeStatus_s2.map(s => s.valid && Mux(s.bits.mshrTask, s.bits.toTXDAT, s.bits.fromB)))) +
     queueCnt
+
+  assert(inflightCnt <= mshrsAll.U, "in-flight overflow at TXDAT")
+
   val noSpaceForSinkBReq = inflightCnt >= mshrsAll.U
-  val noSpaceForMSHRReq = inflightCnt >= (mshrsAll-1).U
+  val noSpaceForMSHRReq = inflightCnt >= (mshrsAll-2).U
 
   io.toReqArb.blockSinkBReqEntrance := noSpaceForSinkBReq
   io.toReqArb.blockMSHRReqEntrance := noSpaceForMSHRReq

src/main/scala/coupledL2/tl2chi/TXREQ.scala

@@ -61,6 +61,9 @@ class TXREQ(implicit p: Parameters) extends TL2CHIL2Module {
 //    pipeStatus_s1.valid.asUInt +
     1.U - s2ReturnCredit.asUInt + //Fix Timing: always take credit and s2 return if not take 
     queueCnt
+
+  assert(inflightCnt <= mshrsAll.U, "in-flight overflow at TXREQ")
+
   val noSpace = inflightCnt >= mshrsAll.U
 
   io.toReqArb.blockMSHRReqEntrance := noSpace

src/main/scala/coupledL2/tl2chi/TXRSP.scala

@@ -59,8 +59,11 @@ class TXRSP(implicit p: Parameters) extends TL2CHIL2Module {
   val inflightCnt = PopCount(Cat(pipeStatus_s3_s5.map(s => s.valid && s.bits.toTXRSP && (s.bits.fromB || s.bits.mshrTask)))) +
     PopCount(Cat(pipeStatus_s2.map(s => s.valid && Mux(s.bits.mshrTask, s.bits.toTXRSP, s.bits.fromB)))) +
     queueCnt
+
+  assert(inflightCnt <= mshrsAll.U, "in-flight overflow at TXRSP")
+
   val noSpaceForSinkBReq = inflightCnt >= mshrsAll.U
-  val noSpaceForMSHRReq = inflightCnt >= (mshrsAll-1).U
+  val noSpaceForMSHRReq = inflightCnt >= (mshrsAll-2).U
 
   io.toReqArb.blockSinkBReqEntrance := noSpaceForSinkBReq
   io.toReqArb.blockMSHRReqEntrance := noSpaceForMSHRReq

src/main/scala/coupledL2/tl2chi/chi/CHILogger.scala

@@ -24,7 +24,7 @@ import freechips.rocketchip.util._
 import scala.collection.immutable.{ListMap, SeqMap}
 import utility.ChiselDB
 
-class CHILogger(name: String, enable: Boolean, flit_as_is: Boolean = false)
+class CHILogger(name: String, enable: Boolean)
                (implicit val p: Parameters) extends Module with HasCHIOpcodes {
 
   val io = IO(new Bundle() {
@@ -35,7 +35,8 @@ class CHILogger(name: String, enable: Boolean, flit_as_is: Boolean = false)
 
   // packed_flit = true: just dump the whole flit as UInt
   // packed_flit = false: separate every field
-  val packed_flit = flit_as_is
+  val packed_flit = !p(CHIIssue).equals(Issue.B)
+  // *NOTICE: (or TODO) Non-packed flit mode for Issue E.b was currently broken.
 
   // ** !! gather all distinct fields from CHI bundles !! **
   val all_bundles = Seq(new CHIREQ, new CHIRSP, new CHIDAT, new CHISNP)
@@ -181,8 +182,15 @@ class CHILogger(name: String, enable: Boolean, flit_as_is: Boolean = false)
 
 object CHILogger {
 
-  def apply(name: String, enable: Boolean = true)(implicit p: Parameters) = {
-    val logger = Module(new CHILogger(name, enable))
+  def apply(name: String, enable: Boolean)(implicit p: Parameters) = {
+    val logger = Module(new CHILogger(name, enable)(p))
+    logger
+  }
+
+  def apply(name: String, issue: String, enable: Boolean)(implicit p: Parameters) = {
+    val logger = Module(new CHILogger(name, enable)(
+      p.alterPartial { case CHIIssue => issue }
+    ))
     logger
   }
 }

src/main/scala/coupledL2/tl2chi/chi/LinkLayer.scala

@@ -177,7 +177,7 @@ class LCredit2Decoupled[T <: Bundle](
 
   assert(!accept || queue.io.enq.ready)
 
-  io.in.lcrdv := lcreditOut
+  io.in.lcrdv := RegNext(lcreditOut, init = false.B)
 
   io.out <> queue.io.deq
   val opcodeElements = queue.io.deq.bits.elements.filter(_._1 == "opcode")
@@ -220,36 +220,37 @@ class Decoupled2LCredit[T <: Bundle](gen: T) extends Module {
     val state = Input(new LinkState())
   })
 
+  val out = Wire(io.out.cloneType)
+
   val state = io.state.state
   val disableFlit = state === LinkStates.STOP || state === LinkStates.ACTIVATE
   val disableLCredit = state === LinkStates.STOP
-  val acceptLCredit = io.out.lcrdv && !disableLCredit
+  val acceptLCredit = out.lcrdv && !disableLCredit
 
   // The maximum number of L-Credits that a receiver can provide is 15.
   val lcreditsMax = 15
   val lcreditPool = RegInit(0.U(log2Up(lcreditsMax).W))
 
   val returnLCreditValid = !io.in.valid && state === LinkStates.DEACTIVATE && lcreditPool =/= 0.U
+  val flitv = io.in.fire || returnLCreditValid
 
   when (acceptLCredit) {
-    when (!io.out.flitv) {
+    when (!flitv) {
       lcreditPool := lcreditPool + 1.U
       assert(lcreditPool + 1.U =/= 0.U, "L-Credit pool overflow")
     }
   }.otherwise {
-    when (io.out.flitv) {
+    when (flitv) {
       lcreditPool := lcreditPool - 1.U
     }
   }
 
   io.in.ready := lcreditPool =/= 0.U && !disableFlit
-  io.out.flitpend := true.B
-  io.out.flitv := io.in.fire || returnLCreditValid
-  io.out.flit := Mux(
-    io.in.valid,
-    Cat(io.in.bits.getElements.map(_.asUInt)),
-    0.U // LCrdReturn
-  )
+
+  io.out <> out
+  out.flitpend := RegNext(true.B, init = false.B) // TODO
+  out.flitv := RegNext(flitv, init = false.B)
+  out.flit := RegEnable(Mux(io.in.valid, Cat(io.in.bits.getElements.map(_.asUInt)), 0.U /* LCrdReturn */), flitv)
 }
 
 object Decoupled2LCredit {