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fix(TL2CHICoupledL2): denial of access must assert corrupt (#239)
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* fix(MMIOBridge): denial of access must assert corrupt

According to TileLink spec, when a response message that carries data is
denied, it must mark all beats of message as corrupt.

* fix(TL2CHICoupledL2): handle denied and corrupt in cacheable space
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linjuanZ authored Sep 12, 2024
1 parent 084df8f commit 4ded089
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Showing 8 changed files with 30 additions and 23 deletions.
3 changes: 3 additions & 0 deletions src/main/scala/coupledL2/Common.scala
Original file line number Diff line number Diff line change
Expand Up @@ -71,6 +71,8 @@ class TaskBundle(implicit p: Parameters) extends L2Bundle
val sourceId = UInt(sourceIdBits.W) // tilelink sourceID
val bufIdx = UInt(bufIdxBits.W) // idx of SinkC buffer
val needProbeAckData = Bool() // only used for SinkB reqs, whether L3 needs probeAckData
val denied = Bool()
val corrupt = Bool()

// MSHR may send Release(Data) or Grant(Data) or ProbeAck(Data) through Main Pipe
val mshrTask = Bool() // is task from mshr
Expand Down Expand Up @@ -227,6 +229,7 @@ class RespInfoBundle(implicit p: Parameters) extends L2Bundle
val dbID = chiOpt.map(_ => UInt(DBID_WIDTH.W))
val resp = chiOpt.map(_ => UInt(RESP_WIDTH.W))
val pCrdType = chiOpt.map(_ => UInt(PCRDTYPE_WIDTH.W))
val respErr = chiOpt.map(_ => UInt(RESPERR_WIDTH.W))
}

class RespBundle(implicit p: Parameters) extends L2Bundle {
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4 changes: 2 additions & 2 deletions src/main/scala/coupledL2/GrantBuffer.scala
Original file line number Diff line number Diff line change
Expand Up @@ -90,9 +90,9 @@ class GrantBuffer(implicit p: Parameters) extends L2Module {
d.size := offsetBits.U
d.source := task.sourceId
d.sink := grant_id
d.denied := false.B
d.denied := task.denied
d.data := data
d.corrupt := false.B
d.corrupt := task.corrupt
d.echo.lift(IsKeywordKey).foreach(_ := false.B)
d
}
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6 changes: 4 additions & 2 deletions src/main/scala/coupledL2/tl2chi/MMIOBridge.scala
Original file line number Diff line number Diff line change
Expand Up @@ -136,8 +136,10 @@ class MMIOBridgeEntry(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CHIL2Mo
when (rxdat.fire) {
w_compdata := true.B
rdata := rxdat.bits.data
denied := denied || rxdat.bits.respErr === RespErrEncodings.NDERR
corrupt := corrupt || rxdat.bits.respErr === RespErrEncodings.DERR
val nderr = rxdat.bits.respErr === RespErrEncodings.NDERR
val derr = rxdat.bits.respErr === RespErrEncodings.DERR
denied := denied || nderr
corrupt := corrupt || derr || nderr
}
when (io.resp.fire) {
s_resp := true.B
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16 changes: 16 additions & 0 deletions src/main/scala/coupledL2/tl2chi/MSHR.scala
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@ import org.chipsalliance.cde.config.Parameters
import coupledL2.prefetch.{PfSource, PrefetchTrain}
import coupledL2.tl2chi.CHICohStates._
import coupledL2.tl2chi.CHIChannel
import coupledL2.tl2chi.RespErrEncodings._
import coupledL2.MetaData._
import coupledL2._

Expand Down Expand Up @@ -99,6 +100,8 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
val pcrdtype = RegInit(0.U(PCRDTYPE_WIDTH.W))
val gotRetryAck = RegInit(false.B)
val gotPCrdGrant = RegInit(false.B)
val denied = RegInit(false.B)
val corrupt = RegInit(false.B)
val metaChi = ParallelLookUp(
Cat(meta.dirty, meta.state),
Seq(
Expand Down Expand Up @@ -133,6 +136,8 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
srcid := 0.U
dbid := 0.U
pcrdtype := 0.U
denied := false.B
corrupt := false.B

retryTimes := 0.U
backoffTimer := 0.U
Expand Down Expand Up @@ -595,6 +600,8 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
mp_grant.size := 0.U(msgSizeBits.W)
mp_grant.bufIdx := 0.U(bufIdxBits.W)
mp_grant.needProbeAckData := false.B
mp_grant.denied := denied
mp_grant.corrupt := corrupt
mp_grant.mshrTask := true.B
mp_grant.mshrId := io.id
mp_grant.way := dirResult.way
Expand Down Expand Up @@ -843,6 +850,8 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {

// RXDAT
when (rxdat.valid) {
val nderr = rxdat.bits.respErr.getOrElse(OK) === NDERR
val derr = rxdat.bits.respErr.getOrElse(OK) === DERR
when (rxdat.bits.chiOpcode.get === DataSepResp) {
require(beatSize == 2) // TODO: This is ugly
beatCnt := beatCnt + 1.U
Expand All @@ -852,6 +861,8 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
gotT := rxdatIsU || rxdatIsU_PD
gotDirty := gotDirty || rxdatIsU_PD
gotGrantData := true.B
denied := denied || nderr
corrupt := corrupt || derr || nderr
}

when (rxdat.bits.chiOpcode.get === CompData) {
Expand All @@ -864,16 +875,20 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
gotGrantData := true.B
dbid := rxdat.bits.dbID.getOrElse(0.U)
homenid := rxdat.bits.homeNID.getOrElse(0.U)
denied := denied || nderr
corrupt := corrupt || derr || nderr
}
}

// RXRSP for dataless
when (rxrsp.valid) {
val nderr = rxrsp.bits.respErr.getOrElse(OK) === NDERR
when (rxrsp.bits.chiOpcode.get === RespSepData) {
state.w_grantfirst := true.B
srcid := rxrsp.bits.srcID.getOrElse(0.U)
homenid := rxrsp.bits.srcID.getOrElse(0.U)
dbid := rxrsp.bits.dbID.getOrElse(0.U)
denied := denied || nderr
}

when (rxrsp.bits.chiOpcode.get === Comp) {
Expand All @@ -884,6 +899,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
state.w_grant := req.off === 0.U || rxrsp.bits.last // TODO? why offset?
gotT := rxrspIsU
gotDirty := false.B
denied := denied || nderr
}

// There is a pending Evict transaction waiting for the Comp resp
Expand Down
1 change: 1 addition & 0 deletions src/main/scala/coupledL2/tl2chi/RXDAT.scala
Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,7 @@ class RXDAT(implicit p: Parameters) extends TL2CHIL2Module {
io.in.respInfo.dbID.get := io.out.bits.dbID
io.in.respInfo.resp.get := io.out.bits.resp
io.in.respInfo.pCrdType.get := DontCare // RXDAT Channel does not have a pCrdType field
io.in.respInfo.respErr.get := io.out.bits.respErr

io.out.ready := true.B

Expand Down
1 change: 1 addition & 0 deletions src/main/scala/coupledL2/tl2chi/RXRSP.scala
Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,7 @@ class RXRSP(implicit p: Parameters) extends TL2CHIL2Module {
io.in.respInfo.dbID.get := io.out.bits.dbID
io.in.respInfo.resp.get := io.out.bits.resp
io.in.respInfo.pCrdType.get := io.out.bits.pCrdType
io.in.respInfo.respErr.get := io.out.bits.respErr
io.in.respInfo.last := true.B

io.out.ready := true.B
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2 changes: 2 additions & 0 deletions src/main/scala/coupledL2/tl2tl/MainPipe.scala
Original file line number Diff line number Diff line change
Expand Up @@ -231,6 +231,8 @@ class MainPipe(implicit p: Parameters) extends L2Module {
ms_task.snpHitReleaseWithData := false.B
ms_task.snpHitReleaseIdx := 0.U
ms_task.cmoTask := false.B
ms_task.denied := false.B
ms_task.corrupt := false.B

/* ======== Resps to SinkA/B/C Reqs ======== */
val sink_resp_s3 = WireInit(0.U.asTypeOf(Valid(new TaskBundle))) // resp for sinkA/B/C request that does not need to alloc mshr
Expand Down
20 changes: 1 addition & 19 deletions src/main/scala/coupledL2/tl2tl/SinkB.scala
Original file line number Diff line number Diff line change
Expand Up @@ -35,38 +35,20 @@ class SinkB(implicit p: Parameters) extends L2Module {

def fromTLBtoTaskBundle(b: TLBundleB): TaskBundle = {
val task = Wire(new TaskBundle)
task := 0.U.asTypeOf(new TaskBundle)
task.channel := "b010".U
task.txChannel := 0.U
task.tag := parseAddress(b.address)._1
task.set := parseAddress(b.address)._2
task.off := parseAddress(b.address)._3
task.alias.foreach(_ := 0.U)
task.vaddr.foreach(_ := 0.U)
task.isKeyword.foreach(_ := false.B)
task.opcode := b.opcode
task.param := b.param
task.size := b.size
task.sourceId := 0.U(sourceIdBits.W)
task.bufIdx := 0.U(bufIdxBits.W)
task.needProbeAckData := b.data(0) // TODO: parameterize this
task.mshrTask := false.B
task.mshrId := 0.U(mshrBits.W)
task.aliasTask.foreach(_ := false.B)
task.useProbeData := false.B
task.mshrRetry := false.B
task.fromL2pft.foreach(_ := false.B)
task.needHint.foreach(_ := false.B)
task.dirty := false.B
task.way := 0.U(wayBits.W)
task.meta := 0.U.asTypeOf(new MetaEntry)
task.metaWen := false.B
task.tagWen := false.B
task.dsWen := false.B
task.wayMask := Fill(cacheParams.ways, "b1".U)
task.reqSource := MemReqSource.NoWhere.id.U // Ignore
task.replTask := false.B
task.mergeA := false.B
task.aMergeTask := 0.U.asTypeOf(new MergeTaskBundle)
task.snpHitRelease := false.B
task.snpHitReleaseWithData := false.B
task.snpHitReleaseIdx := 0.U
Expand Down

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