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chose: remove stale comments
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@linjuanZ
linjuanZ committed Sep 6, 2024
1 parent 2524095 commit 08fdfb5
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Showing 4 changed files with 4 additions and 180 deletions.
34 changes: 0 additions & 34 deletions src/main/scala/coupledL2/tl2chi/MMIOBridge.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -66,10 +66,6 @@ class MMIOBridgeEntry(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CHIL2Mo
val resp = DecoupledIO(new TLBundleD(edge.bundle))
val chi = new DecoupledNoSnpPortIO
val id = Input(UInt())
// val pCrdQuery = Output(ValidIO(new Bundle() {
// val pCrdType = UInt(PCRDTYPE_WIDTH.W)
// }))
// val pCrdGrant = Input(Bool())
val pCrd = new PCrdQueryBundle
val waitOnReadReceipt = Option.when(needRR)(Output(Bool()))
})
Expand Down Expand Up @@ -263,30 +259,6 @@ class MMIOBridgeImp(outer: MMIOBridge) extends LazyModuleImp(outer)
/**
* Protocol Retry
*/
// val pCrdValids = RegInit(VecInit(Seq.fill(mmioBridgeSize)(false.B)))
// val pCrdTypes = Reg(Vec(mmioBridgeSize, UInt(PCRDTYPE_WIDTH.W)))
// val pCrdInsertOH = PriorityEncoderOH(pCrdValids.map(!_))
// val isPCrdGrant = io.rx.rsp.bits.opcode === PCrdGrant
// val pCrdMatch = Wire(Vec(mmioBridgeSize, Vec(mmioBridgeSize, Bool())))
// val pCrdMatchEntryVec = pCrdMatch.map(_.asUInt.orR)
// val pCrdMatchEntryOH = PriorityEncoderOH(pCrdMatchEntryVec)
// val pCrdFreeOH = ParallelPriorityMux(
// pCrdMatchEntryVec,
// pCrdMatch.map(x => VecInit(PriorityEncoderOH(x)))
// )

// when (io.rx.rsp.valid && isPCrdGrant) {
// pCrdValids.zip(pCrdInsertOH).foreach { case (v, insert) =>
// when (insert) { v := true.B }
// assert(!(v && insert), "P-Credit overflow")
// }
// pCrdTypes.zip(pCrdInsertOH).foreach { case (t, insert) =>
// when (insert) { t := io.rx.rsp.bits.pCrdType }
// }
// }
// pCrdFreeOH.zip(pCrdValids).foreach { case (free, v) =>
// when (free) { v := false.B }
// }
val isPCrdGrant = io_pCrd.map(_.grant).reduce(_ || _)
io_pCrd.zip(entries).foreach(x => x._1 <> x._2.io.pCrd)

Expand All @@ -301,12 +273,6 @@ class MMIOBridgeImp(outer: MMIOBridge) extends LazyModuleImp(outer)
entry.io.chi.rx.rsp.bits := io.rx.rsp.bits

entry.io.id := i.U

// pCrdMatch(i) := VecInit(pCrdValids.zip(pCrdTypes).map { case (v, t) =>
// entry.io.pCrdQuery.valid && v &&
// entry.io.pCrdQuery.bits.pCrdType === t
// })
// entry.io.pCrdGrant := pCrdMatchEntryOH(i)
}

val txreqArb = Module(new Arbiter(chiselTypeOf(io.tx.req.bits), mmioBridgeSize))
Expand Down
13 changes: 4 additions & 9 deletions src/main/scala/coupledL2/tl2chi/MSHR.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -43,11 +43,9 @@ class MSHRTasks(implicit p: Parameters) extends TL2CHIL2Bundle {
}

class MSHRResps(implicit p: Parameters) extends TL2CHIL2Bundle {
val sinkC = Flipped(ValidIO(new RespInfoBundle))
val rxrsp = Flipped(ValidIO(new RespInfoBundle))
val rxdat = Flipped(ValidIO(new RespInfoBundle))
// val rxrsp = new RespBundle()
// val rxdat = new RespBundle()
val sinkC = Flipped(ValidIO(new RespInfoBundle))
val rxrsp = Flipped(ValidIO(new RespInfoBundle))
val rxdat = Flipped(ValidIO(new RespInfoBundle))
}

class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
Expand Down Expand Up @@ -113,10 +111,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
Cat( true.B, TRUNK) -> UD,
Cat( true.B, TIP) -> UD
))
//for PCrdGrant info. search
// io.waitPCrdInfo.valid := gotRetryAck && !gotPCrdGrant
// io.waitPCrdInfo.srcID.get := srcid
// io.waitPCrdInfo.pCrdType.get := pcrdtype

io.pCrd.query.valid := gotRetryAck && !gotPCrdGrant
io.pCrd.query.bits.pCrdType := pcrdtype
io.pCrd.query.bits.srcID := srcid
Expand Down
101 changes: 0 additions & 101 deletions src/main/scala/coupledL2/tl2chi/MSHRCtl.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -27,14 +27,6 @@ import freechips.rocketchip.tilelink.TLMessages._
import coupledL2.prefetch.PrefetchTrain
import coupledL2._

// PCrd info for MSHR Retry
// class PCrdInfo(implicit p: Parameters) extends TL2CHIL2Bundle
// {
// val valid = Bool()
// val srcID = chiOpt.map(_ => UInt(SRCID_WIDTH.W))
// val pCrdType = chiOpt.map(_ => UInt(PCRDTYPE_WIDTH.W))
// }

class MSHRCtl(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
val io = IO(new Bundle() {
/* interact with req arb */
Expand Down Expand Up @@ -91,8 +83,6 @@ class MSHRCtl(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes
val msStatus = topDownOpt.map(_ => Vec(mshrsAll, ValidIO(new MSHRStatus)))

/* to Slice Top for pCrd info.*/
// val waitPCrdInfo = Output(Vec(mshrsAll, new PCrdInfo))
// val matchPCrdInfo = Input(UInt(mshrsAll.W))
val pCrd = Vec(mshrsAll, new PCrdQueryBundle)
})

Expand Down Expand Up @@ -120,92 +110,6 @@ class MSHRCtl(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes
mshrSelector.io.idle := mshrs.map(m => !m.io.status.valid)
io.toMainPipe.mshr_alloc_ptr := OHToUInt(selectedMSHROH)

// /*
// when PCrdGrant, give credit to one entry that:
// 1. got RetryAck and not Reissued
// 2. match srcID and PCrdType
// 3. use Round-Robin arbiter if multi-entry match
// */
// val isPCrdGrant = io.resps.rxrsp.valid && (io.resps.rxrsp.respInfo.chiOpcode.get === PCrdGrant)
// val isPCrdGrantReg = RegNext(isPCrdGrant)
// val waitPCrdInfo = Wire(Vec(mshrsAll, new PCrdInfo))
// val timeOutPri = VecInit(Seq.fill(16)(false.B))
// val timeOutSel = WireInit(false.B)
// val pCrdPri = VecInit(Seq.fill(16)(false.B))
// val pArb = Module(new RRArbiterInit(UInt(), mshrsAll))

// val matchPCrdGrantPre = VecInit(pCrdPri.zip(io.matchPCrdInfo.asBools.map(_ & io.resps.rxrsp.valid)).map{
// case(a,b) => !a & b
// })
// val matchPCrdGrant = RegNext(matchPCrdGrantPre)

// pArb.io.in.zipWithIndex.foreach {
// case (in, i) =>
// in.valid := matchPCrdGrant(i)
// in.bits := 0.U
// }
// pArb.io.out.ready := true.B

// val pCrdOH = VecInit(UIntToOH(pArb.io.chosen).asBools)
// val pCrdFixPri = VecInit(pCrdOH zip matchPCrdGrant map {case(a,b) => a && b})

// // timeout protect
// val counter = RegInit(VecInit(Seq.fill(mshrsAll)(0.U((log2Ceil(mshrsAll)+1).W))))

// for(i <- 0 until 16) {
// when(matchPCrdGrant(i)) {
// when(!timeOutSel && pCrdFixPri(i) || timeOutPri(i)) {
// counter(i):=0.U
// }.otherwise {
// counter(i):= counter(i) + 1.U
// }
// }
// }
// val timeOutOH = PriorityEncoderOH(counter.map(_>=12.U) zip matchPCrdGrant map {case(a,b) => a&&b})
// timeOutPri := VecInit(timeOutOH)

// timeOutSel := timeOutPri.reduce(_|_)
// pCrdPri := Mux(timeOutSel, timeOutPri, pCrdFixPri)

// dontTouch (timeOutPri)
// dontTouch (timeOutSel)
// dontTouch (pCrdOH)
// dontTouch (pCrdFixPri)
// dontTouch (pCrdPri)

// /* when PCrdGrant come before RetryAck, 16 entry CAM used to:
// 1. save {srcID, PCrdType}
// 2. Broadcast to each MSHR for seaching when RetryAck
// */
// // val pCamValids = RegInit(VecInit(Seq.fill(mshrsAll){ false.B }))
// val pCam = RegInit(VecInit(Seq.fill(mshrsAll)(0.U.asTypeOf(new PCrdInfo))))
// val pCamPri = Wire(UInt(5.W))
// val pCamValids = Cat(pCam.map(_.valid))
// val enqIdx = PriorityEncoder(~pCamValids.asUInt)

// // when (isPCrdGrant && !pCrdIsWait.orR){
// when (isPCrdGrant){
// pCam(enqIdx).valid := true.B
// pCam(enqIdx).srcID.get := io.resps.rxrsp.respInfo.srcID.get
// pCam(enqIdx).pCrdType.get := io.resps.rxrsp.respInfo.pCrdType.get
// }

// pCamPri := 16.U //out of range of mshrAll

// //each entry zip pCam
// for (i <- 0 until mshrsAll) { //entry
// when (waitPCrdInfo(i).valid) {
// for (j <- 0 until mshrsAll) { //pCam
// when (pCam(j).valid &&
// waitPCrdInfo(i).srcID.get === pCam(j).srcID.get &&
// waitPCrdInfo(i).srcID.get === pCam(j).pCrdType.get) {
// pCam(j).valid := false.B
// pCamPri := i.U
// }
// }
// }
// }

/* SinkC(release) search MSHR with PA */
val resp_sinkC_match_vec = mshrs.map { mshr =>
val status = mshr.io.status.bits
Expand Down Expand Up @@ -239,12 +143,7 @@ class MSHRCtl(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes
m.io.aMergeTask.bits := io.aMergeTask.bits.task

io.pCrd(i) <> m.io.pCrd

// waitPCrdInfo(i) := m.io.waitPCrdInfo
// m.io.pCrdPri := isPCrdGrantReg && pCrdPri(i)
}
// /* mshrc -> L2Top to wait pCrd */
// io.waitPCrdInfo <> waitPCrdInfo

/* Reserve 1 entry for SinkB */
io.toReqArb.blockC_s1 := false.B
Expand Down
36 changes: 0 additions & 36 deletions src/main/scala/coupledL2/tl2chi/TL2CHICoupledL2.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -155,42 +155,6 @@ class TL2CHICoupledL2(implicit p: Parameters) extends CoupledL2Base {
val rxrsp = Wire(DecoupledIO(new CHIRSP))
val rxrspIsMMIO = rxrsp.bits.txnID.head(1).asBool
val isPCrdGrant = rxrsp.valid && rxrsp.bits.opcode === PCrdGrant
// val pArb = Module(new RRArbiterInit(UInt(), banks))
// val pMatch = VecInit(Seq.fill(banks)(Module(new PCrdGrantMatcher(mshrsAll)).io))
// val pCrdSliceID = Wire(UInt(log2Ceil(banks).W))
// /*
// when PCrdGrant, give credit to one Slice that:
// 1. got RetryAck and not Reissued
// 2. match srcID and PCrdType
// 3. use Round-Robin arbiter if multi-Slice match
// */
// val matchPCrdGrant = Wire(Vec(banks, UInt(mshrsAll.W)))
// val validCounts = Wire(Vec(banks, UInt(log2Ceil(mshrsAll+1).W)))
// slices.zipWithIndex.foreach { case (s, i) =>
// pMatch(i).io_waitPCrdInfo := s.io_waitPCrdInfo
// pMatch(i).rxrsp.bits.srcID := rxrsp.bits.srcID
// pMatch(i).rxrsp.bits.pCrdType := rxrsp.bits.pCrdType
// pMatch(i).isPCrdGrant := isPCrdGrant

// matchPCrdGrant(i) := pMatch(i).matchPCrdGrant
// s.io_matchPCrdInfo := matchPCrdGrant(i)
// validCounts(i) := PopCount(s.io_waitPCrdInfo.map(_.valid))
// }

// val pCrdIsWait = VecInit(matchPCrdGrant.map(_.asUInt.orR)).asUInt
// val pCrdSliceIDOH = UIntToOH(pCrdSliceID)
// val onlyValidraw = Cat(validCounts.map(count => count === 1.U)).asUInt
// val onlyValid = Reverse(onlyValidraw)
// val pCrdSliceHit = pCrdSliceIDOH & pCrdIsWait & onlyValid
// val pCrdCancel = RegNext(pCrdSliceHit) & onlyValid

// pArb.io.in.zipWithIndex.foreach {
// case (in, i) =>
// in.valid := pCrdIsWait(i) && !pCrdCancel(i)
// in.bits := 0.U
// }
// pArb.io.out.ready := true.B
// pCrdSliceID := pArb.io.chosen

// PCredit arbitration
val (mmioQuerys, mmioGrants) = mmio.io_pCrd.map { case x => (x.query, x.grant) }.unzip
Expand Down

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