OSCPU · poemonsense · Sep 7, 2025 · Sep 7, 2025
diff --git a/difftest b/difftest
diff --git a/src/test/scala/TopMain.scala b/src/test/scala/TopMain.scala
@@ -43,7 +43,7 @@ object TopMain extends App {
     require(target != "")
     target.substring(info.length()+1)
   }
-  val newArgs = DifftestModule.parseArgs(args)
+  val (newArgs, firtoolOptions) = DifftestModule.parseArgs(args)
   val board = parseArgs("BOARD", newArgs)
   val core = parseArgs("CORE", newArgs)
 
@@ -75,7 +75,7 @@ object TopMain extends App {
   var exe_args = newArgs.filter{
     value => value.forall(char => char!='=')
   }
-  (new ChiselStage).execute(newArgs, Seq(generator)
+  (new ChiselStage).execute(newArgs, Seq(generator) ++ firtoolOptions
     :+ CIRCTTargetAnnotation(CIRCTTarget.SystemVerilog)
     :+ FirtoolOption("--disable-annotation-unknown")
   )
+65 −15		.github/workflows/main.yml
+11 −10		.github/workflows/nightly.yml
+52 −8		Makefile
+2 −12		README.md
+7 −16		build.sc
+5 −0		config/config.cpp
+5 −3		config/config.h
+19 −4		fpga.mk
+120 −0		galaxsim.mk
+7 −7		gsim.mk
+13 −23		palladium.mk
+42 −0		pdb.mk
+17 −0		scripts/fpga_sim/ci.sh
+13 −0		scripts/st_tools/interface.py
+29 −0		src/main/scala/Coverage.scala
+21 −17		src/main/scala/DPIC.scala
+17 −5		src/main/scala/Difftest.scala
+17 −11		src/main/scala/Gateway.scala
+17 −8		src/main/scala/Squash.scala
+2 −2		src/main/scala/common/LogPerfControl.scala
+43 −17		src/main/scala/common/Mem.scala
+10 −16		src/main/scala/common/WiringControl.scala
+0 −41		src/main/scala/util/Compatibility.scala
+0 −48		src/main/scala/util/DataMirror.scala
+2 −8		src/main/scala/util/VerificationExtractor.scala
+34 −0		src/test/csrc/common/common.cpp
+6 −0		src/test/csrc/common/common.h
+3 −2		src/test/csrc/common/coverage.cpp
+1 −1		src/test/csrc/common/dut.h
+1 −7		src/test/csrc/common/elfloader.h
+0 −1		src/test/csrc/common/flash.cpp
+1 −1		src/test/csrc/common/main.cpp
+67 −43		src/test/csrc/common/mpool.cpp
+47 −23		src/test/csrc/common/mpool.h
+2 −5		src/test/csrc/common/perf.cpp
+1 −3		src/test/csrc/common/perf.h
+0 −1		src/test/csrc/common/ram.cpp
+44 −32		src/test/csrc/difftest/difftest.cpp
+62 −22		src/test/csrc/difftest/difftest.h
+0 −2		src/test/csrc/difftest/goldenmem.cpp
+102 −66		src/test/csrc/fpga/fpga_main.cpp
+120 −0		src/test/csrc/fpga/serial_port.cpp
+58 −0		src/test/csrc/fpga/serial_port.h
+85 −39		src/test/csrc/fpga/xdma.cpp
+59 −31		src/test/csrc/fpga/xdma.h
+145 −0		src/test/csrc/fpga_sim/xdma_sim.cpp
+26 −0		src/test/csrc/fpga_sim/xdma_sim.h
+3 −1		src/test/csrc/gsim/unimpl-blackbox.cpp
+95 −0		src/test/csrc/plugin/xspdb/cpp/export.cpp
+36 −0		src/test/csrc/plugin/xspdb/cpp/export.h
+79 −0		src/test/csrc/plugin/xspdb/swig.i
+108 −122		src/test/csrc/vcs/vcs_main.cpp
+106 −310		src/test/csrc/verilator/emu.cpp
+27 −41		src/test/csrc/verilator/emu.h
+5 −7		src/test/csrc/verilator/gsim.cpp.inc
+75 −0		src/test/csrc/verilator/gsim.h
+22 −0		src/test/csrc/verilator/simulator.cpp
+132 −0		src/test/csrc/verilator/simulator.h
+1 −1		src/test/csrc/verilator/snapshot.cpp.inc
+1 −3		src/test/csrc/verilator/snapshot.h
+115 −0		src/test/csrc/verilator/verilator.cpp.inc
+104 −0		src/test/csrc/verilator/verilator.h
+64 −0		src/test/csrc/verilator/waveform.cpp.inc
+55 −0		src/test/csrc/verilator/waveform.h
+1 −1		src/test/scala/DifftestMain.scala
+1 −1		src/test/scala/DifftestTop.scala
+48 −0		src/test/vsrc/fpga_sim/xdma_axi.v
+44 −0		src/test/vsrc/fpga_sim/xdma_clock.v
+184 −0		src/test/vsrc/fpga_sim/xdma_ctrl.v
+62 −0		src/test/vsrc/fpga_sim/xdma_wrapper.v
+9 −8		src/test/vsrc/vcs/DifftestEndpoint.sv
+23 −2		src/test/vsrc/vcs/top.v
+4 −17		vcs.mk
+9 −6		verilator.mk