i.MX OCOTP improvements #7594
i.MX OCOTP improvements #7594
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Question: Is it really required to keep the 80-char limit? |
Generally, yes, but there are exceptions for prints. Problems with following the limit usually stem from unwieldy local variables. If there's a place apart from prints where you think an exception is needed, feel free to point it out. |
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Okay thanks and good to know. I asked because most projects have lifted this hard requirement to 100-chars. |
The 80-char limit is for the sake of readability; A standard terminal window is 80 characters wide. I don't see a problem with breaking those lines; better than the wrapping at 80. |
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@bith3ad Can you please tell me how you tested writing of fuse and did you update the ocotp pta also for this ? |
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Please fix the style issues and use only C-style comments (no |
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This pull request has been marked as a stale pull request because it has been open (more than) 30 days with no activity. Remove the stale label or add a comment, otherwise this pull request will automatically be closed in 5 days. Note, that you can always re-open a closed issue at any time. |
The Cortex-A9 inside of the i.MX6Q/D/QP/DL/S/SL/SLL SoCs has no generic timer support, but all variants should boot with 792Mhz out of the boot rom. Set the Generic Timer configuration variable to n and implement the required plat_get_freq() call to support the udelay() calls. Signed-off-by: Rouven Czerwinski <[email protected]>
The i.MX8MP has an OCOTP_CTRL_ADDR field which is 8-bit wide compared to all other current supported i.MX SoCs. Due to the larger ADDR field all bits shifted by 1 bit. Also make some minor style fixes while on it by replacing the mix of tabs and spaces with tabs-only. Signed-off-by: Marco Felsch <[email protected]>
According the reference manuals the ERROR bit should be cleared by writing a '1' to the OCOTP_CTRL_CLR register and not by writing to the OCOTP_CTRL direct. Signed-off-by: Marco Felsch <[email protected]>
Check the g_base_addr and g_ocotp before do the first access. Signed-off-by: Marco Felsch <[email protected]>
bith3ad
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Use the ARM architected timer instead of assuming that the CPU is running at 500MHz and the poll takes around ~20us. Signed-off-by: Marco Felsch <[email protected]>
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Tested this one on i.MX8MM and able to write the fuse, will be testing on other platforms too. |
Make use of the udelay() function and the newly added OCOTP_OP_BUSY_TIMEOUT_US to align platforms which don't support architected timers, like i.MX6Q with the ones that support architected timers. udelay() can be used since we have added the plat_get_freq() support for all i.MX SoCs which don't support architected timers previously. While on it drop the dsb() since the memory is mapped as non-cacheable device-memory. So there is no need for a data barrier. Keep the isb() to not send use-less register loads. Signed-off-by: Marco Felsch <[email protected]>
This adds the support to burn fuses on i.MX8M SoCs. This approach assume that the IPG clock is running at 66.67 MHz which is AHB/2 (AHB max. clock = 133 MHz). Due to lack of HW I added only the i.MX8M support. Signed-off-by: Marco Felsch <[email protected]>
Reuse the same write functions as for i.MX8M SoC since they seem to use the same OCOTP IP core according to the reference manual. Signed-off-by: Rouven Czerwinski <[email protected]>
Reuse the same write function as the other i.MX6 SoCs since the OCOTP IP is the same. i.MX6ULL just has fewer fuse banks than i.MX6UL. Signed-off-by: Philipp Zabel <[email protected]>
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6 participants
Hi,
this v2 is based on the review I received on #7453. Unfortunately I couldn't follow the contributors guideline and had to open a new PR because the PR got closed by the bot. Therefore I added the changes but squashed them directly.