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Merge remote-tracking branch 'origin/GP-2812_ghidorahrex_armv5_regres…
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…sion_fix--SQUASHED' into patch
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@ghidra1
ghidra1 committed Nov 10, 2022
2 parents db92f74 + a0babb4 commit 3cf13c2
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Showing 3 changed files with 26 additions and 36 deletions.
38 changes: 19 additions & 19 deletions Ghidra/Processors/ARM/data/languages/ARM.ldefs
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
endian="little"
size="32"
variant="v8"
version="1.105"
version="1.106"
slafile="ARM8_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -29,7 +29,7 @@
endian="little"
size="32"
variant="v8T"
version="1.105"
version="1.106"
slafile="ARM8_le.sla"
processorspec="ARMtTHUMB.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -49,7 +49,7 @@
instructionEndian="little"
size="32"
variant="v8LEInstruction"
version="1.105"
version="1.106"
slafile="ARM8_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -64,7 +64,7 @@
endian="big"
size="32"
variant="v8"
version="1.105"
version="1.106"
slafile="ARM8_be.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -87,7 +87,7 @@
endian="big"
size="32"
variant="v8T"
version="1.105"
version="1.106"
slafile="ARM8_be.sla"
processorspec="ARMtTHUMB.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -104,7 +104,7 @@
endian="little"
size="32"
variant="v7"
version="1.105"
version="1.106"
slafile="ARM7_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -124,7 +124,7 @@
instructionEndian="little"
size="32"
variant="v7LEInstruction"
version="1.105"
version="1.106"
slafile="ARM7_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -139,7 +139,7 @@
endian="big"
size="32"
variant="v7"
version="1.105"
version="1.106"
slafile="ARM7_be.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -157,7 +157,7 @@
endian="little"
size="32"
variant="Cortex"
version="1.105"
version="1.106"
slafile="ARM7_le.sla"
processorspec="ARMCortex.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -177,7 +177,7 @@
endian="big"
size="32"
variant="Cortex"
version="1.105"
version="1.106"
slafile="ARM7_be.sla"
processorspec="ARMCortex.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -196,7 +196,7 @@
endian="little"
size="32"
variant="v6"
version="1.105"
version="1.106"
slafile="ARM6_le.sla"
processorspec="ARMt_v6.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -216,7 +216,7 @@
endian="big"
size="32"
variant="v6"
version="1.105"
version="1.106"
slafile="ARM6_be.sla"
processorspec="ARMt_v6.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -236,7 +236,7 @@
endian="little"
size="32"
variant="v5t"
version="1.105"
version="1.106"
slafile="ARM5t_le.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -254,7 +254,7 @@
endian="big"
size="32"
variant="v5t"
version="1.105"
version="1.106"
slafile="ARM5t_be.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -272,7 +272,7 @@
endian="little"
size="32"
variant="v5"
version="1.105"
version="1.106"
slafile="ARM5_le.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
Expand Down Expand Up @@ -304,7 +304,7 @@
endian="little"
size="32"
variant="v4t"
version="1.105"
version="1.106"
slafile="ARM4t_le.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -321,7 +321,7 @@
endian="big"
size="32"
variant="v4t"
version="1.105"
version="1.106"
slafile="ARM4t_be.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -338,7 +338,7 @@
endian="little"
size="32"
variant="v4"
version="1.105"
version="1.106"
slafile="ARM4_le.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
Expand All @@ -358,7 +358,7 @@
endian="big"
size="32"
variant="v4"
version="1.105"
version="1.106"
slafile="ARM4_be.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
Expand Down
9 changes: 3 additions & 6 deletions Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
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Original file line number Diff line number Diff line change
Expand Up @@ -1024,11 +1024,8 @@ RtGotoCheck: is Rt1215 {}
#


@if defined(VERSION_6T2) || defined(VERSION_7)
# Ensure that the recursive rule for ARMcond is applied for assembly
# Ensure that the condition check phase has been completed
with : ARMcondCk=1 {
@endif


:adc^CheckInIT_CZNO^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x105 & Rm0305 & Rd0002 & CheckInIT_CZNO
{
Expand Down Expand Up @@ -5291,6 +5288,6 @@ Pcrel: [cloc,Rm0003] is Rm0003 & thc0404=1 [ cloc = inst_next; ]
{
HintYield();
}
@endif #VERSION_6T2 || VERSION_7

} # End with : ARMcondCk=1
@endif # VERSION_6T2 || VERSION_7
} # End with : ARMcondCk=1
15 changes: 4 additions & 11 deletions Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc
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Original file line number Diff line number Diff line change
Expand Up @@ -1522,19 +1522,13 @@ SRSMode: "sys" is srsMode=23 & c0004 { export *[const]:1 c0004; }
SRSMode: "#"^srsMode is srsMode { export *[const]:1 srsMode; }
@endif # VERSION_6

# Add a hat instruction to set the ARMcond context variable which
# tells whether this is a legal conditional instruction (for v7 and
# later).

@if defined(VERSION_6T2) || defined(VERSION_7)
:^instruction is ARMcondCk=0 & itmode=0 & TMode=0 & (bit31=0|bit30=0|bit29=0|bit28=0) & instruction [ ARMcondCk=1; ARMcond=1; ] {}
# Perform ARMcond check phase and set ARMcond context variable
:^instruction is $(AMODE) & ARMcondCk=0 & (bit31=0|bit30=0|bit29=0|bit28=0) & instruction [ ARMcondCk=1; ARMcond=1; ] {}
:^instruction is ARMcondCk=0 & instruction [ ARMcondCk=1; ARMcond=0; ] {}

# Ensure one of the recursive rules above is applied for assembly
# Ensure that the condition check phase has been completed
with : ARMcondCk=1 {

@endif

#################################################
#
# Include the SIMD/VFP instructions before the
Expand Down Expand Up @@ -6466,6 +6460,5 @@ armEndianNess: "BE" is c0031=0xf1010200 { export 1:1; }
#}


@if defined(VERSION_6T2) || defined(VERSION_7)
} # End with : ARMcondCk=1
@endif

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