[STF] Abstract logical data

[caugonnet]

Description

To improve CUDASTF modularity, it should be possible to describe abstract logical data which do not manage data allocations or transfers, letting users manage it but still get the benefits of automated management of asynchrony.

Checklist

• New or existing tests cover these changes.
• The documentation is up to date with these changes.

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[caugonnet]

/ok to test

[caugonnet]

/ok to test

[caugonnet]

/ok to test

[caugonnet]

/ok to test

[caugonnet]

/ok to test

[caugonnet]

/ok to test

[github-actions]

🟩 CI finished in 37m 09s: Pass: 100%/26 | Total: 5h 17m | Avg: 12m 12s | Max: 20m 50s | Hits: 92%/312

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👃 Inspect Changes

Modifications in project?

	Project
	CCCL Infrastructure
	libcu++
	CUB
	Thrust
+/-	CUDA Experimental
	python
	CCCL C Parallel Library
	Catch2Helper

Modifications in project or dependencies?

	Project
	CCCL Infrastructure
	libcu++
	CUB
	Thrust
+/-	CUDA Experimental
	python
	CCCL C Parallel Library
	Catch2Helper

🏃‍ Runner counts (total jobs: 26)

#	Runner
18	linux-amd64-cpu16
4	linux-arm64-cpu16
2	windows-amd64-cpu16
2	linux-amd64-gpu-v100-latest-1