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Clsotog/coresight mmap #36

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Clsotog/coresight mmap #36

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5dfc765
NVIDIA: SAUCE: ACPI/HMAT: Move HMAT messages to pr_debug()
clsotog Dec 6, 2024
7a69914
coresight: Make language around "activated" sinks consistent
clsotog Dec 17, 2024
0db9216
coresight: Remove ops callback checks
clsotog Dec 17, 2024
406ca4a
coresight: Move mode to struct coresight_device
clsotog Dec 17, 2024
ebaefb2
coresight: Remove the 'enable' field.
clsotog Dec 17, 2024
02021a3
coresight: Move all sysfs code to sysfs file
clsotog Dec 17, 2024
4961242
coresight: Remove atomic type from refcnt
clsotog Dec 17, 2024
c0e83ee
coresight: Remove unused stubs
clsotog Dec 17, 2024
e7267c4
coresight: Add explicit member initializers to coresight_dev_type
clsotog Dec 17, 2024
a6e9475
coresight: Add helper for atomically taking the device
clsotog Dec 17, 2024
c6f794a
coresight: Add a helper for getting csdev->mode
clsotog Dec 17, 2024
16de9b3
coresight: Add helper for setting csdev->mode
clsotog Dec 17, 2024
1fa138a
perf auxtrace: Allow number of queues to be specified
clsotog Dec 17, 2024
487c77b
perf cs-etm: Print error for new PERF_RECORD_AUX_OUTPUT_HW_ID versions
clsotog Dec 17, 2024
453a3e9
libperf cpumap: Add any, empty and min helpers
clsotog Dec 17, 2024
db9a529
perf arm-spe/cs-etm: Directly iterate CPU maps
clsotog Dec 17, 2024
7107d51
perf cs-etm: Use struct perf_cpu as much as possible
clsotog Dec 17, 2024
4a5ad3a
perf cs-etm: Create decoders after both AUX and HW_ID search passes
clsotog Dec 17, 2024
df62e7d
perf: cs-etm: Allocate queues for all CPUs
clsotog Dec 17, 2024
5cd028b
perf: cs-etm: Move traceid_list to each queue
clsotog Dec 17, 2024
8e7954e
perf: cs-etm: Create decoders based on the trace ID mappings
clsotog Dec 17, 2024
2a04cc8
perf: cs-etm: Only save valid trace IDs into files
clsotog Dec 17, 2024
0e43848
perf: cs-etm: Support version 0.1 of HW_ID packets
clsotog Dec 17, 2024
912e16d
perf: cs-etm: Print queue number in raw trace dump
clsotog Dec 17, 2024
7410fad
coresight: Remove unused ETM Perf stubs
clsotog Dec 17, 2024
c92e32e
coresight: Clarify comments around the PID of the sink owner
clsotog Dec 17, 2024
eb17203
coresight: Move struct coresight_trace_id_map to common header
clsotog Dec 17, 2024
d66e0d3
coresight: Expose map arguments in trace ID API
clsotog Dec 17, 2024
aa79b48
coresight: Make CPU id map a property of a trace ID map
clsotog Dec 17, 2024
a3b7871
coresight: Use per-sink trace ID maps for Perf sessions
clsotog Dec 18, 2024
ff79951
coresight: Remove pending trace ID release mechanism
clsotog Dec 18, 2024
c4707e7
coresight: Emit sink ID in the HW_ID packets
clsotog Dec 18, 2024
267fef2
coresight: Make trace ID map spinlock local to the map
clsotog Dec 18, 2024
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24 changes: 12 additions & 12 deletions drivers/acpi/numa/hmat.c
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Original file line number Diff line number Diff line change
Expand Up @@ -412,9 +412,9 @@ static __init int hmat_parse_locality(union acpi_subtable_headers *header,
return -EINVAL;
}

pr_info("Locality: Flags:%02x Type:%s Initiator Domains:%u Target Domains:%u Base:%lld\n",
hmat_loc->flags, hmat_data_type(type), ipds, tpds,
hmat_loc->entry_base_unit);
pr_debug("Locality: Flags:%02x Type:%s Initiator Domains:%u Target Domains:%u Base:%lld\n",
hmat_loc->flags, hmat_data_type(type), ipds, tpds,
hmat_loc->entry_base_unit);

inits = (u32 *)(hmat_loc + 1);
targs = inits + ipds;
Expand All @@ -425,9 +425,9 @@ static __init int hmat_parse_locality(union acpi_subtable_headers *header,
value = hmat_normalize(entries[init * tpds + targ],
hmat_loc->entry_base_unit,
type);
pr_info(" Initiator-Target[%u-%u]:%u%s\n",
inits[init], targs[targ], value,
hmat_data_type_suffix(type));
pr_debug(" Initiator-Target[%u-%u]:%u%s\n",
inits[init], targs[targ], value,
hmat_data_type_suffix(type));

hmat_update_target(targs[targ], inits[init],
mem_hier, type, value);
Expand Down Expand Up @@ -455,9 +455,9 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header,
}

attrs = cache->cache_attributes;
pr_info("Cache: Domain:%u Size:%llu Attrs:%08x SMBIOS Handles:%d\n",
cache->memory_PD, cache->cache_size, attrs,
cache->number_of_SMBIOShandles);
pr_debug("Cache: Domain:%u Size:%llu Attrs:%08x SMBIOS Handles:%d\n",
cache->memory_PD, cache->cache_size, attrs,
cache->number_of_SMBIOShandles);

target = find_mem_target(cache->memory_PD);
if (!target)
Expand Down Expand Up @@ -516,9 +516,9 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade
}

if (hmat_revision == 1)
pr_info("Memory (%#llx length %#llx) Flags:%04x Processor Domain:%u Memory Domain:%u\n",
p->reserved3, p->reserved4, p->flags, p->processor_PD,
p->memory_PD);
pr_debug("Memory (%#llx length %#llx) Flags:%04x Processor Domain:%u Memory Domain:%u\n",
p->reserved3, p->reserved4, p->flags, p->processor_PD,
p->memory_PD);
else
pr_info("Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
p->flags, p->processor_PD, p->memory_PD);
Expand Down
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