Host IR: make stream synchronization non blocking #3608
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samnordmann
commented
Dec 18, 2024
| @@ -196,6 +197,8 @@ Communicator::Communicator( | |||
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| NVFUSER_CUDA_RT_SAFE_CALL(cudaSetDevice(local_rank_)); | |||
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It's been a long time I suspected this was going to be required at some point. Anyway, this is a recommended (if not required) practice. Without it, cudaEventRecord throws cudaErrorInvalidResourceHandle in a multi-GPU scenario.
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wujingyue
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Dec 19, 2024
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samnordmann
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Jan 13, 2025
…lap: AG+GEMM layout (#3606) Stacked on top of - [x] #3608 - [x] #3605 # What Lower a MatmulOp sharded on the first inner axis into a pipelined AG+GEMM algorithm achieving fine grained overlap. We introduce a new parallel type `Stream` to account for this scheduling. More precisely, this patch enables lowering the fusion: ``` TensorView* a = makeContigTensor(4); //[S, DIDx(D), M/(S*d), K] TensorView* b = makeContigTensor(2); //[K, N] TensorView* c = matmul(a, b); //[S, D, M/(S*D), N] fusion->addInput(a); fusion->addInput(b); fusion->addOutput(c); auto mesh = DeviceMesh::createForNumDevices(D); a->setDeviceMesh(mesh); b->setDeviceMesh(mesh); c->setDeviceMesh(mesh); a->axis(1)->parallelize(ParallelType::DIDx); c->axis(0)->parallelize(ParallelType::Stream); ``` to the Host Ir program (obtained from dump, using `NVFUSER_DUMP=host_ir`) ``` %HostIrContainer { (T0_g_float[iS0{i0}, ideviceIdx.x1{i2}, iS2{i3}, iS3{i4}] (DeviceMesh{0 1 2 3 4 5 6 7}), T1_g_float[iS4{i5}, iS5{i6}] (DeviceMesh{0 1 2 3 4 5 6 7})) -> (T2_g_float[iStream6{i0}, iS7{i2}, iS8{i3}, iS9{i6}, rS10{i4}] (DeviceMesh{0 1 2 3 4 5 6 7})) : GetCurrentStream into Stream 0 T3_g_float[iS11{i0}, iS12{i2}, iS13{i3}, iS14{i4}] (DeviceMesh{0 1 2 3 4 5 6 7}) = ALLOCATE(buffer=T3_g_float[iS11{i0}, iS12{i2}, iS13{i3}, iS14{i4}] (DeviceMesh{0 1 2 3 4 5 6 7}), mem_type=global, size=( ( ( i0 * i2 ) * i3 ) * i4 ), zero_init=false, resets_to_zero=fals e) T2_g_float[iStream6{i0}, iS7{i2}, iS8{i3}, iS9{i6}, rS10{i4}] (DeviceMesh{0 1 2 3 4 5 6 7}) = ALLOCATE(buffer=T2_g_float[iStream6{i0}, iS7{i2}, iS8{i3}, iS9{i6}, rS10{i4}] (DeviceMesh{0 1 2 3 4 5 6 7}), mem_type=global, size=( ( ( i0 * i2 ) * i3 ) * i6 ), zero_init=fals e, resets_to_zero=false) FOR i104 in iS0{i0}: SetCurrentStream to Stream ( i104 % numberOfStreams ) T4_l_float[ideviceIdx.x15{i2}, iS16{i3}, iS17{i4}] (DeviceMesh{0 1 2 3 4 5 6 7}) = select( T0_g_float[iS0{i0}, ideviceIdx.x1{i2}, iS2{i3}, iS3{i4}] (DeviceMesh{0 1 2 3 4 5 6 7}), axis = iS0{i0}, index = i104 ) T5_l_float[iS18{i2}, iS19{i3}, iS20{i4}] (DeviceMesh{0 1 2 3 4 5 6 7}) = select( T3_g_float[iS11{i0}, iS12{i2}, iS13{i3}, iS14{i4}] (DeviceMesh{0 1 2 3 4 5 6 7}), axis = iS11{i0}, index = i104 ) Communication 46 (type=Allgather, team=(0 1 2 3 4 5 6 7), input=T4_l_float[ideviceIdx.x15{i2}, iS16{i3}, iS17{i4}] (DeviceMesh{0 1 2 3 4 5 6 7}), output=T5_l_float[iS18{i2}, iS19{i3}, iS20{i4}] (DeviceMesh{0 1 2 3 4 5 6 7})) Wait Communication 46 T6_l_float[iS21{i2}, iS22{i3}, iS23{i6}] (DeviceMesh{0 1 2 3 4 5 6 7}) = select( T2_g_float[iStream6{i0}, iS7{i2}, iS8{i3}, iS9{i6}, rS10{i4}] (DeviceMesh{0 1 2 3 4 5 6 7}), axis = iStream6{i0}, index = i104 ) T6_l_float[iS21{i2}, iS22{i3}, iS23{i6}] (DeviceMesh{0 1 2 3 4 5 6 7}) = matmul(T5_l_float[iS18{i2}, iS19{i3}, iS20{i4}] (DeviceMesh{0 1 2 3 4 5 6 7}), T1_g_float[iS4{i5}, iS5{i6}] (DeviceMesh{0 1 2 3 4 5 6 7})) SetCurrentStream to Stream 0 Synchronize Stream ( i104 % numberOfStreams ) } // %HostIrContainer ``` The nsight profile shows that we do achieve overlap, in a way that is comparable to the Aten overlap experiments 
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What
Make stream synchronization non-blocking from the CPU point of view
Why
Needed for achieving overlap in
before this patch:
after this patch
How
Before this patch, the host IR
Synchronizewould callc10::synchronize()on the cuda stream, which makes the CPU blocks until stream completion. With this patch, we synchronize the current stream with a given stream through acudaEventand the APIcudaStreamWaitEvent.