RISC-V CPU

A simple 32-bit RISC-V CPU core that supports

• the RV32I Base Integer Instruction Set
• the "Zicntr" extension
• the "Zmmul" extension, via an accelerator running in a faster clock domain
• some of the "Zicsr" extension, including cycle, time and instret
• some of the privileged instruction set, like timer interrupts and exceptions

The design is written in SystemVerilog. Design verification is done using UVM-SystemC, with Verilator as the simulator, CRAVE as the constrained randomization environment, and FC4SC as the functional coverage collector.

Technical specification

Design verification document

Applications have been successfully run on a softcore CPU in an FPGA and in a verilator simulation with an emulated UART interface. They include

• CoreMark
• a simple FreeRTOS program

Repository structure

• doc/: documentation, including the technical specification and design verification document
• dv/
  • cpu/: design verification in C++ with UVM-SystemC
    • sc_main.cpp: 'top level' testbench
    • cpu_util.*: common utility
    • other: UVM-SystemC classes
    • DV Doc
    • Simulation details
  • mul/: simple SystemVerilog testbench
• rtl/: design in SystemVerilog
  • cpu.sv: CPU design
  • cpu.svh: definitions
  • config.svh: configurations
  • mul.sv: multiplier with safe clock domain crossing
  • dual_port_ram.sv: mock memory for simulation
  • uart*.sv: UART modules with configurable baud rate, data bit size, stop bit, parity bit, and buffer size
  • mock_uart_rx.sv: mock UART receiver for recording app output during simulation
  • address_decoder.sv: decodes address to RAM or IO
  • top.sv: top level module
  • sim_top.sv: simulation top for running applications in simulation
• src/: applications
  • helloworld/: simple app that prints using UART
  • coremark/: CoreMark
  • shell/: simple interactive shell
  • freertos/: simple FreeRTOS program
  • util.h, util.c: utilities for UART control and CSR reading
  • create_mif: script to create memory initialization files .mif from hexdump output
  • Details
• de1-soc/: port to the DE1-SoC FPGA
  • Quartus project file
  • RAM and PLL generated by Quartus II
  • custom configuration and top-level module
  • memory initialization files
  • Details
• sim/: simulation tools
  • uart_terminal.cpp: used with sim_top to emulate a UART interface to interact with a simulated system
  • Details