- 🎓 I'm a 3rd-year Electronics and Communication Engineering student
- 💡 Passionate about VLSI, Semiconductors, and Digital Logic Design
- ⚙️ Hands-on with tools like Verilog, SystemVerilog, Xilinx Vivado, and ModelSim
- 🌱 Currently learning: ASIC Flow, RTL Design, and Timing Analysis
- 📬 Always open to connect and collaborate on hardware & chip design related projects!
