- π I'm a 3rd-year Electronics and Communication Engineering student
- π‘ Passionate about VLSI, Semiconductors, and Digital Logic Design
- βοΈ Hands-on with tools like Verilog, SystemVerilog, Xilinx Vivado, and ModelSim
- π± Currently learning: ASIC Flow, RTL Design, and Timing Analysis
- π¬ Always open to connect and collaborate on hardware & chip design related projects!
π
Working from home
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