This project introduces a Python framework to (1) manage the files of an embedded hardware/software (HW/SW) codesign project and (2) generate the Verilog code of the hardware components. The flow will use only open-source tools.
An embedded HW/SW project requires that various source files be conveniently organized in a directory tree so that the various EDA tools can run. Typically, makefiles and different scripting languages are employed to drive these tools, which is often a barrier for new developers. The proposed Python framework will raise developer accessibility by providing a single cockpit for the design process.
Hardware Design Languages such as Verilog and VHDL give a lot of flexibility to users. Still, the industry imposes strict linting rules that reverse this flexibility, allowing only a small subset of these languages that ensure sound FPGAs and ASIC designs. Writing HDL code in a lint-friendly fashion is tedious and error-prone.
Py2HWSW solves this problem by generating lint-friendly and portable Verilog code that can be ported seamlessly between FPGA and ASIC flows.
Py2HWSW runs on nix-shell and self-installs when an example is run. Alternatively, manually install the program and all its dependencies listed in the py2hwsw default.nix file.
The Py2HWSW framework's leading usage example is IOb-SoC, a System-on-Chip (SoC) template comprising an open-source RISC-V processor, a memory subsystem, and a UART.
Py2HWSW can generate a user guide with LaTeX using the --py2hwsw_docs argument.
To generate a documentation directory with the user guide sources and build it, run:
py2hwsw --py2hwsw_docs
make -C py2hwsw_docs/document/ buildA prebuilt user guide can be found here.
This project is funded through NGI Zero Core, a fund established by NLnet with financial support from the European Commission's Next Generation Internet program. Learn more at the NLnet project page.
