riscv: avoid compressed instructions #2419
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... and do not throw errors if there are relocs (might be benign)
| @@ -267,8 +268,8 @@ def _assembler(): | |||
| 'ia64': [gas, '-m%ce' % context.endianness[0]], | |||
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| # riscv64-unknown-elf-as supports riscv32 as well as riscv64 | |||
| 'riscv32': [gas, '-march=rv32gc', '-mabi=ilp32'], | |||
| 'riscv64': [gas, '-march=rv64gc', '-mabi=lp64'], | |||
| 'riscv32': [gas, '-march=rv32g', '-mabi=ilp32'], | |||
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This prevents you from using compressed instructions when manually writing shellcode and compiling using asm, no?
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Sure, and therefore I am not very sure about this change. I don't know any way to avoid C and yet allow c.* opcodes.
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I think we thought about adding assembler command line args to context when adding riscv support? Or just asm?
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We could do this like we do with thumb (separate arch) but I doubt whether it is worth it. Maybe we can revisit this one day.
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Would it make sense to make two different archs? That way you could do asm -c riscv32 and asm -c riscv32c or something similar?
... and do not throw errors if there are relocs (might be benign)