Merge pull request #265 from flaviojs/remove-fastcall-asmlinkage

Remove fastcall/asmlinkage.

common/dynamips_common.h

@@ -58,7 +58,6 @@
 #define ARCH_BYTE_ORDER ARCH_LITTLE_ENDIAN
 #elif defined(__i386) || defined(__i386__) || defined(i386)
 #define ARCH_BYTE_ORDER ARCH_LITTLE_ENDIAN
-#define ARCH_REGPARM_SUPPORTED  1
 #elif defined(__x86_64__)
 #define ARCH_BYTE_ORDER ARCH_LITTLE_ENDIAN
 #elif defined(__ia64__)
@@ -79,15 +78,6 @@
 #error Please define your architecture!
 #endif
 
-/* Useful attributes for functions */
-#ifdef ARCH_REGPARM_SUPPORTED
-#define asmlinkage __attribute__((regparm(0)))
-#define fastcall   __attribute__((regparm(3)))
-#else
-#define asmlinkage
-#define fastcall
-#endif
-
 #ifndef _Unused
 /* Function that is never used */
 #define _Unused  __attribute__((unused))

common/ppc32_exec.h

@@ -11,7 +11,7 @@
 /* PowerPC instruction recognition */
 struct ppc32_insn_exec_tag {
    char *name;
-   fastcall int (*exec)(cpu_ppc_t *,ppc_insn_t);
+   int (*exec)(cpu_ppc_t *,ppc_insn_t);
    m_uint32_t mask,value;
    int instr_type;
    m_uint64_t count;
@@ -37,9 +37,9 @@ void ppc32_exec_create_ilt(void);
 void ppc32_dump_stats(cpu_ppc_t *cpu);
 
 /* Execute a page */
-fastcall int ppc32_exec_page(cpu_ppc_t *cpu);
+int ppc32_exec_page(cpu_ppc_t *cpu);
 
 /* Execute a single instruction (external) */
-fastcall int ppc32_exec_single_insn_ext(cpu_ppc_t *cpu,ppc_insn_t insn);
+int ppc32_exec_single_insn_ext(cpu_ppc_t *cpu,ppc_insn_t insn);
 
 #endif

stable/mips64.c

@@ -419,7 +419,7 @@ void mips64_trigger_exception(cpu_mips_t *cpu,u_int exc_code,int bd_slot)
  * Increment count register and trigger the timer IRQ if value in compare 
  * register is the same.
  */
-fastcall void mips64_exec_inc_cp0_cnt(cpu_mips_t *cpu)
+void mips64_exec_inc_cp0_cnt(cpu_mips_t *cpu)
 {
    cpu->cp0_virt_cnt_reg++;
 
@@ -435,7 +435,7 @@ fastcall void mips64_exec_inc_cp0_cnt(cpu_mips_t *cpu)
 }
 
 /* Trigger the Timer IRQ */
-fastcall void mips64_trigger_timer_irq(cpu_mips_t *cpu)
+void mips64_trigger_timer_irq(cpu_mips_t *cpu)
 {
    mips_cp0_t *cp0 = &cpu->cp0;
 
@@ -447,7 +447,7 @@ fastcall void mips64_trigger_timer_irq(cpu_mips_t *cpu)
 }
 
 /* Execute ERET instruction */
-fastcall void mips64_exec_eret(cpu_mips_t *cpu)
+void mips64_exec_eret(cpu_mips_t *cpu)
 {
    mips_cp0_t *cp0 = &cpu->cp0;
 
@@ -467,7 +467,7 @@ fastcall void mips64_exec_eret(cpu_mips_t *cpu)
 }
 
 /* Execute SYSCALL instruction */
-fastcall void mips64_exec_syscall(cpu_mips_t *cpu)
+void mips64_exec_syscall(cpu_mips_t *cpu)
 {
 #if DEBUG_SYSCALL
    printf("MIPS64: SYSCALL at PC=0x%llx (RA=0x%llx)\n"
@@ -482,7 +482,7 @@ fastcall void mips64_exec_syscall(cpu_mips_t *cpu)
 }
 
 /* Execute BREAK instruction */
-fastcall void mips64_exec_break(cpu_mips_t *cpu,u_int code)
+void mips64_exec_break(cpu_mips_t *cpu,u_int code)
 {
    printf("MIPS64: BREAK instruction (code=%u)\n",code);
    mips64_dump_regs(cpu->gen);
@@ -492,15 +492,15 @@ fastcall void mips64_exec_break(cpu_mips_t *cpu,u_int code)
 }
 
 /* Trigger a Trap Exception */
-fastcall void mips64_trigger_trap_exception(cpu_mips_t *cpu)
+void mips64_trigger_trap_exception(cpu_mips_t *cpu)
 {  
    /* XXX TODO: Branch Delay slot */
    printf("MIPS64: TRAP exception, CPU=%p\n",cpu);
    mips64_trigger_exception(cpu,MIPS_CP0_CAUSE_TRAP,0);
 }
 
 /* Trigger IRQs */
-fastcall void mips64_trigger_irq(cpu_mips_t *cpu)
+void mips64_trigger_irq(cpu_mips_t *cpu)
 {
    if (unlikely(cpu->irq_disable)) {
       cpu->irq_pending = 0;
@@ -515,19 +515,19 @@ fastcall void mips64_trigger_irq(cpu_mips_t *cpu)
 }
 
 /* DMFC1 */
-fastcall void mips64_exec_dmfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg)
+void mips64_exec_dmfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg)
 {
    cpu->gpr[gp_reg] = cpu->fpu.reg[cp1_reg];
 }
 
 /* DMTC1 */
-fastcall void mips64_exec_dmtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg)
+void mips64_exec_dmtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg)
 {
    cpu->fpu.reg[cp1_reg] = cpu->gpr[gp_reg];
 }
 
 /* MFC1 */
-fastcall void mips64_exec_mfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg)
+void mips64_exec_mfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg)
 {
    m_int64_t val;
 
@@ -536,13 +536,13 @@ fastcall void mips64_exec_mfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg)
 }
 
 /* MTC1 */
-fastcall void mips64_exec_mtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg)
+void mips64_exec_mtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg)
 {
    cpu->fpu.reg[cp1_reg] = cpu->gpr[gp_reg] & 0xffffffff;
 }
 
 /* Virtual breakpoint */
-fastcall void mips64_run_breakpoint(cpu_mips_t *cpu)
+void mips64_run_breakpoint(cpu_mips_t *cpu)
 {
    cpu_log(cpu->gen,"BREAKPOINT",
            "Virtual breakpoint reached at PC=0x%llx\n",cpu->pc);
@@ -595,7 +595,7 @@ void mips64_remove_breakpoint(cpu_gen_t *cpu,m_uint64_t pc)
 }
 
 /* Debugging for register-jump to address 0 */
-fastcall void mips64_debug_jr0(cpu_mips_t *cpu)
+void mips64_debug_jr0(cpu_mips_t *cpu)
 {
    printf("MIPS64: cpu %p jumping to address 0...\n",cpu);
    mips64_dump_regs(cpu->gen);

stable/mips64.h

@@ -308,7 +308,7 @@ enum {
 typedef struct cpu_mips cpu_mips_t;
 
 /* Memory operation function prototype */
-typedef fastcall void (*mips_memop_fn)(cpu_mips_t *cpu,m_uint64_t vaddr,
+typedef void (*mips_memop_fn)(cpu_mips_t *cpu,m_uint64_t vaddr,
                                        u_int reg);
 
 /* TLB entry definition */
@@ -357,7 +357,7 @@ struct cpu_mips {
    mips64_jit_tcb_t **exec_blk_map;
 
    /* Virtual address to physical page translation */
-   fastcall int (*translate)(cpu_mips_t *cpu,m_uint64_t vaddr,
+   int (*translate)(cpu_mips_t *cpu,m_uint64_t vaddr,
                              m_uint32_t *phys_page);
 
    /* Memory access functions */
@@ -503,25 +503,25 @@ void mips64_trigger_exception(cpu_mips_t *cpu,u_int exc_code,int bd_slot);
  * Increment count register and trigger the timer IRQ if value in compare 
  * register is the same.
  */
-fastcall void mips64_exec_inc_cp0_cnt(cpu_mips_t *cpu);
+void mips64_exec_inc_cp0_cnt(cpu_mips_t *cpu);
 
 /* Trigger the Timer IRQ */
-fastcall void mips64_trigger_timer_irq(cpu_mips_t *cpu);
+void mips64_trigger_timer_irq(cpu_mips_t *cpu);
 
 /* Execute ERET instruction */
-fastcall void mips64_exec_eret(cpu_mips_t *cpu);
+void mips64_exec_eret(cpu_mips_t *cpu);
 
 /* Execute SYSCALL instruction */
-fastcall void mips64_exec_syscall(cpu_mips_t *cpu);
+void mips64_exec_syscall(cpu_mips_t *cpu);
 
 /* Execute BREAK instruction */
-fastcall void mips64_exec_break(cpu_mips_t *cpu,u_int code);
+void mips64_exec_break(cpu_mips_t *cpu,u_int code);
 
 /* Trigger a Trap Exception */
-fastcall void mips64_trigger_trap_exception(cpu_mips_t *cpu);
+void mips64_trigger_trap_exception(cpu_mips_t *cpu);
 
 /* Trigger IRQs */
-fastcall void mips64_trigger_irq(cpu_mips_t *cpu);
+void mips64_trigger_irq(cpu_mips_t *cpu);
 
 /* Set an IRQ */
 void mips64_set_irq(cpu_mips_t *cpu,m_uint8_t irq);
@@ -530,19 +530,19 @@ void mips64_set_irq(cpu_mips_t *cpu,m_uint8_t irq);
 void mips64_clear_irq(cpu_mips_t *cpu,m_uint8_t irq);
 
 /* DMFC1 */
-fastcall void mips64_exec_dmfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
+void mips64_exec_dmfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
 
 /* DMTC1 */
-fastcall void mips64_exec_dmtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
+void mips64_exec_dmtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
 
 /* MFC1 */
-fastcall void mips64_exec_mfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
+void mips64_exec_mfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
 
 /* MTC1 */
-fastcall void mips64_exec_mtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
+void mips64_exec_mtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);
 
 /* Virtual breakpoint */
-fastcall void mips64_run_breakpoint(cpu_mips_t *cpu);
+void mips64_run_breakpoint(cpu_mips_t *cpu);
 
 /* Add a virtual breakpoint */
 int mips64_add_breakpoint(cpu_gen_t *cpu,m_uint64_t pc);
@@ -551,7 +551,7 @@ int mips64_add_breakpoint(cpu_gen_t *cpu,m_uint64_t pc);
 void mips64_remove_breakpoint(cpu_gen_t *cpu,m_uint64_t pc);
 
 /* Debugging for register-jump to address 0 */
-fastcall void mips64_debug_jr0(cpu_mips_t *cpu);
+void mips64_debug_jr0(cpu_mips_t *cpu);
 
 /* Set a register */
 void mips64_reg_set(cpu_gen_t *cpu,u_int reg,m_uint64_t val);

stable/mips64_amd64_trans.c

@@ -418,7 +418,7 @@ static void mips64_emit_memop(mips64_jit_tcb_t *b,int op,int base,int offset,
 }
 
 /* Coprocessor Register transfert operation */
-static void mips64_emit_cp_xfr_op(mips64_jit_tcb_t *b,int rt,int rd,void *f)
+static void mips64_emit_cp_xfr_op(mips64_jit_tcb_t *b,int rt,int rd,void (*f)(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg))
 {
    /* update pc */
    mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
@@ -443,7 +443,7 @@ void mips64_emit_breakpoint(mips64_jit_tcb_t *b)
 }
 
 /* Unknown opcode handler */
-static fastcall void mips64_unknown_opcode(cpu_mips_t *cpu,m_uint32_t opcode)
+static void mips64_unknown_opcode(cpu_mips_t *cpu,m_uint32_t opcode)
 {
    printf("CPU = %p\n",cpu);
 
@@ -465,7 +465,7 @@ static int mips64_emit_unknown(cpu_mips_t *cpu,mips64_jit_tcb_t *b,
 }
 
 /* Invalid delay slot handler */
-static fastcall void mips64_invalid_delay_slot(cpu_mips_t *cpu)
+static void mips64_invalid_delay_slot(cpu_mips_t *cpu)
 {
    printf("MIPS64: invalid instruction in delay slot at 0x%llx (ra=0x%llx)\n",
           cpu->pc,cpu->gpr[MIPS_GPR_RA]);

stable/mips64_cp0.c

@@ -277,37 +277,37 @@ static inline void mips64_cp0_s1_set_reg(cpu_mips_t *cpu,u_int cp0_s1_reg,
 }
 
 /* DMFC0 */
-fastcall void mips64_cp0_exec_dmfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg)
+void mips64_cp0_exec_dmfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg)
 {
    cpu->gpr[gp_reg] = mips64_cp0_get_reg_fast(cpu,cp0_reg);
 }
 
 /* DMTC0 */
-fastcall void mips64_cp0_exec_dmtc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg)
+void mips64_cp0_exec_dmtc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg)
 {
    mips64_cp0_set_reg(cpu,cp0_reg,cpu->gpr[gp_reg]);
 }
 
 /* MFC0 */
-fastcall void mips64_cp0_exec_mfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg)
+void mips64_cp0_exec_mfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg)
 {
    cpu->gpr[gp_reg] = sign_extend(mips64_cp0_get_reg_fast(cpu,cp0_reg),32);
 }
 
 /* MTC0 */
-fastcall void mips64_cp0_exec_mtc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg)
+void mips64_cp0_exec_mtc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg)
 {
    mips64_cp0_set_reg(cpu,cp0_reg,cpu->gpr[gp_reg] & 0xffffffff);
 }
 
 /* CFC0 */
-fastcall void mips64_cp0_exec_cfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg)
+void mips64_cp0_exec_cfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg)
 {
    cpu->gpr[gp_reg] = sign_extend(mips64_cp0_s1_get_reg(cpu,cp0_reg),32);
 }
 
 /* CTC0 */
-fastcall void mips64_cp0_exec_ctc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg)
+void mips64_cp0_exec_ctc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg)
 {
    mips64_cp0_s1_set_reg(cpu,cp0_reg,cpu->gpr[gp_reg] & 0xffffffff);
 }
@@ -491,7 +491,7 @@ void mips64_cp0_map_all_tlb_to_mts(cpu_mips_t *cpu)
 }
 
 /* TLBP: Probe a TLB entry */
-fastcall void mips64_cp0_exec_tlbp(cpu_mips_t *cpu)
+void mips64_cp0_exec_tlbp(cpu_mips_t *cpu)
 {
    mips_cp0_t *cp0 = &cpu->cp0;
    m_uint64_t hi_reg,asid;
@@ -523,7 +523,7 @@ fastcall void mips64_cp0_exec_tlbp(cpu_mips_t *cpu)
 }
 
 /* TLBR: Read Indexed TLB entry */
-fastcall void mips64_cp0_exec_tlbr(cpu_mips_t *cpu)
+void mips64_cp0_exec_tlbr(cpu_mips_t *cpu)
 {
    mips_cp0_t *cp0 = &cpu->cp0;
    tlb_entry_t *entry;
@@ -600,13 +600,13 @@ static inline void mips64_cp0_exec_tlbw(cpu_mips_t *cpu,u_int index)
 }
 
 /* TLBWI: Write Indexed TLB entry */
-fastcall void mips64_cp0_exec_tlbwi(cpu_mips_t *cpu)
+void mips64_cp0_exec_tlbwi(cpu_mips_t *cpu)
 {
    mips64_cp0_exec_tlbw(cpu,cpu->cp0.reg[MIPS_CP0_INDEX]);
 }
 
 /* TLBWR: Write Random TLB entry */
-fastcall void mips64_cp0_exec_tlbwr(cpu_mips_t *cpu)
+void mips64_cp0_exec_tlbwr(cpu_mips_t *cpu)
 {
    mips64_cp0_exec_tlbw(cpu,mips64_cp0_get_random_reg(cpu));
 }

stable/mips64_cp0.h

@@ -21,24 +21,24 @@ u_int mips64_cp0_get_mode(cpu_mips_t *cpu);
 m_uint64_t mips64_cp0_get_reg(cpu_mips_t *cpu,u_int cp0_reg);
 
 /* DMFC0 */
-fastcall void mips64_cp0_exec_dmfc0(cpu_mips_t *cpu,u_int gp_reg,
+void mips64_cp0_exec_dmfc0(cpu_mips_t *cpu,u_int gp_reg,
                                     u_int cp0_reg);
 
 /* DMTC0 */
-fastcall void mips64_cp0_exec_dmtc0(cpu_mips_t *cpu,u_int gp_reg,
+void mips64_cp0_exec_dmtc0(cpu_mips_t *cpu,u_int gp_reg,
                                     u_int cp0_reg);
 
 /* MFC0 */
-fastcall void mips64_cp0_exec_mfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg);
+void mips64_cp0_exec_mfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg);
 
 /* MTC0 */
-fastcall void mips64_cp0_exec_mtc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg);
+void mips64_cp0_exec_mtc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg);
 
 /* CFC0 */
-fastcall void mips64_cp0_exec_cfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg);
+void mips64_cp0_exec_cfc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg);
 
 /* CTC0 */
-fastcall void mips64_cp0_exec_ctc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg);
+void mips64_cp0_exec_ctc0(cpu_mips_t *cpu,u_int gp_reg,u_int cp0_reg);
 
 /* TLB lookup */
 int mips64_cp0_tlb_lookup(cpu_mips_t *cpu,m_uint64_t vaddr,mts_map_t *res);
@@ -47,16 +47,16 @@ int mips64_cp0_tlb_lookup(cpu_mips_t *cpu,m_uint64_t vaddr,mts_map_t *res);
 void mips64_cp0_map_all_tlb_to_mts(cpu_mips_t *cpu);
 
 /* TLBP: Probe a TLB entry */
-fastcall void mips64_cp0_exec_tlbp(cpu_mips_t *cpu);
+void mips64_cp0_exec_tlbp(cpu_mips_t *cpu);
 
 /* TLBR: Read Indexed TLB entry */
-fastcall void mips64_cp0_exec_tlbr(cpu_mips_t *cpu);
+void mips64_cp0_exec_tlbr(cpu_mips_t *cpu);
 
 /* TLBWI: Write Indexed TLB entry */
-fastcall void mips64_cp0_exec_tlbwi(cpu_mips_t *cpu);
+void mips64_cp0_exec_tlbwi(cpu_mips_t *cpu);
 
 /* TLBWR: Write Random TLB entry */
-fastcall void mips64_cp0_exec_tlbwr(cpu_mips_t *cpu);
+void mips64_cp0_exec_tlbwr(cpu_mips_t *cpu);
 
 /* Raw dump of the TLB */
 void mips64_tlb_raw_dump(cpu_gen_t *cpu);