test deca

.gitmodules

@@ -4,3 +4,6 @@
 [submodule "rtl/jt49"]
 	path = rtl/jt49
 	url = [email protected]:jotego/jt49.git
+[submodule "DeMiSTify"]
+	path = DeMiSTify
+	url = [email protected]:DECAfpga/DeMiSTify.git

Makefile

@@ -0,0 +1,37 @@
+DEMISTIFYPATH=DeMiSTify
+
+PROJECT=ORIC
+BOARD=
+
+all: submodules vbcc firmware init compile tns
+
+submodules: $(DEMISTIFYPATH)/Makefile
+
+.PHONY: vbcc
+vbcc:
+	make -C $(DEMISTIFYPATH)/EightThirtyTwo/ vbcc
+
+$(DEMISTIFYPATH)/DeMiSTify/Makefile:
+	git submodule update --init --recursive
+
+.PHONY: firmware
+firmware: submodules
+	make -C firmware -f ../$(DEMISTIFYPATH)/Scripts/firmware.mk DEMISTIFYPATH=../$(DEMISTIFYPATH)
+
+.PHONY: init
+init:
+	make -f $(DEMISTIFYPATH)/Makefile DEMISTIFYPATH=$(DEMISTIFYPATH) PROJECTS=$(PROJECT) BOARD=$(BOARD) init 
+
+.PHONY: compile
+compile:
+	make -f build_id.mk
+	make -f $(DEMISTIFYPATH)/Makefile DEMISTIFYPATH=$(DEMISTIFYPATH) PROJECTS=$(PROJECT) BOARD=$(BOARD) compile
+
+.PHONY: clean
+clean:
+	make -f $(DEMISTIFYPATH)/Makefile DEMISTIFYPATH=$(DEMISTIFYPATH) PROJECTS=$(PROJECT) BOARD=$(BOARD) clean
+
+.PHONY: tns
+tns:
+	grep -r Design-wide\ TNS fpga/*
+

Oric.qip

@@ -0,0 +1,19 @@
+set_global_assignment -name QIP_FILE  [file join $::quartus(qip_path) rtl/jt49/hdl/jt49.qip]
+set_global_assignment -name QIP_FILE  [file join $::quartus(qip_path) mist-modules/mist.qip]
+set_global_assignment -name VHDL_FILE  [file join $::quartus(qip_path) rtl/oricatmos.vhd]
+set_global_assignment -name SYSTEMVERILOG_FILE  [file join $::quartus(qip_path) rtl/sdram.sv]
+set_global_assignment -name VHDL_FILE  [file join $::quartus(qip_path) rtl/microdisc.vhd]
+set_global_assignment -name SYSTEMVERILOG_FILE  [file join $::quartus(qip_path) rtl/wd1793.sv]
+set_global_assignment -name VHDL_FILE  [file join $::quartus(qip_path) rtl/T65/T65_Pack.vhd]
+set_global_assignment -name VHDL_FILE  [file join $::quartus(qip_path) rtl/T65/T65_MCode.vhd]
+set_global_assignment -name VHDL_FILE  [file join $::quartus(qip_path) rtl/T65/T65_ALU.vhd]
+set_global_assignment -name VHDL_FILE  [file join $::quartus(qip_path) rtl/T65/T65.vhd]
+set_global_assignment -name VHDL_FILE  [file join $::quartus(qip_path) rtl/rom/MICRODIS.vhd]
+set_global_assignment -name VHDL_FILE  [file join $::quartus(qip_path) rtl/rom/BASIC10.vhd]
+set_global_assignment -name VHDL_FILE  [file join $::quartus(qip_path) rtl/rom/BASIC11A.vhdl]
+set_global_assignment -name SYSTEMVERILOG_FILE  [file join $::quartus(qip_path)  Oric.sv]
+set_global_assignment -name VHDL_FILE  [file join $::quartus(qip_path) rtl/ula.vhd]
+set_global_assignment -name VHDL_FILE  [file join $::quartus(qip_path) rtl/m6522.vhd]
+set_global_assignment -name VHDL_FILE  [file join $::quartus(qip_path) rtl/video.vhd]
+set_global_assignment -name SYSTEMVERILOG_FILE  [file join $::quartus(qip_path) rtl/keyboard.sv]
+set_global_assignment -name CDF_FILE output_files/Chain1.cdf]

Oric.sv

@@ -8,6 +8,8 @@ module OricAtmos_MiST(
    output        VGA_VS,
    output        LED,
 
+	input         RESET_N,
+
    input         UART_RXD,
    output        UART_TXD,
 
@@ -89,14 +91,14 @@ reg         old_disk_enable;
 
 assign      disk_enable = status[6];
 assign      rom = ~status[3] ;
-wire        stereo = status[9:8];
+wire [1:0]  stereo = status[9:8];
 
 assign      LED = fdd_ready;
 
 always @(posedge clk_24) begin
 	old_rom <= rom;
 	old_disk_enable <= disk_enable;
-	reset <= (!pll_locked | status[0] | buttons[1] | old_rom != rom | old_disk_enable != disk_enable);
+	reset <= (!pll_locked | status[0] | buttons[0] | old_rom != rom | old_disk_enable != disk_enable);
 end
 
 pll pll (

build_id.mk

@@ -0,0 +1,7 @@
+DEMISTIFYPATH=DeMiSTify
+include $(DEMISTIFYPATH)/site.mk
+
+.PHONY: build_id.v
+build_id.v: mist/build_id_verilog.tcl
+	$(Q13)/quartus_sh -t mist/build_id_verilog.tcl
+

mist/Oric_MiST.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 14:32:28  October 06, 2018
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "14:32:28  October 06, 2018"
+
+# Revisions
+
+PROJECT_REVISION = "Oric_MiST"

mist/Oric_MiST.qsf

@@ -0,0 +1,132 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 21:40:59  July 23, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Oric_MiST_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:11:53  MARCH 09, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:build_id.tcl"
+
+
+# Changes for SiDi FPGA
+# =====================
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SPI_SCK
+
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name SEARCH_PATH roms/ -tag from_archive
+set_global_assignment -name SEARCH_PATH src/ -tag from_archive
+set_global_assignment -name SEARCH_PATH src/MC6522/ -tag from_archive
+set_global_assignment -name SEARCH_PATH src/RAM/ -tag from_archive
+set_global_assignment -name SEARCH_PATH src/T6502/ -tag from_archive
+set_global_assignment -name SEARCH_PATH src/ps2kybrd/ -tag from_archive
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY OricAtmos_MiST
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# ----------------------------
+# start ENTITY(OricAtmos_MiST)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(OricAtmos_MiST)
+# --------------------------
+set_instance_assignment -name IO_STANDARD "2.5 V" -to UART_RXD
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/oric.stp
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "NORMAL COMPILATION"
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF
+
+
+source pines.qip
+source files.qip
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top