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Removed submodule
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@rampa069
rampa069 committed Mar 15, 2020
1 parent 4badfd0 commit a63ac69
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3 changes: 3 additions & 0 deletions .gitmodules
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@@ -0,0 +1,3 @@
[submodule "fdc1772-verilator"]
path = fdc1772-verilator
url = [email protected]:gyurco/fdc1772-verilator.git
1 change: 1 addition & 0 deletions fdc1772-verilator
Submodule fdc1772-verilator added at 338b13
132 changes: 98 additions & 34 deletions mist/data_io.v
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Expand Up @@ -26,90 +26,154 @@ module data_io
input clk_sys,
input SPI_SCK,
input SPI_SS2,
input SPI_SS4,
input SPI_DI,
input SPI_DO, // yes, SPI_DO is input when SS4 active

input clkref_n, // assert ioctl_wr one cycle after clkref stobe (negative active)

// ARM -> FPGA download
output reg ioctl_download = 0, // signal indicating an active download
output reg [7:0] ioctl_index, // menu index used to upload the file
output ioctl_wr,
output reg ioctl_wr, // strobe indicating ioctl_dout valid
output reg [24:0] ioctl_addr,
output reg [7:0] ioctl_dout
);

parameter START_ADDR = 25'd0;
parameter ROM_DIRECT_UPLOAD = 0;

/////////////////////////////// DOWNLOADING ///////////////////////////////

reg [7:0] data_w;
reg [24:0] addr_w;
reg [7:0] data_w2 = 0;
reg rclk = 0;
reg rclk2 = 0;
reg addr_reset = 0;

reg downloading_reg = 0;
reg [7:0] index_reg = 0;

localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
localparam DIO_FILE_TX = 8'h53;
localparam DIO_FILE_TX_DAT = 8'h54;
localparam DIO_FILE_INDEX = 8'h55;

// data_io has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS2) begin
reg [6:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [3:0] cnt;
reg [24:0] addr;

if(SPI_SS2) cnt <= 0;
else begin
rclk <= 0;

// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};

// increase target address after write
if(rclk) addr <= addr + 1'd1;

// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 1'd1;
// count 0-7 8-15 8-15 ...
if(cnt != 15) cnt <= cnt + 1'd1;
else cnt <= 8;

// finished command byte
if(cnt == 7) cmd <= {sbuf, SPI_DI};

// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if((cmd == DIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
addr <= 0;
ioctl_download <= 1;
addr_reset <= ~addr_reset;
downloading_reg <= 1;
end else begin
addr_w <= addr;
ioctl_download <= 0;
downloading_reg <= 0;
end
end

// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
addr_w <= addr;
if((cmd == DIO_FILE_TX_DAT) && (cnt == 15)) begin
data_w <= {sbuf, SPI_DI};
rclk <= 1;
rclk <= ~rclk;
end

// expose file (menu) index
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
if((cmd == DIO_FILE_INDEX) && (cnt == 15)) index_reg <= {sbuf, SPI_DI};
end
end


// direct SD Card->FPGA transfer
generate if (ROM_DIRECT_UPLOAD == 1) begin

always@(posedge SPI_SCK, posedge SPI_SS4) begin
reg [6:0] sbuf2;
reg [2:0] cnt2;
reg [9:0] bytecnt;

if(SPI_SS4) begin
cnt2 <= 0;
bytecnt <= 0;
end else begin
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt2 != 7)
sbuf2 <= { sbuf2[5:0], SPI_DO };

cnt2 <= cnt2 + 1'd1;

// received a byte
if(cnt2 == 7) begin
bytecnt <= bytecnt + 1'd1;
// read 514 byte/sector (512 + 2 CRC)
if (bytecnt == 513) bytecnt <= 0;
// don't send the CRC bytes
if (~bytecnt[9]) begin
data_w2 <= {sbuf2, SPI_DO};
rclk2 <= ~rclk2;
end
end
end
end

assign ioctl_wr = |ioctl_wrd;
reg [1:0] ioctl_wrd;
end
endgenerate

always@(posedge clk_sys) begin
// bring flags from spi clock domain into core clock domain
reg rclkD, rclkD2;
reg rclk2D, rclk2D2;
reg addr_resetD, addr_resetD2;
reg wr_int, wr_int_direct;
reg [24:0] addr;

always@(negedge clk_sys) begin
reg rclkD, rclkD2;
{ rclkD, rclkD2 } <= { rclk, rclkD };
{ rclk2D ,rclk2D2 } <= { rclk2, rclk2D };
{ addr_resetD, addr_resetD2 } <= { addr_reset, addr_resetD };

rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wrd<= {ioctl_wrd[0],1'b0};
ioctl_wr <= 0;

if(rclkD & ~rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wrd <= 2'b11;
if (!downloading_reg) ioctl_download <= 0;

if (~clkref_n) begin
wr_int <= 0;
wr_int_direct <= 0;
if (wr_int || wr_int_direct) begin
ioctl_dout <= wr_int ? data_w : data_w2;
ioctl_wr <= 1;
addr <= addr + 1'd1;
ioctl_addr <= addr;
end
end

// detect transfer start from the SPI receiver
if(addr_resetD ^ addr_resetD2) begin
addr <= START_ADDR;
ioctl_index <= index_reg;
ioctl_download <= 1;
end

// detect new byte from the SPI receiver
if (rclkD ^ rclkD2) wr_int <= 1;
if (rclk2D ^ rclk2D2) wr_int_direct <= 1;
end

endmodule
68 changes: 41 additions & 27 deletions mist/user_io.v
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Expand Up @@ -22,8 +22,10 @@

// parameter STRLEN and the actual length of conf_str have to match

module user_io #(parameter STRLEN=0, parameter PS2DIV=100) (
module user_io #(parameter STRLEN=0, parameter PS2DIV=100, parameter ROM_DIRECT_UPLOAD=0) (
input [(8*STRLEN)-1:0] conf_str,
output [9:0] conf_addr, // RAM address for config string, if STRLEN=0
input [7:0] conf_chr,

input clk_sys, // clock for system-related messages (kbd, joy, etc...)
input clk_sd, // clock for SD-card related messages
Expand All @@ -33,31 +35,33 @@ module user_io #(parameter STRLEN=0, parameter PS2DIV=100) (
output reg SPI_MISO,
input SPI_MOSI,

output reg [31:0] joystick_0,
output reg [31:0] joystick_1,
output reg [31:0] joystick_2,
output reg [31:0] joystick_3,
output reg [31:0] joystick_4,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output reg [31:0] joystick_0,
output reg [31:0] joystick_1,
output reg [31:0] joystick_2,
output reg [31:0] joystick_3,
output reg [31:0] joystick_4,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output ypbpr,
output reg [31:0] status,
output no_csync,
output reg [31:0] status,
output reg [6:0] core_mod, // core variant, sent before the config string is requested

// connection to sd card emulation
input [31:0] sd_lba,
input sd_rd,
input sd_wr,
output reg sd_ack,
input sd_rd,
input sd_wr,
output reg sd_ack,
output reg sd_ack_conf,
input sd_conf,
input sd_sdhc,
input sd_conf,
input sd_sdhc,
output reg [7:0] sd_dout, // valid on rising edge of sd_dout_strobe
output reg sd_dout_strobe,
output reg sd_dout_strobe,
input [7:0] sd_din,
output reg sd_din_strobe,
output reg sd_din_strobe,
output reg [8:0] sd_buff_addr,

output reg img_mounted, //rising edge if a new image is mounted
Expand All @@ -81,25 +85,29 @@ module user_io #(parameter STRLEN=0, parameter PS2DIV=100) (
output reg [7:0] mouse_flags, // YOvfl, XOvfl, dy8, dx8, 1, mbtn, rbtn, lbtn
output reg mouse_strobe, // mouse data is valid on mouse_strobe

// serial com port
// serial com port
input [7:0] serial_data,
input serial_strobe
);

reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [9:0] byte_cnt; // counts bytes
reg [7:0] but_sw;
reg [7:0] but_sw;
reg [2:0] stick_idx;

assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
assign ypbpr = but_sw[5];
assign no_csync = but_sw[6];

assign conf_addr = byte_cnt;

// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// bit 4 indicates ROM direct upload capability
wire [7:0] core_type = ROM_DIRECT_UPLOAD ? 8'hb4 : 8'ha4;

// command byte read by the io controller
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
Expand Down Expand Up @@ -331,7 +339,8 @@ always@(posedge spi_sck or posedge SPI_SS_IO) begin
spi_byte_out <= 0;
case({(!byte_cnt) ? {sbuf, SPI_MOSI} : cmd})
// reading config string
8'h14: if(byte_cnt < STRLEN) spi_byte_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
8'h14: if (STRLEN == 0) spi_byte_out <= conf_chr; else
if(byte_cnt < STRLEN) spi_byte_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];

// reading sd card status
8'h16: if(byte_cnt == 0) begin
Expand Down Expand Up @@ -476,7 +485,10 @@ always @(posedge clk_sys) begin
// status, 32bit version
8'h1e: if(abyte_cnt<5) status[(abyte_cnt-1)<<3 +:8] <= spi_byte_in;

endcase
// core variant
8'h21: core_mod <= spi_byte_in[6:0];

endcase
end
end
end
Expand Down Expand Up @@ -548,8 +560,10 @@ always @(posedge clk_sd) begin

// send sector FPGA -> IO
8'h18: begin
sd_din_strobe <= 1'b1;
if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
if(~&sd_buff_addr) begin
sd_din_strobe <= 1'b1;
sd_buff_addr <= sd_buff_addr + 1'b1;
end
end

// send SD config IO -> FPGA
Expand Down

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