Framework from submodule

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "mist-modules"]
+	path = mist-modules
+	url = https://github.com/mist-devel/mist-modules

Oric_Sidi.qsf

@@ -243,11 +243,10 @@ set_global_assignment -name USE_SIGNALTAP_FILE rtl/stp1.stp
 set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
 set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
 set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF
+set_global_assignment -name QIP_FILE "mist-modules/mist.qip"
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/wd1793.sv
-set_global_assignment -name VERILOG_FILE mist/sd_card.v
+set_global_assignment -name VHDL_FILE rtl/microdisc.vhd
 set_global_assignment -name VHDL_FILE rtl/rom/MICRODIS.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE mist/sdram.sv
-set_global_assignment -name QIP_FILE mist/mist.qip
 set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd
 set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd
 set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd
@@ -256,6 +255,7 @@ set_global_assignment -name VHDL_FILE rtl/rom/BASIC10.vhd
 set_global_assignment -name VHDL_FILE rtl/rom/BASIC11A.vhdl
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/OricAtmos_MiST.sv
 set_global_assignment -name VHDL_FILE rtl/oricatmos.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
 set_global_assignment -name VHDL_FILE rtl/ula.vhd
 set_global_assignment -name VHDL_FILE rtl/ay8912.vhd
 set_global_assignment -name VHDL_FILE rtl/m6522.vhd
@@ -265,6 +265,5 @@ set_global_assignment -name VERILOG_FILE rtl/pll.v
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
 set_global_assignment -name QIP_FILE rtl/pll.qip
 set_global_assignment -name CDF_FILE output_files/Chain3.cdf
-set_global_assignment -name VHDL_FILE rtl/microdisc.vhd
 set_global_assignment -name CDF_FILE output_files/Chain1.cdf
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top