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Calculates Multiple Karnaugh Maps at once using Selenium and custom built parser. The program then converts the Boolean Expressions into Dataflow Verilog (VHDL)
This program converts a truth table into corresponding Karnaugh Map equations and resulting Tables.
The Boolean Equations are then parsed into Dataflow Verilog code for Digital Circuits processing.
Built to save 3 hours of mundane work and finishing it in ~90 seconds.
Designed For : Fundamentals of Digital Systems Class (LE-E3, ECE 2544).
Written by Qasim Wani.
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Calculates Multiple Karnaugh Maps at once using Selenium and custom built parser. The program then converts the Boolean Expressions into Dataflow Verilog (VHDL)