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SPI flash: dummy bytes calculation for DUAL_IO mode

Status: Open.

#131 In BrunoLevy/learn-fpga;

· loeriver opened on May 14, 2025

Zero register x0 not initialized anywhere

Status: Open.

#129 In BrunoLevy/learn-fpga;

· MrJake222 opened on May 12, 2025

RISCOF and riscv-arch-test for all CPUs

Status: Open.

#128 In BrunoLevy/learn-fpga;

· jeras opened on Mar 25, 2025

fasm2frames.py failed to generate frames from step14.v for xc7a100tcsg324-1

Status: Open.

#127 In BrunoLevy/learn-fpga;

· darshilshah7070 opened on Mar 23, 2025

Make ICESTICK fail with latest oss-cad-suite for macOS 12

Status: Open.

#125 In BrunoLevy/learn-fpga;

· daveti opened on Dec 27, 2024

Icebreaker FPGA UART communication garbage out

Status: Open.

#116 In BrunoLevy/learn-fpga;

· kir486680 opened on Dec 23, 2023

Rv32i quark Block diagram

Status: Open.

#111 In BrunoLevy/learn-fpga;

· cicamargoba opened on Jul 31, 2023

Interrupt handling, double triggering

Status: Open.

#104 In BrunoLevy/learn-fpga;

· spectrumero opened on Jun 19, 2023

From Blinky to RiscV - porting to other HDLs

documentationImprovements or additions to documentationImprovements or additions to documentation

enhancementNew feature or requestNew feature or request

help wantedExtra attention is neededExtra attention is needed

Status: Open.

#103 In BrunoLevy/learn-fpga;

· BrunoLevy opened on Jun 16, 2023

Step 7 Yields No Output

Status: Open.

#87 In BrunoLevy/learn-fpga;

· usmank11 opened on Jan 8, 2023

ice-sugar-nano: PLL avaliable but unused

Status: Open.

#86 In BrunoLevy/learn-fpga;

· wingrime opened on Dec 25, 2022

FROM_BLINKER_TO_RISCV step 14 multiply simulates but doesn't run on IceStick

Status: Open.

#84 In BrunoLevy/learn-fpga;

· dbenn opened on Dec 14, 2022