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FemtoRV32 Design: from zero to I,II,III,IV ... RISC-V

During the first confinement in March 2020, I grabbed an IceStick just before getting stuck at home, with the idea in mind to learn verilog and processor design. I came out with FemtoRV32, a super-simple design. It is too basic (no pipeline), but it may be useful to somebody who wants to quickly understand the general principles. This document is written from my curated notes, keeping the order in which I understood different things and how they mesh together.