diff --git a/drivers/memc/memc_sam_smc.c b/drivers/memc/memc_sam_smc.c
index b54f18f55bbc9bb..3e6bc29cefe8442 100644
--- a/drivers/memc/memc_sam_smc.c
+++ b/drivers/memc/memc_sam_smc.c
@@ -75,10 +75,18 @@ static int memc_smc_init(const struct device *dev)
 	SMC_CYCLE_NWE_CYCLE(DT_PROP_BY_IDX(node_id, atmel_smc_cycle_timing, 0))		\
 	| SMC_CYCLE_NRD_CYCLE(DT_PROP_BY_IDX(node_id, atmel_smc_cycle_timing, 1))
 
+#if defined(CONFIG_SOC_SERIES_SAME70) || defined(CONFIG_SOC_SERIES_SAMV71)
+	#define BUS_WIDTH(node_id) COND_CODE_1( DT_ENUM_IDX(node_id, atmel_smc_bus_width), \
+	(SMC_MODE_DBW_16_BIT), (SMC_MODE_DBW_8_BIT))
+#else
+	#define BUS_WIDTH(node_id) (0)
+#endif
+
 #define BANK_CONFIG(node_id)								\
 	{										\
 		.cs = DT_REG_ADDR(node_id),						\
-		.mode = COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_write_mode),		\
+		.mode = BUS_WIDTH(node_id)                                              \
+			| COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_write_mode),	\
 				    (SMC_MODE_WRITE_MODE), (0))				\
 			| COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_read_mode),	\
 				      (SMC_MODE_READ_MODE), (0)),			\
diff --git a/dts/arm/atmel/same70.dtsi b/dts/arm/atmel/same70.dtsi
index fa954af21f5ca68..d82422dd0537ded 100644
--- a/dts/arm/atmel/same70.dtsi
+++ b/dts/arm/atmel/same70.dtsi
@@ -476,6 +476,15 @@
 			alarms-count = <1>;
 			status = "disabled";
 		};
+
+		smc: smc@40080000 {
+			compatible = "atmel,sam-smc";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40080000 0x4000>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+			status = "disabled";
+		};
 	};
 };
 
diff --git a/dts/bindings/memory-controllers/atmel,sam-smc.yaml b/dts/bindings/memory-controllers/atmel,sam-smc.yaml
index 57e646bd73a5360..b9449e57af0d13c 100644
--- a/dts/bindings/memory-controllers/atmel,sam-smc.yaml
+++ b/dts/bindings/memory-controllers/atmel,sam-smc.yaml
@@ -148,3 +148,16 @@ child-binding:
         is encoded in 9 bits where the two highest bits are multiplied
         with an offset of 256.
         Effective value for each element: 256 x cycle[8:7] + cycle[6:0]
+
+    atmel,smc-bus-width:
+      type: int
+      required: false
+      default: 8
+      description: |
+        Bus Width configuration for the External Bus Interface / the
+        Static Memory Controller that is wired to the external device.
+        SMC on SAME70 (and S70/V70/V71) supports 8- or 16-bit bus width.
+        On SAM4S (and 4E) only 8-bit data buses are supported, therefore 8-bit is set as default.
+      enum:
+        - 8
+        - 16
diff --git a/west.yml b/west.yml
index 9454f2e57adc82e..857ec81f9ab4936 100644
--- a/west.yml
+++ b/west.yml
@@ -152,7 +152,7 @@ manifest:
       groups:
         - hal
     - name: hal_atmel
-      revision: 56d60ebc909ad065bf6554cee73487969857614b
+      revision: pull/41/head
       path: modules/hal/atmel
       groups:
         - hal