From af7abaab1f0c0de8c781d0e0715993890881088f Mon Sep 17 00:00:00 2001 From: Asgeir Stavik Hustad Date: Sun, 8 Sep 2024 13:54:14 +0200 Subject: [PATCH] same70: patch: Fix SmcCs struct naming to match Zephyr driver Fixes a build failure when adding support for the SMC peripheral to the same70-dts. Signed-off-by: Asgeir Stavik Hustad --- asf/sam/include/same70/README | 1 + asf/sam/include/same70/component/smc.h | 10 +++++----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/asf/sam/include/same70/README b/asf/sam/include/same70/README index 17ba9e56..7160b805 100644 --- a/asf/sam/include/same70/README +++ b/asf/sam/include/same70/README @@ -39,6 +39,7 @@ License Link: https://www.apache.org/licenses/LICENSE-2.0 Patch List: + * Fix SmcCs struct naming to match Zephyr driver. * Fix the GMAC priority queue registers to match the datasheet. * Fix GMAC_SA register name. * Fix XDMAC_CHID register name. diff --git a/asf/sam/include/same70/component/smc.h b/asf/sam/include/same70/component/smc.h index 88e333f0..adec49b2 100644 --- a/asf/sam/include/same70/component/smc.h +++ b/asf/sam/include/same70/component/smc.h @@ -372,12 +372,12 @@ typedef struct { __IO uint32_t SMC_PULSE; /**< (SMC_CS_NUMBER Offset: 0x04) SMC Pulse Register (CS_number = 0) */ __IO uint32_t SMC_CYCLE; /**< (SMC_CS_NUMBER Offset: 0x08) SMC Cycle Register (CS_number = 0) */ __IO uint32_t SMC_MODE; /**< (SMC_CS_NUMBER Offset: 0x0C) SMC MODE Register (CS_number = 0) */ -} SmcCsNumber; +} SmcCs_number; -#define SMCCSNUMBER_NUMBER 4 +#define SMCCS_NUMBER_NUMBER 4 /** \brief SMC hardware registers */ typedef struct { - SmcCsNumber SMC_CS_NUMBER[SMCCSNUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */ + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */ __I uint8_t Reserved1[64]; __IO uint32_t SMC_OCMS; /**< (SMC Offset: 0x80) SMC OCMS MODE Register */ __O uint32_t SMC_KEY1; /**< (SMC Offset: 0x84) SMC OCMS KEY1 Register */ @@ -394,11 +394,11 @@ typedef struct { __IO SMC_PULSE_Type SMC_PULSE; /**< Offset: 0x04 (R/W 32) SMC Pulse Register (CS_number = 0) */ __IO SMC_CYCLE_Type SMC_CYCLE; /**< Offset: 0x08 (R/W 32) SMC Cycle Register (CS_number = 0) */ __IO SMC_MODE_Type SMC_MODE; /**< Offset: 0x0C (R/W 32) SMC MODE Register (CS_number = 0) */ -} SmcCsNumber; +} SmcCs_number; /** \brief SMC hardware registers */ typedef struct { - SmcCsNumber SMC_CS_NUMBER[4]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */ + SmcCs_number SMC_CS_NUMBER[4]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */ __I uint8_t Reserved1[64]; __IO SMC_OCMS_Type SMC_OCMS; /**< Offset: 0x80 (R/W 32) SMC OCMS MODE Register */ __O SMC_KEY1_Type SMC_KEY1; /**< Offset: 0x84 ( /W 32) SMC OCMS KEY1 Register */