From 1b5c03cd3da95aafc9ccbae7e0459b7242e1001f Mon Sep 17 00:00:00 2001 From: Asgeir Stavik Hustad Date: Sun, 8 Sep 2024 13:58:01 +0200 Subject: [PATCH] samv71: patch: Fix SmcCs struct naming Fixes a build failure when enabling the SMC-peripheral in the samv71 dts. Signed-off-by: Asgeir Stavik Hustad --- asf/sam/include/samv71/README | 1 + asf/sam/include/samv71/component/smc.h | 10 +++++----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/asf/sam/include/samv71/README b/asf/sam/include/samv71/README index 002e8f4a..99a3db55 100644 --- a/asf/sam/include/samv71/README +++ b/asf/sam/include/samv71/README @@ -39,5 +39,6 @@ License Link: https://www.apache.org/licenses/LICENSE-2.0 Patch List: + * Fix SmcCs struct naming to match Zephyr driver. * Fix the GMAC priority queue registers to match the datasheet. * Fix XDMAC_CHID register name. diff --git a/asf/sam/include/samv71/component/smc.h b/asf/sam/include/samv71/component/smc.h index 6a8ec7f4..a0ebff76 100644 --- a/asf/sam/include/samv71/component/smc.h +++ b/asf/sam/include/samv71/component/smc.h @@ -399,12 +399,12 @@ typedef struct { __IO uint32_t SMC_PULSE; /**< (SMC_CS_NUMBER Offset: 0x04) SMC Pulse Register (CS_number = 0) */ __IO uint32_t SMC_CYCLE; /**< (SMC_CS_NUMBER Offset: 0x08) SMC Cycle Register (CS_number = 0) */ __IO uint32_t SMC_MODE; /**< (SMC_CS_NUMBER Offset: 0x0C) SMC Mode Register (CS_number = 0) */ -} SmcCsNumber; +} SmcCs_number; -#define SMCCSNUMBER_NUMBER 4 +#define SMCCS_NUMBER_NUMBER 4 /** \brief SMC hardware registers */ typedef struct { - SmcCsNumber SmcCsNumber[SMCCSNUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */ + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */ __I uint8_t Reserved1[64]; __IO uint32_t SMC_OCMS; /**< (SMC Offset: 0x80) SMC Off-Chip Memory Scrambling Register */ __O uint32_t SMC_KEY1; /**< (SMC Offset: 0x84) SMC Off-Chip Memory Scrambling KEY1 Register */ @@ -423,11 +423,11 @@ typedef struct { __IO SMC_PULSE_Type SMC_PULSE; /**< Offset: 0x04 (R/W 32) SMC Pulse Register (CS_number = 0) */ __IO SMC_CYCLE_Type SMC_CYCLE; /**< Offset: 0x08 (R/W 32) SMC Cycle Register (CS_number = 0) */ __IO SMC_MODE_Type SMC_MODE; /**< Offset: 0x0C (R/W 32) SMC Mode Register (CS_number = 0) */ -} SmcCsNumber; +} SmcCs_number; /** \brief SMC hardware registers */ typedef struct { - SmcCsNumber SmcCsNumber[4]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */ + SmcCs_number SMC_CS_NUMBER[4]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */ __I uint8_t Reserved1[64]; __IO SMC_OCMS_Type SMC_OCMS; /**< Offset: 0x80 (R/W 32) SMC Off-Chip Memory Scrambling Register */ __O SMC_KEY1_Type SMC_KEY1; /**< Offset: 0x84 ( /W 32) SMC Off-Chip Memory Scrambling KEY1 Register */