From 066a70b6d41a0c2d8adf13ae33d4664d4a422230 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Tue, 5 Sep 2023 08:21:18 +1000 Subject: [PATCH 1/6] Himbaechel. Improve dedicated clock router Added buffers for the global clock network. We indicate that the network is CLOCK by placing the following construction in the file of restrictions: CLOCK_LOC "net_name" BUFG; As a result, the specified network is cut into two parts: the part from the source to the buffer is routed using any available PIPs, while the part from the buffer to the sink is routed through the global clock network. This will slightly improve the situation with Tangnano20k, since now it is possible to declare its pin, on which the simple external generator is located, as a clock, which will lead to routing through the buffer without any clock glitches. All examples for Tangnano20k, which previously used the PLL as a buffer, are no longer needed and use the same files as for the rest of the boards. Signed-off-by: YRabbit --- apycula/chipdb.py | 92 ++++++++- apycula/gowin_pack.py | 6 +- examples/himbaechel/Makefile.himbaechel | 6 +- examples/himbaechel/tangnano20k.cst | 3 +- examples/himbaechel/tangnano20k/TOP.v | 106 ----------- examples/himbaechel/tangnano20k/attosoc.v | 179 ------------------ examples/himbaechel/tangnano20k/blinky-oddr.v | 36 ---- examples/himbaechel/tangnano20k/blinky-osc.v | 44 ----- examples/himbaechel/tangnano20k/blinky-tbuf.v | 25 --- examples/himbaechel/tangnano20k/blinky.v | 21 -- examples/himbaechel/tangnano20k/elvds.v | 31 --- examples/himbaechel/tangnano20k/ides10.v | 52 ----- examples/himbaechel/tangnano20k/ides4.v | 29 --- examples/himbaechel/tangnano20k/ides8.v | 38 ---- examples/himbaechel/tangnano20k/ivideo.v | 51 ----- examples/himbaechel/tangnano20k/oddr-elvds.v | 43 ----- examples/himbaechel/tangnano20k/oddr-tlvds.v | 44 ----- examples/himbaechel/tangnano20k/oser10.v | 74 -------- examples/himbaechel/tangnano20k/oser4.v | 57 ------ examples/himbaechel/tangnano20k/oser8.v | 63 ------ examples/himbaechel/tangnano20k/ovideo.v | 76 -------- examples/himbaechel/tangnano20k/shift.v | 44 ----- examples/himbaechel/tangnano20k/tlvds.v | 31 --- 23 files changed, 95 insertions(+), 1056 deletions(-) delete mode 100644 examples/himbaechel/tangnano20k/TOP.v delete mode 100644 examples/himbaechel/tangnano20k/attosoc.v delete mode 100644 examples/himbaechel/tangnano20k/blinky-oddr.v delete mode 100644 examples/himbaechel/tangnano20k/blinky-osc.v delete mode 100644 examples/himbaechel/tangnano20k/blinky-tbuf.v delete mode 100644 examples/himbaechel/tangnano20k/blinky.v delete mode 100644 examples/himbaechel/tangnano20k/elvds.v delete mode 100644 examples/himbaechel/tangnano20k/ides10.v delete mode 100644 examples/himbaechel/tangnano20k/ides4.v delete mode 100644 examples/himbaechel/tangnano20k/ides8.v delete mode 100644 examples/himbaechel/tangnano20k/ivideo.v delete mode 100644 examples/himbaechel/tangnano20k/oddr-elvds.v delete mode 100644 examples/himbaechel/tangnano20k/oddr-tlvds.v delete mode 100644 examples/himbaechel/tangnano20k/oser10.v delete mode 100644 examples/himbaechel/tangnano20k/oser4.v delete mode 100644 examples/himbaechel/tangnano20k/oser8.v delete mode 100644 examples/himbaechel/tangnano20k/ovideo.v delete mode 100644 examples/himbaechel/tangnano20k/shift.v delete mode 100644 examples/himbaechel/tangnano20k/tlvds.v diff --git a/apycula/chipdb.py b/apycula/chipdb.py index 590ab6c9..f1aa3e84 100644 --- a/apycula/chipdb.py +++ b/apycula/chipdb.py @@ -113,6 +113,7 @@ class Device: # - OSER16/IDES16 # - ref to hclk_pips # - disabled blocks + # - BUF(G) extra_func: Dict[Tuple[int, int], Dict[str, Any]] = field(default_factory=dict) @property @@ -154,6 +155,40 @@ def bank_tiles(self): res.update({ bel[4:] : pos }) return res +# XXX GW1N-4 and GW1NS-4 have next data in dat['CmuxIns']: +# 62 [11, 1, 126] +# 63 [11, 1, 126] +# this means that the same wire (11, 1, 126) is connected implicitly to two +# other logical wires. Let's remember such connections. +# If suddenly a command is given to assign an already used wire to another +# node, then all the contents of this node are combined with the existing one, +# and the node itself is destroyed. only for HCLK and clock nets for now +wire2node = {} +def add_node(dev, node_name, wire_type, row, col, wire): + if (row, col, wire) not in wire2node: + wire2node[row, col, wire] = node_name + dev.nodes.setdefault(node_name, (wire_type, set()))[1].add((row, col, wire)) + else: + if node_name != wire2node[row, col, wire] and node_name in dev.nodes: + #print(f'{node_name} -> {wire2node[row, col, wire]} share ({row}, {col}, {wire})') + dev.nodes[wire2node[row, col, wire]][1].update(dev.nodes[node_name][1]) + del dev.nodes[node_name] + +# create bels for entry potints to the global clock nets +def add_buf_bel(dev, row, col, wire, buf_type = 'BUFG'): + # clock pins + if not wire.startswith('CLK'): + return + extra_func = dev.extra_func.setdefault((row, col), {}) + if 'buf' not in extra_func or buf_type not in extra_func['buf']: + extra_func.update({'buf': {buf_type: [wire]}}) + else: + # dups not allowed for now + if wire in extra_func['buf'][buf_type]: + #print(f'extra buf dup ({row}, {col}) {buf_type}/{wire}') + return + extra_func['buf'][buf_type].append(wire) + def unpad(fuses, pad=-1): try: return fuses[:fuses.index(pad)] @@ -962,7 +997,10 @@ def fse_create_hclk_nodes(dev, device, fse, dat): # entries to the HCLK from logic for hclk_idx, row, col, wire_idx in {(i, dat['CmuxIns'][str(i - 80)][0] - 1, dat['CmuxIns'][str(i - 80)][1] - 1, dat['CmuxIns'][str(i - 80)][2]) for i in range(hclknumbers['TBDHCLK0'], hclknumbers['RBDHCLK3'] + 1)}: if row != -2: - dev.nodes.setdefault(hclknames[hclk_idx], ("HCLK", set()))[1].add((row, col, wirenames[wire_idx])) + add_node(dev, hclknames[hclk_idx], "HCLK", row, col, wirenames[wire_idx]) + # XXX clock router is doing fine with HCLK w/o any buffering + # may be placement suffers a bit + #add_buf_bel(dev, row, col, wirenames[wire_idx], buf_type = 'BUFH') if 'hclk' in hclk_info[side]: # create HCLK cells pips @@ -975,7 +1013,7 @@ def fse_create_hclk_nodes(dev, device, fse, dat): for src in srcs.keys(): for pfx in _global_wire_prefixes: if src.startswith(pfx): - dev.nodes.setdefault(src, ('HCLK', set()))[1].add((row, col, src)) + add_node(dev, src, "HCLK", row, col, src) # strange GW1N-9C input-input aliases for i in {0, 2}: dev.nodes.setdefault(f'X{col}Y{row}/HCLK9-{i}', ('HCLK', {(row, col, f'HCLK_IN{i}')}))[1].add((row, col, f'HCLK_9IN{i}')) @@ -1249,7 +1287,8 @@ def fse_create_clocks(dev, device, dat, fse): # find center muxes for clk_idx, row, col, wire_idx in {(i, dat['CmuxIns'][str(i - 80)][0] - 1, dat['CmuxIns'][str(i - 80)][1] - 1, dat['CmuxIns'][str(i - 80)][2]) for i in range(clknumbers['PCLKT0'], clknumbers['PCLKR1'] + 1)}: if row != -2: - dev.nodes.setdefault(clknames[clk_idx], ("GLOBAL_CLK", set()))[1].add((row, col, wirenames[wire_idx])) + add_node(dev, clknames[clk_idx], "GLOBAL_CLK", row, col, wirenames[wire_idx]) + add_buf_bel(dev, row, col, wirenames[wire_idx]) spines = {f'SPINE{i}' for i in range(32)} for row, rd in enumerate(dev.grid): @@ -1257,11 +1296,11 @@ def fse_create_clocks(dev, device, dat, fse): for dest, srcs in rc.pure_clock_pips.items(): for src in srcs.keys(): if src in spines and not dest.startswith('GT'): - dev.nodes.setdefault(src, ("GLOBAL_CLK", set()))[1].add((row, col, src)) + add_node(dev, src, "GLOBAL_CLK", row, col, src) if dest in spines: - dev.nodes.setdefault(dest, ("GLOBAL_CLK", set()))[1].add((row, col, dest)) + add_node(dev, dest, "GLOBAL_CLK", row, col, dest) for src in { wire for wire in srcs.keys() if wire not in {'VCC', 'VSS'}}: - dev.nodes.setdefault(src, ("GLOBAL_CLK", set()))[1].add((row, col, src)) + add_node(dev, src, "GLOBAL_CLK", row, col, src) # GBx0 <- GBOx for spine_pair in range(4): # GB00/GB40, GB10/GB50, GB20/GB60, GB30/GB70 tap_start = _clock_data[device]['tap_start'][0] @@ -1428,6 +1467,46 @@ def fse_create_io16(dev, device): ('OSCW', 'GW2AN-18'): ({'OSCOUT': 'Q4'}, {}), } +# from logic to global clocks. An interesting piece of dat['CmuxIns'], it was +# found out experimentally that this range is responsible for the wires +# 129: 'TRBDCLK0' - 152: 'TRMDCLK1'. Again we have a shift of 80 from the wire number +# (see create clock aliases). +# 124-126 equal CLK0-CLK2 so these are clearly inputs to the clock system +# (GW1N-1 data) +# 49 [1, 11, 124] +# 50 [1, 11, 125] +# 51 [6, 20, 124] +# 52 [6, 20, 125] +# 53 [1, 10, 125] +# 54 [6, 1, 124] +# 55 [6, 1, 125] +# 56 [1, 10, 124] +# 57 [11, 11, 124] +# 58 [11, 11, 125] +# 59 [7, 20, 126] +# 60 [8, 20, 126] +# 61 [11, 10, 125] +# 62 [7, 1, 126] +# 63 [8, 1, 126] +# 64 [11, 10, 124] +# 65 [-1, -1, -1] +# 66 [-1, -1, -1] +# 67 [-1, -1, -1] +# 68 [-1, -1, -1] +# 69 [-1, -1, -1] +# 70 [-1, -1, -1] +# 71 [6, 10, 126] +# 72 [6, 11, 126] +# We don't need to worry about routing TRBDCLK0 and the family - this was +# already done when we created pure clock pips. But what we need to do is +# indicate that these CLKs at these coordinates are TRBDCLK0, etc. Therefore, +# we create Himbaechel nodes. +def fse_create_logic2clk(dev, device, dat): + for clkwire_idx, row, col, wire_idx in {(i, dat['CmuxIns'][str(i - 80)][0] - 1, dat['CmuxIns'][str(i - 80)][1] - 1, dat['CmuxIns'][str(i - 80)][2]) for i in range(clknumbers['TRBDCLK0'], clknumbers['TRMDCLK1'] + 1)}: + if row != -2: + add_node(dev, clknames[clkwire_idx], "GLOBAL_CLK", row, col, wirenames[wire_idx]) + add_buf_bel(dev, row, col, wirenames[wire_idx]) + def fse_create_osc(dev, device, fse): for row, rd in enumerate(dev.grid): for col, rc in enumerate(rd): @@ -1503,6 +1582,7 @@ def from_fse(device, fse, dat): fse_create_io16(dev, device) fse_create_osc(dev, device, fse) fse_create_gsr(dev, device) + fse_create_logic2clk(dev, device, dat) disable_plls(dev, device) sync_extra_func(dev) return dev diff --git a/apycula/gowin_pack.py b/apycula/gowin_pack.py index e1e0fced..c3d3d859 100644 --- a/apycula/gowin_pack.py +++ b/apycula/gowin_pack.py @@ -82,7 +82,7 @@ def extra_pll_bels(cell, row, col, num, cellname): def get_bels(data): later = [] if is_himbaechel: - belre = re.compile(r"X(\d+)Y(\d+)/(?:GSR|LUT|DFF|IOB|MUX|ALU|ODDR|OSC[ZFHWO]?|BUFS|RAM16SDP4|RAM16SDP2|RAM16SDP1|PLL|IOLOGIC)(\w*)") + belre = re.compile(r"X(\d+)Y(\d+)/(?:GSR|LUT|DFF|IOB|MUX|ALU|ODDR|OSC[ZFHWO]?|BUF[GS]|RAM16SDP4|RAM16SDP2|RAM16SDP1|PLL|IOLOGIC)(\w*)") else: belre = re.compile(r"R(\d+)C(\d+)_(?:GSR|SLICE|IOB|MUX2_LUT5|MUX2_LUT6|MUX2_LUT7|MUX2_LUT8|ODDR|OSC[ZFHWO]?|BUFS|RAMW|rPLL|PLLVR|IOLOGIC)(\w*)") @@ -572,7 +572,7 @@ def __init__(self, row, col, idx, attrs, flags, connections): 'TBUF': {'ODMUX_1': 'UNKNOWN', 'PULLMODE': 'UP', 'SLEWRATE': 'FAST', 'DRIVE': '8', 'HYSTERESIS': 'NONE', 'CLAMP': 'OFF', 'DIFFRESISTOR': 'OFF', 'SINGLERESISTOR': 'OFF', 'VCCIO': '1.8', 'LVDS_OUT': 'OFF', 'DDR_DYNTERM': 'NA', - 'TO': 'INV', 'PERSISTENT': 'OFF', 'ODMUX': 'TRIMUX'}, + 'TO': 'INV', 'PERSISTENT': 'OFF', 'ODMUX': 'TRIMUX', 'OPENDRAIN': 'OFF'}, 'IOBUF': {'ODMUX_1': 'UNKNOWN', 'PULLMODE': 'UP', 'SLEWRATE': 'FAST', 'DRIVE': '8', 'HYSTERESIS': 'NONE', 'CLAMP': 'OFF', 'DIFFRESISTOR': 'OFF', 'SINGLERESISTOR': 'OFF', 'VCCIO': '1.8', 'LVDS_OUT': 'OFF', 'DDR_DYNTERM': 'NA', @@ -700,6 +700,8 @@ def place(db, tilemap, bels, cst, args): bits2zero.update(tiledata.bels[f'BUFS{num}'].flags[fuses]) for r, c in bits2zero: tile[r][c] = 0 + elif typ.startswith("BUFG"): + continue elif typ in {'OSC', 'OSCZ', 'OSCF', 'OSCH', 'OSCW', 'OSCO'}: # XXX turn on (GW1NZ-1) diff --git a/examples/himbaechel/Makefile.himbaechel b/examples/himbaechel/Makefile.himbaechel index 16729528..88ba0dcc 100644 --- a/examples/himbaechel/Makefile.himbaechel +++ b/examples/himbaechel/Makefile.himbaechel @@ -146,13 +146,13 @@ clean: %-tangnano20k.json: %-tangnano20k-synth.json tangnano20k.cst $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW2A-18C.bin --vopt partno=GW2AR-LV18QN88C8/I7 --vopt cst=tangnano20k.cst -%-tangnano20k-synth.json: tangnano20k/%.v +%-tangnano20k-synth.json: %.v $(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@" -pll-nanolcd-tangnano20k-synth.json: pll/GW2A-18-dyn.vh tangnano20k/TOP.v pll-nanolcd/VGAMod.v +pll-nanolcd-tangnano20k-synth.json: pll/GW2A-18-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v $(YOSYS) -p "read_verilog $^; synth_gowin -json $@" -attosoc-tangnano20k-synth.json: tangnano20k/attosoc.v attosoc/picorv32.v +attosoc-tangnano20k-synth.json: attosoc/attosoc.v attosoc/picorv32.v $(YOSYS) -p "read_verilog $^; synth_gowin -json $@" # ============================================================ diff --git a/examples/himbaechel/tangnano20k.cst b/examples/himbaechel/tangnano20k.cst index 0b349507..3992d521 100644 --- a/examples/himbaechel/tangnano20k.cst +++ b/examples/himbaechel/tangnano20k.cst @@ -1,5 +1,6 @@ IO_LOC "clk" 4; -IO_LOC "clk_i" 4; + +CLOCK_LOC "clk" BUFG; IO_LOC "led[0]" 15; IO_LOC "led[1]" 16; diff --git a/examples/himbaechel/tangnano20k/TOP.v b/examples/himbaechel/tangnano20k/TOP.v deleted file mode 100644 index 9f5db57b..00000000 --- a/examples/himbaechel/tangnano20k/TOP.v +++ /dev/null @@ -1,106 +0,0 @@ -(* top *) -module TOP -( - input rst, - input clk, - - output LCD_CLK, - output LCD_HYNC, - output LCD_SYNC, - output LCD_DEN, - output [4:0] LCD_R, - output [5:0] LCD_G, - output [4:0] LCD_B, - - output LED_R, - output LED_G, - output LED_B - -); - - wire CLK_SYS; - wire CLK_PIX; - -/* //使用内部时钟 - Gowin_OSC chip_osc( - .oscout(oscout_o) //output oscout - ); -*/ -rPLL pll( - .CLKOUT(CLK_PIX), // 9MHz - .CLKIN(clk), - .CLKFB(GND), - .RESET(GND), - .RESET_P(GND), - .FBDSEL({GND,GND,GND,GND,GND,GND}), - .IDSEL({GND,GND,GND,GND,GND,GND}), - .ODSEL({GND,GND,GND,GND,GND,GND}), - .DUTYDA({GND,GND,GND,GND}), - .PSDA({GND,GND,GND,GND}), - .FDLY({GND,GND,GND,GND}) - ); - defparam pll.DEVICE = `PLL_DEVICE; - defparam pll.FCLKIN = `PLL_FCLKIN; - defparam pll.FBDIV_SEL = `PLL_FBDIV_SEL_LCD; - defparam pll.IDIV_SEL = `PLL_IDIV_SEL_LCD; - defparam pll.ODIV_SEL = `PLL_ODIV_SEL; - defparam pll.CLKFB_SEL="internal"; - defparam pll.CLKOUTD3_SRC="CLKOUT"; - defparam pll.CLKOUTD_BYPASS="true"; - defparam pll.CLKOUTD_SRC="CLKOUT"; - defparam pll.CLKOUTP_BYPASS="false"; - defparam pll.CLKOUTP_DLY_STEP=0; - defparam pll.CLKOUTP_FT_DIR=1'b1; - defparam pll.CLKOUT_BYPASS="false"; - defparam pll.CLKOUT_DLY_STEP=0; - defparam pll.CLKOUT_FT_DIR=1'b1; - defparam pll.DUTYDA_SEL="1000"; - defparam pll.DYN_DA_EN="false"; - defparam pll.DYN_FBDIV_SEL="false"; - defparam pll.DYN_IDIV_SEL="false"; - defparam pll.DYN_ODIV_SEL="false"; - defparam pll.DYN_SDIV_SEL=1; // 9MHz --- pixel clock - defparam pll.PSDA_SEL="0000"; - - VGAMod D1 - ( - .CLK ( CLK_SYS ), - .nRST ( !rst ), - - .PixelClk ( CLK_PIX ), - .LCD_DE ( LCD_DEN ), - .LCD_HSYNC ( LCD_HYNC ), - .LCD_VSYNC ( LCD_SYNC ), - - .LCD_B ( LCD_B ), - .LCD_G ( LCD_G ), - .LCD_R ( LCD_R ) - ); - - assign LCD_CLK = CLK_PIX; - assign CLK_SYS = CLK_PIX; - - - //RGB LED TEST - reg [24:0] Count; - reg [1:0] rgb_data; - always @( posedge CLK_SYS or posedge rst ) - begin - if( rst ) - begin - Count <= 25'd0; - rgb_data <= 2'b00; - end - else if ( Count == 1200000 ) - begin - Count <= 4'b0; - rgb_data <= rgb_data + 1'b1; - end - else - Count <= Count + 1'b1; - end - assign LED_R = ~(rgb_data == 2'b01); - assign LED_G = ~(rgb_data == 2'b10); - assign LED_B = ~(rgb_data == 2'b11); - -endmodule diff --git a/examples/himbaechel/tangnano20k/attosoc.v b/examples/himbaechel/tangnano20k/attosoc.v deleted file mode 100644 index 755d0360..00000000 --- a/examples/himbaechel/tangnano20k/attosoc.v +++ /dev/null @@ -1,179 +0,0 @@ -/* - * ECP5 PicoRV32 demo - * - * Copyright (C) 2017 Clifford Wolf - * Copyright (C) 2018 David Shah - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -`ifdef PICORV32_V -`error "attosoc.v must be read before picorv32.v!" -`endif - -`define PICORV32_REGS picosoc_regs - -(* top *) -module attosoc ( - input clk_i, - output reg [7:0] led -); - -wire lock_o; -wire clkoutp_o; -wire clkoutd_o; -wire clkoutd3_o; -wire gw_gnd; - -assign gw_gnd = 1'b0; - -wire clk; - -rPLL rpll_inst ( - .CLKOUT(clk), - .LOCK(lock_o), - .CLKOUTP(clkoutp_o), - .CLKOUTD(clkoutd_o), - .CLKOUTD3(clkoutd3_o), - .RESET(gw_gnd), - .RESET_P(gw_gnd), - .CLKIN(clk_i), - .CLKFB(gw_gnd), - .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}) -); - -defparam rpll_inst.FCLKIN = "27"; -defparam rpll_inst.DYN_IDIV_SEL = "false"; -defparam rpll_inst.IDIV_SEL = 2; -defparam rpll_inst.DYN_FBDIV_SEL = "false"; -defparam rpll_inst.FBDIV_SEL = 0; -defparam rpll_inst.DYN_ODIV_SEL = "false"; -defparam rpll_inst.ODIV_SEL = 64; -defparam rpll_inst.PSDA_SEL = "0000"; -defparam rpll_inst.DYN_DA_EN = "false"; -defparam rpll_inst.DUTYDA_SEL = "1000"; -defparam rpll_inst.CLKOUT_FT_DIR = 1'b1; -defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1; -defparam rpll_inst.CLKOUT_DLY_STEP = 0; -defparam rpll_inst.CLKOUTP_DLY_STEP = 0; -defparam rpll_inst.CLKFB_SEL = "internal"; -defparam rpll_inst.CLKOUT_BYPASS = "true"; -defparam rpll_inst.CLKOUTP_BYPASS = "false"; -defparam rpll_inst.CLKOUTD_BYPASS = "false"; -defparam rpll_inst.DYN_SDIV_SEL = 2; -defparam rpll_inst.CLKOUTD_SRC = "CLKOUT"; -defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT"; -defparam rpll_inst.DEVICE = "GW2AR-18C"; - - reg [5:0] reset_cnt = 0; - wire resetn = &reset_cnt; - - always @(posedge clk) begin - reset_cnt <= reset_cnt + !resetn; - end - - parameter integer MEM_WORDS = 256; - parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory - parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // ROM at 0x0 - parameter integer ROM_BYTES = 256; - - reg [7:0] rom [0:ROM_BYTES-1]; - wire [31:0] rom_rdata = {rom[mem_addr+3], rom[mem_addr+2], rom[mem_addr+1], rom[mem_addr+0]}; - initial $readmemh("attosoc/firmware.hex", rom); - - wire mem_valid; - wire mem_instr; - wire mem_ready; - wire [31:0] mem_addr; - wire [31:0] mem_wdata; - wire [3:0] mem_wstrb; - wire [31:0] mem_rdata; - - wire rom_ready = mem_valid && mem_addr[31:24] == 8'h00; - - wire iomem_valid; - wire iomem_ready; - wire [31:0] iomem_addr; - wire [31:0] iomem_wdata; - wire [3:0] iomem_wstrb; - wire [31:0] iomem_rdata; - - assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01); - assign iomem_ready = 1'b1; - assign iomem_wstrb = mem_wstrb; - assign iomem_addr = mem_addr; - assign iomem_wdata = mem_wdata; - - wire [31:0] spimemio_cfgreg_do; - - - always @(posedge clk) - if (iomem_valid && iomem_wstrb[0]) - led <= iomem_wdata[7:0]; - - assign mem_ready = (iomem_valid && iomem_ready) || rom_ready; - - assign mem_rdata = rom_rdata; - - picorv32 #( - .STACKADDR(STACKADDR), - .PROGADDR_RESET(PROGADDR_RESET), - .PROGADDR_IRQ(32'h 0000_0000), - .BARREL_SHIFTER(0), - .COMPRESSED_ISA(0), - .ENABLE_MUL(0), - .ENABLE_DIV(0), - .ENABLE_IRQ(0), - .ENABLE_IRQ_QREGS(0) - ) cpu ( - .clk (clk ), - .resetn (resetn ), - .mem_valid (mem_valid ), - .mem_instr (mem_instr ), - .mem_ready (mem_ready ), - .mem_addr (mem_addr ), - .mem_wdata (mem_wdata ), - .mem_wstrb (mem_wstrb ), - .mem_rdata (mem_rdata ) - ); - - - -endmodule - -// Implementation note: -// Replace the following two modules with wrappers for your SRAM cells. - -module picosoc_regs ( - input clk, wen, - input [5:0] waddr, - input [5:0] raddr1, - input [5:0] raddr2, - input [31:0] wdata, - output [31:0] rdata1, - output [31:0] rdata2 -); - reg [31:0] regs [0:31]; - - always @(posedge clk) - if (wen) regs[waddr[4:0]] <= wdata; - - assign rdata1 = regs[raddr1[4:0]]; - assign rdata2 = regs[raddr2[4:0]]; -endmodule diff --git a/examples/himbaechel/tangnano20k/blinky-oddr.v b/examples/himbaechel/tangnano20k/blinky-oddr.v deleted file mode 100644 index cc10be89..00000000 --- a/examples/himbaechel/tangnano20k/blinky-oddr.v +++ /dev/null @@ -1,36 +0,0 @@ -/* -* led[0] is connected directly, led[1] --- via ODDR. This primitive needs 4 clock cycles to start working, so be patient:) -*/ -module top ( - input clk, - input key, - input rst, - output [`LEDS_NR-1:0] led -); - -reg [24:0] ctr_q; -wire [24:0] ctr_d; - -// Sequential code (flip-flop) -always @(posedge clk) begin - if (!rst) begin - ctr_q <= ctr_d; - end -end - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign led[`LEDS_NR-1:2] = {(`LEDS_NR - 2){1'b1}}; -assign led[0] = ctr_q[24:24]; - -ODDRC oddr_0( - .D0(1'b0), - .D1(1'b1), - .CLK(ctr_q[24:24]), - .Q0(led[1]), - .Q1(), - .TX(1'b1), - .CLEAR(key) -); - -endmodule diff --git a/examples/himbaechel/tangnano20k/blinky-osc.v b/examples/himbaechel/tangnano20k/blinky-osc.v deleted file mode 100644 index f434a445..00000000 --- a/examples/himbaechel/tangnano20k/blinky-osc.v +++ /dev/null @@ -1,44 +0,0 @@ -module top ( - input rst, - output [`LEDS_NR-1:0] led -); - -wire clk; - -`ifdef OSC_TYPE_OSC -OSC osc( - .OSCOUT(clk) -); -`elsif OSC_TYPE_OSCZ -OSCZ osc( - .OSCEN(1'b1), - .OSCOUT(clk) -); -`elsif OSC_TYPE_OSCF -OSCF osc( - .OSCEN(1'b1), - .OSCOUT(clk), - .OSCOUT30M() -); -`elsif OSC_TYPE_OSCH -OSCH osc( - .OSCOUT(clk) -); -`endif -defparam osc.FREQ_DIV=16; - -reg [25:0] ctr_q; -wire [25:0] ctr_d; - -// Sequential code (flip-flop) -always @(posedge clk) begin - if (!rst) begin - ctr_q <= ctr_d; - end -end - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign led = ctr_q[25:25-(`LEDS_NR - 1)]; - -endmodule diff --git a/examples/himbaechel/tangnano20k/blinky-tbuf.v b/examples/himbaechel/tangnano20k/blinky-tbuf.v deleted file mode 100644 index 136e1f3f..00000000 --- a/examples/himbaechel/tangnano20k/blinky-tbuf.v +++ /dev/null @@ -1,25 +0,0 @@ -module top ( - input clk, - input key, - output [`LEDS_NR-1:0] led -); - -reg [25:0] ctr_q; -wire [25:0] ctr_d; - -// Sequential code (flip-flop) -always @(posedge clk) begin - ctr_q <= ctr_d; -end - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign led[`LEDS_NR - 1:1] = ctr_q[25:25-(`LEDS_NR - 2)]; - -TBUF tbuf( - .I(ctr_q[25 - (`LEDS_NR - 1)]), - .O(led[0]), - .OEN(key) -); - -endmodule diff --git a/examples/himbaechel/tangnano20k/blinky.v b/examples/himbaechel/tangnano20k/blinky.v deleted file mode 100644 index c8b0699b..00000000 --- a/examples/himbaechel/tangnano20k/blinky.v +++ /dev/null @@ -1,21 +0,0 @@ -module top ( - input clk, - input key, - output [`LEDS_NR-1:0] led -); - -reg [25:0] ctr_q; -wire [25:0] ctr_d; - -// Sequential code (flip-flop) -always @(posedge clk) begin - if (!key) begin - ctr_q <= ctr_d; - end -end - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign led = ctr_q[25:25-(`LEDS_NR - 1)]; - -endmodule diff --git a/examples/himbaechel/tangnano20k/elvds.v b/examples/himbaechel/tangnano20k/elvds.v deleted file mode 100644 index 7fd20470..00000000 --- a/examples/himbaechel/tangnano20k/elvds.v +++ /dev/null @@ -1,31 +0,0 @@ -/* Using an oscilloscope you can see on pins tlvds_p and tlvds_n the signal with changing polarity. -* You can also use a 100 Ohm resistor and two LEDs connected in opposite directions between these pins. -*/ -module top ( - input clk, - output elvds_p, - output elvds_n, - input key -); - -reg [24:0] ctr_q; -wire [24:0] ctr_d; -wire i_tick; - -// Sequential code (flip-flop) -always @(posedge clk) - ctr_q <= ctr_d; - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign i_tick = |ctr_q[24:23]; - -ELVDS_TBUF diff_buf( - .OEN(key), - .O(elvds_p), - .OB(elvds_n), - .I(i_tick) - ); - -endmodule - diff --git a/examples/himbaechel/tangnano20k/ides10.v b/examples/himbaechel/tangnano20k/ides10.v deleted file mode 100644 index 70cd4ff8..00000000 --- a/examples/himbaechel/tangnano20k/ides10.v +++ /dev/null @@ -1,52 +0,0 @@ -`default_nettype none -module top(input wire clk, - input wire rst, - input wire fclk_i, - input wire data_i, - output wire pclk_o, - output wire [7:0]q_o); - - wire dummy[1:0]; - - IDES10 ides( - .D(data_i), - .FCLK(fclk_i), - .PCLK(pclk_o), - .CALIB(1'b0), - .RESET(rst), - .Q0(q_o[0]), - .Q1(q_o[1]), - .Q2(q_o[2]), - .Q3(q_o[3]), - .Q4(q_o[4]), - .Q5(q_o[5]), - .Q6(q_o[6]), - .Q7(q_o[7]), - .Q8(dummy[0]), - .Q9(dummy[1]) - ); - defparam ides.GSREN="false"; - defparam ides.LSREN="true"; - - // div by 5 - reg [2:0] count; - wire clkA; - reg clkB; - always @(posedge fclk_i) begin - if (rst) begin - count <= 0; - end else begin - if (count == 3'd4) begin - count <= 0; - end else begin - count <= count+1; - end - end - end - assign clkA = count[1]; - - always@(negedge fclk_i) begin - clkB <= clkA; - end - assign pclk_o = clkA | clkB; -endmodule diff --git a/examples/himbaechel/tangnano20k/ides4.v b/examples/himbaechel/tangnano20k/ides4.v deleted file mode 100644 index 6128eeef..00000000 --- a/examples/himbaechel/tangnano20k/ides4.v +++ /dev/null @@ -1,29 +0,0 @@ -`default_nettype none -module top(input wire clk, - input wire rst, - input wire fclk_i, - input wire data_i, - output wire pclk_o, - output wire [7:0]q_o); - - IDES4 ides( - .D(data_i), - .FCLK(fclk_i), - .PCLK(pclk_o), - .CALIB(1'b0), - .RESET(rst), - .Q0(q_o[0]), - .Q1(q_o[1]), - .Q2(q_o[2]), - .Q3(q_o[3]) - ); - defparam ides.GSREN="false"; - defparam ides.LSREN="true"; - - reg pclk_r; - always @(posedge fclk_i) begin - pclk_r <= !pclk_r; - end - assign pclk_o = pclk_r; - -endmodule diff --git a/examples/himbaechel/tangnano20k/ides8.v b/examples/himbaechel/tangnano20k/ides8.v deleted file mode 100644 index 284a013c..00000000 --- a/examples/himbaechel/tangnano20k/ides8.v +++ /dev/null @@ -1,38 +0,0 @@ -`default_nettype none -module top(input wire clk, - input wire rst, - input wire fclk_i, - input wire data_i, - output wire pclk_o, - output wire [7:0]q_o); - - IDES8 ides( - .D(data_i), - .FCLK(fclk_i), - .PCLK(pclk_o), - .CALIB(1'b0), - .RESET(rst), - .Q0(q_o[0]), - .Q1(q_o[1]), - .Q2(q_o[2]), - .Q3(q_o[3]), - .Q4(q_o[4]), - .Q5(q_o[5]), - .Q6(q_o[6]), - .Q7(q_o[7]), - ); - defparam ides.GSREN="false"; - defparam ides.LSREN="true"; - - reg [1:0]pclk_r; - - always @(posedge fclk_i) begin - if (rst) begin - pclk_r <= 2'b00; - end else begin - pclk_r <= pclk_r + 2'b01; - end - end - assign pclk_o = pclk_r[1]; - -endmodule diff --git a/examples/himbaechel/tangnano20k/ivideo.v b/examples/himbaechel/tangnano20k/ivideo.v deleted file mode 100644 index fb1f4aef..00000000 --- a/examples/himbaechel/tangnano20k/ivideo.v +++ /dev/null @@ -1,51 +0,0 @@ -`default_nettype none -module top(input wire clk, - input wire rst, - input wire fclk_i, - input wire data_i, - output wire pclk_o, - output wire [7:0]q_o); - - IVIDEO ides( - .D(data_i), - .FCLK(fclk_i), - .PCLK(pclk_o), - .CALIB(1'b0), - .RESET(rst), - .Q0(q_o[0]), - .Q1(q_o[1]), - .Q2(q_o[2]), - .Q3(q_o[3]), - .Q4(q_o[4]), - .Q5(q_o[5]), - .Q6(q_o[6]) - ); - defparam ides.GSREN="false"; - defparam ides.LSREN="true"; - - // div by 3.5 - reg [6:0]cnt_r; - reg ps0_r; - reg ps3_r; - reg ps4_r; - always @(posedge fclk_i) begin - if (rst) begin - cnt_r[6:0] <= 7'b000_0001; - end else begin - cnt_r[6:0] <= {cnt_r[5:0], cnt_r[6]}; - end - end - - always @(negedge fclk_i) begin - if (rst) begin - ps0_r <= 1'b0; - ps3_r <= 1'b0; - ps4_r <= 1'b0; - end else begin - ps0_r <= cnt_r[0]; - ps3_r <= cnt_r[3]; - ps4_r <= cnt_r[4]; - end - end - assign pclk_o = (ps0_r | cnt_r[0] | cnt_r[1]) | (ps3_r | ps4_r | cnt_r[4]); -endmodule diff --git a/examples/himbaechel/tangnano20k/oddr-elvds.v b/examples/himbaechel/tangnano20k/oddr-elvds.v deleted file mode 100644 index 91e49a0f..00000000 --- a/examples/himbaechel/tangnano20k/oddr-elvds.v +++ /dev/null @@ -1,43 +0,0 @@ -/* Using an oscilloscope you can see on pins tlvds_p and tlvds_n the signal with changing polarity. -* You can also use a 100 Ohm resistor and two LEDs connected in opposite directions between these pins. -* ODDR needs 4 clock cycles to start working, so be patient:) -*/ -module top ( - input clk, - input key, - output elvds_p, - output elvds_n -); - -reg [24:0] ctr_q; -wire [24:0] ctr_d; -wire i_tick; -wire w_ddr; -wire oen; - -// Sequential code (flip-flop) -always @(posedge clk) - ctr_q <= ctr_d; - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign i_tick = |ctr_q[24:23]; - -ODDR oddr_0( - .D0(1'b0), - .D1(1'b1), - .CLK(i_tick), - .Q0(w_ddr), - .Q1(oen), - .TX(key) -); - -ELVDS_TBUF diff_buf( - .OEN(oen), - .O(elvds_p), - .OB(elvds_n), - .I(w_ddr) - ); - -endmodule - diff --git a/examples/himbaechel/tangnano20k/oddr-tlvds.v b/examples/himbaechel/tangnano20k/oddr-tlvds.v deleted file mode 100644 index 488ad76d..00000000 --- a/examples/himbaechel/tangnano20k/oddr-tlvds.v +++ /dev/null @@ -1,44 +0,0 @@ -/* Using an oscilloscope you can see on pins tlvds_p and tlvds_n the signal with changing polarity. -* You can also use a 100 Ohm resistor and two LEDs connected in opposite directions between these pins. -* ODDR needs 4 clock cycles to start working, so be patient:) -*/ -module top ( - input clk, - input key, - output tlvds_p, - output tlvds_n -); - -reg [24:0] ctr_q; -wire [24:0] ctr_d; -wire i_tick; -wire w_ddr; - -// Sequential code (flip-flop) -always @(posedge clk) - ctr_q <= ctr_d; - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign i_tick = |ctr_q[24:23]; - -wire w_oen; - -ODDR oddr_0( - .D0(1'b0), - .D1(1'b1), - .CLK(i_tick), - .Q0(w_ddr), - .Q1(w_oen), - .TX(key) -); - -TLVDS_TBUF diff_buf( - .OEN(w_oen), - .O(tlvds_p), - .OB(tlvds_n), - .I(w_ddr) - ); - -endmodule - diff --git a/examples/himbaechel/tangnano20k/oser10.v b/examples/himbaechel/tangnano20k/oser10.v deleted file mode 100644 index 41039d01..00000000 --- a/examples/himbaechel/tangnano20k/oser10.v +++ /dev/null @@ -1,74 +0,0 @@ -`default_nettype none -/* -* This example allows you to generate several OSER10 primitives and then check -* them with a logic analyzer. The PCLK, FCLK and Q outputs of the primitives -* are connected to the board pins. -*/ -module top(input wire clk, - input wire rst, - output wire oser_out, - output wire pclk_o, - output wire fclk_o); - - OSER10 os( - .D0(1'b0), - .D1(1'b1), - .D2(1'b0), - .D3(1'b1), - .D4(1'b0), - .D5(1'b1), - .D6(1'b0), - .D7(1'b1), - .D8(1'b0), - .D9(1'b1), - .FCLK(fclk_w), - .PCLK(pclk_w), - .RESET(1'b0), - .Q(oser_out) - ); - defparam os.GSREN = "false"; - defparam os.LSREN = "true"; - - wire clk_w; - wire pclk_w; - wire fclk_w; - - assign pclk_o = pclk_w; - assign fclk_o = fclk_w; - - reg [2:0] count; - wire clkA; - reg clkB; - always @(posedge fclk_w) begin - if (rst) begin - count <= 0; - end else begin - if (count == 3'd4) begin - count <= 0; - end else begin - count <= count+1; - end - end - end - assign clkA = count[1]; - - always@(negedge fclk_w) begin - clkB <= clkA; - end - assign pclk_w = clkA | clkB; - - // slow - reg [24:0] ctr_q; - wire [24:0] ctr_d; - wire tick_w; - - // Sequential code (flip-flop) - always @(posedge clk) - ctr_q <= ctr_d; - - // Combinational code (boolean logic) - assign ctr_d = ctr_q + 1'b1; - assign tick_w = ctr_q[24]; - - assign fclk_w = tick_w; -endmodule diff --git a/examples/himbaechel/tangnano20k/oser4.v b/examples/himbaechel/tangnano20k/oser4.v deleted file mode 100644 index a4038488..00000000 --- a/examples/himbaechel/tangnano20k/oser4.v +++ /dev/null @@ -1,57 +0,0 @@ -`default_nettype none -/* -* This example allows you to generate several OSER10 primitives and then check -* them with a logic analyzer. The PCLK, FCLK and Q outputs of the primitives -* are connected to the board pins. -*/ -module top(input wire clk, - input wire rst, - output wire oser_out, - output wire pclk_o, - output wire fclk_o); - - OSER4 os( - .D0(1'b0), - .D1(1'b1), - .D2(1'b0), - .D3(1'b1), - .TX0(1'b1), - .TX1(1'b1), - .FCLK(fclk_w), - .PCLK(pclk_w), - .RESET(1'b0), - .Q0(oser_out), - .Q1() - ); - defparam os.GSREN = "false"; - defparam os.LSREN = "true"; - - wire clk_w; - wire pclk_w; - wire fclk_w; - - assign pclk_o = pclk_w; - assign fclk_o = fclk_w; - - reg clkB; - - always@(negedge fclk_w) begin - clkB <= ~clkB; - end - assign pclk_w = clkB; - - // slow - reg [24:0] ctr_q; - wire [24:0] ctr_d; - wire tick_w; - - // Sequential code (flip-flop) - always @(posedge clk) - ctr_q <= ctr_d; - - // Combinational code (boolean logic) - assign ctr_d = ctr_q + 1'b1; - assign tick_w = ctr_q[24]; - - assign fclk_w = tick_w; -endmodule diff --git a/examples/himbaechel/tangnano20k/oser8.v b/examples/himbaechel/tangnano20k/oser8.v deleted file mode 100644 index 1d829976..00000000 --- a/examples/himbaechel/tangnano20k/oser8.v +++ /dev/null @@ -1,63 +0,0 @@ -`default_nettype none -/* -* This example allows you to generate several OSER10 primitives and then check -* them with a logic analyzer. The PCLK, FCLK and Q outputs of the primitives -* are connected to the board pins. -*/ -module top(input wire clk, - input wire rst, - output wire oser_out, - output wire pclk_o, - output wire fclk_o); - - OSER8 os( - .D0(1'b0), - .D1(1'b1), - .D2(1'b0), - .D3(1'b1), - .D4(1'b0), - .D5(1'b1), - .D6(1'b0), - .D7(1'b1), - .TX0(1'b1), - .TX1(1'b1), - .TX2(1'b1), - .TX3(1'b1), - .FCLK(fclk_w), - .PCLK(pclk_r[1]), - .RESET(1'b0), - .Q0(oser_out) - ); - defparam os.GSREN = "false"; - defparam os.LSREN = "true"; - defparam os.TXCLK_POL = 0; - defparam os.HWL = "false"; - - reg [1:0]pclk_r; - wire fclk_w; - - always @(posedge fclk_w) begin - if (rst) begin - pclk_r <= 2'b00; - end else begin - pclk_r <= pclk_r + 2'b01; - end - end - assign pclk_o = pclk_r[1]; - assign fclk_o = fclk_w; - - // slow - reg [24:0] ctr_q; - wire [24:0] ctr_d; - wire tick_w; - - // Sequential code (flip-flop) - always @(posedge clk) - ctr_q <= ctr_d; - - // Combinational code (boolean logic) - assign ctr_d = ctr_q + 1'b1; - assign tick_w = ctr_q[24]; - - assign fclk_w = tick_w; -endmodule diff --git a/examples/himbaechel/tangnano20k/ovideo.v b/examples/himbaechel/tangnano20k/ovideo.v deleted file mode 100644 index 966a2837..00000000 --- a/examples/himbaechel/tangnano20k/ovideo.v +++ /dev/null @@ -1,76 +0,0 @@ -`default_nettype none -/* -* This example allows you to generate several OSER10 primitives and then check -* them with a logic analyzer. The PCLK, FCLK and Q outputs of the primitives -* are connected to the board pins. -*/ -module top(input wire clk, - input wire rst, - output wire oser_out, - output wire pclk_o, - output wire fclk_o); - - OVIDEO os( - .D0(1'b1), - .D1(1'b0), - .D2(1'b1), - .D3(1'b0), - .D4(1'b1), - .D5(1'b0), - .D6(1'b1), - .FCLK(fclk_w), - .PCLK(pclk_w), - .RESET(1'b0), - .Q(oser_out) - ); - defparam os.GSREN = "false"; - defparam os.LSREN = "true"; - - wire clk_w; - wire pclk_w; - wire fclk_w; - - assign pclk_o = pclk_w; - assign fclk_o = fclk_w; - - // div by 3.5 - reg [6:0]cnt_r; - reg ps0_r; - reg ps3_r; - reg ps4_r; - always @(posedge fclk_w) begin - if (rst) begin - cnt_r[6:0] <= 7'b000_0001; - end else begin - cnt_r[6:0] <= {cnt_r[5:0], cnt_r[6]}; - end - end - - always @(negedge fclk_w) begin - if (rst) begin - ps0_r <= 1'b0; - ps3_r <= 1'b0; - ps4_r <= 1'b0; - end else begin - ps0_r <= cnt_r[0]; - ps3_r <= cnt_r[3]; - ps4_r <= cnt_r[4]; - end - end - assign pclk_w = (ps0_r | cnt_r[0] | cnt_r[1]) | (ps3_r | ps4_r | cnt_r[4]); - - // slow - reg [24:0] ctr_q; - wire [24:0] ctr_d; - wire tick_w; - - // Sequential code (flip-flop) - always @(posedge clk) - ctr_q <= ctr_d; - - // Combinational code (boolean logic) - assign ctr_d = ctr_q + 1'b1; - assign tick_w = ctr_q[24]; - - assign fclk_w = tick_w; -endmodule diff --git a/examples/himbaechel/tangnano20k/shift.v b/examples/himbaechel/tangnano20k/shift.v deleted file mode 100644 index a33f3b1f..00000000 --- a/examples/himbaechel/tangnano20k/shift.v +++ /dev/null @@ -1,44 +0,0 @@ -module top ( - input clk, - input rst, - output [`LEDS_NR-1:0] led -); - -wire rst_s; -wire tick_hz; - -localparam HZ_PRESC = 12_000_000, - HZ_SIZE = $clog2(HZ_PRESC); - -reg [HZ_SIZE-1:0] hertz_cpt; -wire [HZ_SIZE-1:0] hertz_cpt_d = hertz_cpt - 1'b1; - -always @(posedge clk) begin - /* 1Hz clk */ - if (tick_hz) begin - hertz_cpt <= HZ_PRESC; - end else begin - hertz_cpt <= hertz_cpt_d; - end -end - - -reg [`LEDS_NR-1:0] ctr_q; -wire [`LEDS_NR-1:0] ctr_d; - -// Sequential code (flip-flop) -always @(posedge clk or posedge rst_s) begin - if (rst_s) begin - ctr_q <= 'd1; - end else if (tick_hz) begin - ctr_q <= ctr_d; - end -end - -// Combinational code (boolean logic) -assign ctr_d = {ctr_q[0], ctr_q[`LEDS_NR-1:1]}; -assign led = ctr_q; -assign tick_hz = (hertz_cpt == 0); -assign rst_s = rst; - -endmodule diff --git a/examples/himbaechel/tangnano20k/tlvds.v b/examples/himbaechel/tangnano20k/tlvds.v deleted file mode 100644 index 8b8656f2..00000000 --- a/examples/himbaechel/tangnano20k/tlvds.v +++ /dev/null @@ -1,31 +0,0 @@ -/* Using an oscilloscope you can see on pins tlvds_p and tlvds_n the signal with changing polarity. -* You can also use a 100 Ohm resistor and two LEDs connected in opposite directions between these pins. -*/ -module top ( - input clk, - output tlvds_p, - output tlvds_n, - input key -); - -reg [24:0] ctr_q; -wire [24:0] ctr_d; -wire i_tick; - -// Sequential code (flip-flop) -always @(posedge clk) - ctr_q <= ctr_d; - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign i_tick = |ctr_q[24:23]; - -TLVDS_TBUF diff_buf( - .OEN(key), - .O(tlvds_p), - .OB(tlvds_n), - .I(i_tick) - ); - -endmodule - From bfcdca64b8ae90b86a0ad1249e6b56b4b669f698 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Tue, 5 Sep 2023 16:28:07 +1000 Subject: [PATCH 2/6] Himbaechel. Bring examples for angnano20k back. The buttons on this board work the other way around, so you still need to have a set of examples for this board only. Signed-off-by: YRabbit --- examples/himbaechel/Makefile.himbaechel | 6 +- examples/himbaechel/tangnano20k/TOP.v | 106 ++++++++++++++ examples/himbaechel/tangnano20k/attosoc.v | 133 ++++++++++++++++++ examples/himbaechel/tangnano20k/blinky-oddr.v | 36 +++++ examples/himbaechel/tangnano20k/blinky-osc.v | 44 ++++++ examples/himbaechel/tangnano20k/blinky-tbuf.v | 25 ++++ examples/himbaechel/tangnano20k/blinky.v | 21 +++ examples/himbaechel/tangnano20k/elvds.v | 31 ++++ examples/himbaechel/tangnano20k/ides10.v | 52 +++++++ examples/himbaechel/tangnano20k/ides4.v | 29 ++++ examples/himbaechel/tangnano20k/ides8.v | 38 +++++ examples/himbaechel/tangnano20k/ivideo.v | 51 +++++++ examples/himbaechel/tangnano20k/oddr-elvds.v | 43 ++++++ examples/himbaechel/tangnano20k/oddr-tlvds.v | 44 ++++++ examples/himbaechel/tangnano20k/oser10.v | 74 ++++++++++ examples/himbaechel/tangnano20k/oser4.v | 57 ++++++++ examples/himbaechel/tangnano20k/oser8.v | 63 +++++++++ examples/himbaechel/tangnano20k/ovideo.v | 76 ++++++++++ examples/himbaechel/tangnano20k/shift.v | 44 ++++++ examples/himbaechel/tangnano20k/tlvds.v | 31 ++++ 20 files changed, 1001 insertions(+), 3 deletions(-) create mode 100644 examples/himbaechel/tangnano20k/TOP.v create mode 100644 examples/himbaechel/tangnano20k/attosoc.v create mode 100644 examples/himbaechel/tangnano20k/blinky-oddr.v create mode 100644 examples/himbaechel/tangnano20k/blinky-osc.v create mode 100644 examples/himbaechel/tangnano20k/blinky-tbuf.v create mode 100644 examples/himbaechel/tangnano20k/blinky.v create mode 100644 examples/himbaechel/tangnano20k/elvds.v create mode 100644 examples/himbaechel/tangnano20k/ides10.v create mode 100644 examples/himbaechel/tangnano20k/ides4.v create mode 100644 examples/himbaechel/tangnano20k/ides8.v create mode 100644 examples/himbaechel/tangnano20k/ivideo.v create mode 100644 examples/himbaechel/tangnano20k/oddr-elvds.v create mode 100644 examples/himbaechel/tangnano20k/oddr-tlvds.v create mode 100644 examples/himbaechel/tangnano20k/oser10.v create mode 100644 examples/himbaechel/tangnano20k/oser4.v create mode 100644 examples/himbaechel/tangnano20k/oser8.v create mode 100644 examples/himbaechel/tangnano20k/ovideo.v create mode 100644 examples/himbaechel/tangnano20k/shift.v create mode 100644 examples/himbaechel/tangnano20k/tlvds.v diff --git a/examples/himbaechel/Makefile.himbaechel b/examples/himbaechel/Makefile.himbaechel index 88ba0dcc..16729528 100644 --- a/examples/himbaechel/Makefile.himbaechel +++ b/examples/himbaechel/Makefile.himbaechel @@ -146,13 +146,13 @@ clean: %-tangnano20k.json: %-tangnano20k-synth.json tangnano20k.cst $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW2A-18C.bin --vopt partno=GW2AR-LV18QN88C8/I7 --vopt cst=tangnano20k.cst -%-tangnano20k-synth.json: %.v +%-tangnano20k-synth.json: tangnano20k/%.v $(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@" -pll-nanolcd-tangnano20k-synth.json: pll/GW2A-18-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v +pll-nanolcd-tangnano20k-synth.json: pll/GW2A-18-dyn.vh tangnano20k/TOP.v pll-nanolcd/VGAMod.v $(YOSYS) -p "read_verilog $^; synth_gowin -json $@" -attosoc-tangnano20k-synth.json: attosoc/attosoc.v attosoc/picorv32.v +attosoc-tangnano20k-synth.json: tangnano20k/attosoc.v attosoc/picorv32.v $(YOSYS) -p "read_verilog $^; synth_gowin -json $@" # ============================================================ diff --git a/examples/himbaechel/tangnano20k/TOP.v b/examples/himbaechel/tangnano20k/TOP.v new file mode 100644 index 00000000..9f5db57b --- /dev/null +++ b/examples/himbaechel/tangnano20k/TOP.v @@ -0,0 +1,106 @@ +(* top *) +module TOP +( + input rst, + input clk, + + output LCD_CLK, + output LCD_HYNC, + output LCD_SYNC, + output LCD_DEN, + output [4:0] LCD_R, + output [5:0] LCD_G, + output [4:0] LCD_B, + + output LED_R, + output LED_G, + output LED_B + +); + + wire CLK_SYS; + wire CLK_PIX; + +/* //使用内部时钟 + Gowin_OSC chip_osc( + .oscout(oscout_o) //output oscout + ); +*/ +rPLL pll( + .CLKOUT(CLK_PIX), // 9MHz + .CLKIN(clk), + .CLKFB(GND), + .RESET(GND), + .RESET_P(GND), + .FBDSEL({GND,GND,GND,GND,GND,GND}), + .IDSEL({GND,GND,GND,GND,GND,GND}), + .ODSEL({GND,GND,GND,GND,GND,GND}), + .DUTYDA({GND,GND,GND,GND}), + .PSDA({GND,GND,GND,GND}), + .FDLY({GND,GND,GND,GND}) + ); + defparam pll.DEVICE = `PLL_DEVICE; + defparam pll.FCLKIN = `PLL_FCLKIN; + defparam pll.FBDIV_SEL = `PLL_FBDIV_SEL_LCD; + defparam pll.IDIV_SEL = `PLL_IDIV_SEL_LCD; + defparam pll.ODIV_SEL = `PLL_ODIV_SEL; + defparam pll.CLKFB_SEL="internal"; + defparam pll.CLKOUTD3_SRC="CLKOUT"; + defparam pll.CLKOUTD_BYPASS="true"; + defparam pll.CLKOUTD_SRC="CLKOUT"; + defparam pll.CLKOUTP_BYPASS="false"; + defparam pll.CLKOUTP_DLY_STEP=0; + defparam pll.CLKOUTP_FT_DIR=1'b1; + defparam pll.CLKOUT_BYPASS="false"; + defparam pll.CLKOUT_DLY_STEP=0; + defparam pll.CLKOUT_FT_DIR=1'b1; + defparam pll.DUTYDA_SEL="1000"; + defparam pll.DYN_DA_EN="false"; + defparam pll.DYN_FBDIV_SEL="false"; + defparam pll.DYN_IDIV_SEL="false"; + defparam pll.DYN_ODIV_SEL="false"; + defparam pll.DYN_SDIV_SEL=1; // 9MHz --- pixel clock + defparam pll.PSDA_SEL="0000"; + + VGAMod D1 + ( + .CLK ( CLK_SYS ), + .nRST ( !rst ), + + .PixelClk ( CLK_PIX ), + .LCD_DE ( LCD_DEN ), + .LCD_HSYNC ( LCD_HYNC ), + .LCD_VSYNC ( LCD_SYNC ), + + .LCD_B ( LCD_B ), + .LCD_G ( LCD_G ), + .LCD_R ( LCD_R ) + ); + + assign LCD_CLK = CLK_PIX; + assign CLK_SYS = CLK_PIX; + + + //RGB LED TEST + reg [24:0] Count; + reg [1:0] rgb_data; + always @( posedge CLK_SYS or posedge rst ) + begin + if( rst ) + begin + Count <= 25'd0; + rgb_data <= 2'b00; + end + else if ( Count == 1200000 ) + begin + Count <= 4'b0; + rgb_data <= rgb_data + 1'b1; + end + else + Count <= Count + 1'b1; + end + assign LED_R = ~(rgb_data == 2'b01); + assign LED_G = ~(rgb_data == 2'b10); + assign LED_B = ~(rgb_data == 2'b11); + +endmodule diff --git a/examples/himbaechel/tangnano20k/attosoc.v b/examples/himbaechel/tangnano20k/attosoc.v new file mode 100644 index 00000000..9cbdc192 --- /dev/null +++ b/examples/himbaechel/tangnano20k/attosoc.v @@ -0,0 +1,133 @@ +/* + * ECP5 PicoRV32 demo + * + * Copyright (C) 2017 Clifford Wolf + * Copyright (C) 2018 David Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +`ifdef PICORV32_V +`error "attosoc.v must be read before picorv32.v!" +`endif + +`define PICORV32_REGS picosoc_regs + +(* top *) +module attosoc ( + input clk, + output reg [7:0] led +); + + wire lock_o; + wire clkoutp_o; + wire clkoutd_o; + wire clkoutd3_o; + + reg [5:0] reset_cnt = 0; + wire resetn = &reset_cnt; + + always @(posedge clk) begin + reset_cnt <= reset_cnt + !resetn; + end + + parameter integer MEM_WORDS = 256; + parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // ROM at 0x0 + parameter integer ROM_BYTES = 256; + + reg [7:0] rom [0:ROM_BYTES-1]; + wire [31:0] rom_rdata = {rom[mem_addr+3], rom[mem_addr+2], rom[mem_addr+1], rom[mem_addr+0]}; + initial $readmemh("attosoc/firmware.hex", rom); + + wire mem_valid; + wire mem_instr; + wire mem_ready; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [3:0] mem_wstrb; + wire [31:0] mem_rdata; + + wire rom_ready = mem_valid && mem_addr[31:24] == 8'h00; + + wire iomem_valid; + wire iomem_ready; + wire [31:0] iomem_addr; + wire [31:0] iomem_wdata; + wire [3:0] iomem_wstrb; + wire [31:0] iomem_rdata; + + assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01); + assign iomem_ready = 1'b1; + assign iomem_wstrb = mem_wstrb; + assign iomem_addr = mem_addr; + assign iomem_wdata = mem_wdata; + + wire [31:0] spimemio_cfgreg_do; + + + always @(posedge clk) + if (iomem_valid && iomem_wstrb[0]) + led <= iomem_wdata[7:0]; + + assign mem_ready = (iomem_valid && iomem_ready) || rom_ready; + + assign mem_rdata = rom_rdata; + + picorv32 #( + .STACKADDR(STACKADDR), + .PROGADDR_RESET(PROGADDR_RESET), + .PROGADDR_IRQ(32'h 0000_0000), + .BARREL_SHIFTER(0), + .COMPRESSED_ISA(0), + .ENABLE_MUL(0), + .ENABLE_DIV(0), + .ENABLE_IRQ(0), + .ENABLE_IRQ_QREGS(0) + ) cpu ( + .clk (clk ), + .resetn (resetn ), + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ) + ); + + + +endmodule + +// Implementation note: +// Replace the following two modules with wrappers for your SRAM cells. + +module picosoc_regs ( + input clk, wen, + input [5:0] waddr, + input [5:0] raddr1, + input [5:0] raddr2, + input [31:0] wdata, + output [31:0] rdata1, + output [31:0] rdata2 +); + reg [31:0] regs [0:31]; + + always @(posedge clk) + if (wen) regs[waddr[4:0]] <= wdata; + + assign rdata1 = regs[raddr1[4:0]]; + assign rdata2 = regs[raddr2[4:0]]; +endmodule diff --git a/examples/himbaechel/tangnano20k/blinky-oddr.v b/examples/himbaechel/tangnano20k/blinky-oddr.v new file mode 100644 index 00000000..cc10be89 --- /dev/null +++ b/examples/himbaechel/tangnano20k/blinky-oddr.v @@ -0,0 +1,36 @@ +/* +* led[0] is connected directly, led[1] --- via ODDR. This primitive needs 4 clock cycles to start working, so be patient:) +*/ +module top ( + input clk, + input key, + input rst, + output [`LEDS_NR-1:0] led +); + +reg [24:0] ctr_q; +wire [24:0] ctr_d; + +// Sequential code (flip-flop) +always @(posedge clk) begin + if (!rst) begin + ctr_q <= ctr_d; + end +end + +// Combinational code (boolean logic) +assign ctr_d = ctr_q + 1'b1; +assign led[`LEDS_NR-1:2] = {(`LEDS_NR - 2){1'b1}}; +assign led[0] = ctr_q[24:24]; + +ODDRC oddr_0( + .D0(1'b0), + .D1(1'b1), + .CLK(ctr_q[24:24]), + .Q0(led[1]), + .Q1(), + .TX(1'b1), + .CLEAR(key) +); + +endmodule diff --git a/examples/himbaechel/tangnano20k/blinky-osc.v b/examples/himbaechel/tangnano20k/blinky-osc.v new file mode 100644 index 00000000..f434a445 --- /dev/null +++ b/examples/himbaechel/tangnano20k/blinky-osc.v @@ -0,0 +1,44 @@ +module top ( + input rst, + output [`LEDS_NR-1:0] led +); + +wire clk; + +`ifdef OSC_TYPE_OSC +OSC osc( + .OSCOUT(clk) +); +`elsif OSC_TYPE_OSCZ +OSCZ osc( + .OSCEN(1'b1), + .OSCOUT(clk) +); +`elsif OSC_TYPE_OSCF +OSCF osc( + .OSCEN(1'b1), + .OSCOUT(clk), + .OSCOUT30M() +); +`elsif OSC_TYPE_OSCH +OSCH osc( + .OSCOUT(clk) +); +`endif +defparam osc.FREQ_DIV=16; + +reg [25:0] ctr_q; +wire [25:0] ctr_d; + +// Sequential code (flip-flop) +always @(posedge clk) begin + if (!rst) begin + ctr_q <= ctr_d; + end +end + +// Combinational code (boolean logic) +assign ctr_d = ctr_q + 1'b1; +assign led = ctr_q[25:25-(`LEDS_NR - 1)]; + +endmodule diff --git a/examples/himbaechel/tangnano20k/blinky-tbuf.v b/examples/himbaechel/tangnano20k/blinky-tbuf.v new file mode 100644 index 00000000..136e1f3f --- /dev/null +++ b/examples/himbaechel/tangnano20k/blinky-tbuf.v @@ -0,0 +1,25 @@ +module top ( + input clk, + input key, + output [`LEDS_NR-1:0] led +); + +reg [25:0] ctr_q; +wire [25:0] ctr_d; + +// Sequential code (flip-flop) +always @(posedge clk) begin + ctr_q <= ctr_d; +end + +// Combinational code (boolean logic) +assign ctr_d = ctr_q + 1'b1; +assign led[`LEDS_NR - 1:1] = ctr_q[25:25-(`LEDS_NR - 2)]; + +TBUF tbuf( + .I(ctr_q[25 - (`LEDS_NR - 1)]), + .O(led[0]), + .OEN(key) +); + +endmodule diff --git a/examples/himbaechel/tangnano20k/blinky.v b/examples/himbaechel/tangnano20k/blinky.v new file mode 100644 index 00000000..c8b0699b --- /dev/null +++ b/examples/himbaechel/tangnano20k/blinky.v @@ -0,0 +1,21 @@ +module top ( + input clk, + input key, + output [`LEDS_NR-1:0] led +); + +reg [25:0] ctr_q; +wire [25:0] ctr_d; + +// Sequential code (flip-flop) +always @(posedge clk) begin + if (!key) begin + ctr_q <= ctr_d; + end +end + +// Combinational code (boolean logic) +assign ctr_d = ctr_q + 1'b1; +assign led = ctr_q[25:25-(`LEDS_NR - 1)]; + +endmodule diff --git a/examples/himbaechel/tangnano20k/elvds.v b/examples/himbaechel/tangnano20k/elvds.v new file mode 100644 index 00000000..7fd20470 --- /dev/null +++ b/examples/himbaechel/tangnano20k/elvds.v @@ -0,0 +1,31 @@ +/* Using an oscilloscope you can see on pins tlvds_p and tlvds_n the signal with changing polarity. +* You can also use a 100 Ohm resistor and two LEDs connected in opposite directions between these pins. +*/ +module top ( + input clk, + output elvds_p, + output elvds_n, + input key +); + +reg [24:0] ctr_q; +wire [24:0] ctr_d; +wire i_tick; + +// Sequential code (flip-flop) +always @(posedge clk) + ctr_q <= ctr_d; + +// Combinational code (boolean logic) +assign ctr_d = ctr_q + 1'b1; +assign i_tick = |ctr_q[24:23]; + +ELVDS_TBUF diff_buf( + .OEN(key), + .O(elvds_p), + .OB(elvds_n), + .I(i_tick) + ); + +endmodule + diff --git a/examples/himbaechel/tangnano20k/ides10.v b/examples/himbaechel/tangnano20k/ides10.v new file mode 100644 index 00000000..70cd4ff8 --- /dev/null +++ b/examples/himbaechel/tangnano20k/ides10.v @@ -0,0 +1,52 @@ +`default_nettype none +module top(input wire clk, + input wire rst, + input wire fclk_i, + input wire data_i, + output wire pclk_o, + output wire [7:0]q_o); + + wire dummy[1:0]; + + IDES10 ides( + .D(data_i), + .FCLK(fclk_i), + .PCLK(pclk_o), + .CALIB(1'b0), + .RESET(rst), + .Q0(q_o[0]), + .Q1(q_o[1]), + .Q2(q_o[2]), + .Q3(q_o[3]), + .Q4(q_o[4]), + .Q5(q_o[5]), + .Q6(q_o[6]), + .Q7(q_o[7]), + .Q8(dummy[0]), + .Q9(dummy[1]) + ); + defparam ides.GSREN="false"; + defparam ides.LSREN="true"; + + // div by 5 + reg [2:0] count; + wire clkA; + reg clkB; + always @(posedge fclk_i) begin + if (rst) begin + count <= 0; + end else begin + if (count == 3'd4) begin + count <= 0; + end else begin + count <= count+1; + end + end + end + assign clkA = count[1]; + + always@(negedge fclk_i) begin + clkB <= clkA; + end + assign pclk_o = clkA | clkB; +endmodule diff --git a/examples/himbaechel/tangnano20k/ides4.v b/examples/himbaechel/tangnano20k/ides4.v new file mode 100644 index 00000000..6128eeef --- /dev/null +++ b/examples/himbaechel/tangnano20k/ides4.v @@ -0,0 +1,29 @@ +`default_nettype none +module top(input wire clk, + input wire rst, + input wire fclk_i, + input wire data_i, + output wire pclk_o, + output wire [7:0]q_o); + + IDES4 ides( + .D(data_i), + .FCLK(fclk_i), + .PCLK(pclk_o), + .CALIB(1'b0), + .RESET(rst), + .Q0(q_o[0]), + .Q1(q_o[1]), + .Q2(q_o[2]), + .Q3(q_o[3]) + ); + defparam ides.GSREN="false"; + defparam ides.LSREN="true"; + + reg pclk_r; + always @(posedge fclk_i) begin + pclk_r <= !pclk_r; + end + assign pclk_o = pclk_r; + +endmodule diff --git a/examples/himbaechel/tangnano20k/ides8.v b/examples/himbaechel/tangnano20k/ides8.v new file mode 100644 index 00000000..284a013c --- /dev/null +++ b/examples/himbaechel/tangnano20k/ides8.v @@ -0,0 +1,38 @@ +`default_nettype none +module top(input wire clk, + input wire rst, + input wire fclk_i, + input wire data_i, + output wire pclk_o, + output wire [7:0]q_o); + + IDES8 ides( + .D(data_i), + .FCLK(fclk_i), + .PCLK(pclk_o), + .CALIB(1'b0), + .RESET(rst), + .Q0(q_o[0]), + .Q1(q_o[1]), + .Q2(q_o[2]), + .Q3(q_o[3]), + .Q4(q_o[4]), + .Q5(q_o[5]), + .Q6(q_o[6]), + .Q7(q_o[7]), + ); + defparam ides.GSREN="false"; + defparam ides.LSREN="true"; + + reg [1:0]pclk_r; + + always @(posedge fclk_i) begin + if (rst) begin + pclk_r <= 2'b00; + end else begin + pclk_r <= pclk_r + 2'b01; + end + end + assign pclk_o = pclk_r[1]; + +endmodule diff --git a/examples/himbaechel/tangnano20k/ivideo.v b/examples/himbaechel/tangnano20k/ivideo.v new file mode 100644 index 00000000..fb1f4aef --- /dev/null +++ b/examples/himbaechel/tangnano20k/ivideo.v @@ -0,0 +1,51 @@ +`default_nettype none +module top(input wire clk, + input wire rst, + input wire fclk_i, + input wire data_i, + output wire pclk_o, + output wire [7:0]q_o); + + IVIDEO ides( + .D(data_i), + .FCLK(fclk_i), + .PCLK(pclk_o), + .CALIB(1'b0), + .RESET(rst), + .Q0(q_o[0]), + .Q1(q_o[1]), + .Q2(q_o[2]), + .Q3(q_o[3]), + .Q4(q_o[4]), + .Q5(q_o[5]), + .Q6(q_o[6]) + ); + defparam ides.GSREN="false"; + defparam ides.LSREN="true"; + + // div by 3.5 + reg [6:0]cnt_r; + reg ps0_r; + reg ps3_r; + reg ps4_r; + always @(posedge fclk_i) begin + if (rst) begin + cnt_r[6:0] <= 7'b000_0001; + end else begin + cnt_r[6:0] <= {cnt_r[5:0], cnt_r[6]}; + end + end + + always @(negedge fclk_i) begin + if (rst) begin + ps0_r <= 1'b0; + ps3_r <= 1'b0; + ps4_r <= 1'b0; + end else begin + ps0_r <= cnt_r[0]; + ps3_r <= cnt_r[3]; + ps4_r <= cnt_r[4]; + end + end + assign pclk_o = (ps0_r | cnt_r[0] | cnt_r[1]) | (ps3_r | ps4_r | cnt_r[4]); +endmodule diff --git a/examples/himbaechel/tangnano20k/oddr-elvds.v b/examples/himbaechel/tangnano20k/oddr-elvds.v new file mode 100644 index 00000000..91e49a0f --- /dev/null +++ b/examples/himbaechel/tangnano20k/oddr-elvds.v @@ -0,0 +1,43 @@ +/* Using an oscilloscope you can see on pins tlvds_p and tlvds_n the signal with changing polarity. +* You can also use a 100 Ohm resistor and two LEDs connected in opposite directions between these pins. +* ODDR needs 4 clock cycles to start working, so be patient:) +*/ +module top ( + input clk, + input key, + output elvds_p, + output elvds_n +); + +reg [24:0] ctr_q; +wire [24:0] ctr_d; +wire i_tick; +wire w_ddr; +wire oen; + +// Sequential code (flip-flop) +always @(posedge clk) + ctr_q <= ctr_d; + +// Combinational code (boolean logic) +assign ctr_d = ctr_q + 1'b1; +assign i_tick = |ctr_q[24:23]; + +ODDR oddr_0( + .D0(1'b0), + .D1(1'b1), + .CLK(i_tick), + .Q0(w_ddr), + .Q1(oen), + .TX(key) +); + +ELVDS_TBUF diff_buf( + .OEN(oen), + .O(elvds_p), + .OB(elvds_n), + .I(w_ddr) + ); + +endmodule + diff --git a/examples/himbaechel/tangnano20k/oddr-tlvds.v b/examples/himbaechel/tangnano20k/oddr-tlvds.v new file mode 100644 index 00000000..488ad76d --- /dev/null +++ b/examples/himbaechel/tangnano20k/oddr-tlvds.v @@ -0,0 +1,44 @@ +/* Using an oscilloscope you can see on pins tlvds_p and tlvds_n the signal with changing polarity. +* You can also use a 100 Ohm resistor and two LEDs connected in opposite directions between these pins. +* ODDR needs 4 clock cycles to start working, so be patient:) +*/ +module top ( + input clk, + input key, + output tlvds_p, + output tlvds_n +); + +reg [24:0] ctr_q; +wire [24:0] ctr_d; +wire i_tick; +wire w_ddr; + +// Sequential code (flip-flop) +always @(posedge clk) + ctr_q <= ctr_d; + +// Combinational code (boolean logic) +assign ctr_d = ctr_q + 1'b1; +assign i_tick = |ctr_q[24:23]; + +wire w_oen; + +ODDR oddr_0( + .D0(1'b0), + .D1(1'b1), + .CLK(i_tick), + .Q0(w_ddr), + .Q1(w_oen), + .TX(key) +); + +TLVDS_TBUF diff_buf( + .OEN(w_oen), + .O(tlvds_p), + .OB(tlvds_n), + .I(w_ddr) + ); + +endmodule + diff --git a/examples/himbaechel/tangnano20k/oser10.v b/examples/himbaechel/tangnano20k/oser10.v new file mode 100644 index 00000000..41039d01 --- /dev/null +++ b/examples/himbaechel/tangnano20k/oser10.v @@ -0,0 +1,74 @@ +`default_nettype none +/* +* This example allows you to generate several OSER10 primitives and then check +* them with a logic analyzer. The PCLK, FCLK and Q outputs of the primitives +* are connected to the board pins. +*/ +module top(input wire clk, + input wire rst, + output wire oser_out, + output wire pclk_o, + output wire fclk_o); + + OSER10 os( + .D0(1'b0), + .D1(1'b1), + .D2(1'b0), + .D3(1'b1), + .D4(1'b0), + .D5(1'b1), + .D6(1'b0), + .D7(1'b1), + .D8(1'b0), + .D9(1'b1), + .FCLK(fclk_w), + .PCLK(pclk_w), + .RESET(1'b0), + .Q(oser_out) + ); + defparam os.GSREN = "false"; + defparam os.LSREN = "true"; + + wire clk_w; + wire pclk_w; + wire fclk_w; + + assign pclk_o = pclk_w; + assign fclk_o = fclk_w; + + reg [2:0] count; + wire clkA; + reg clkB; + always @(posedge fclk_w) begin + if (rst) begin + count <= 0; + end else begin + if (count == 3'd4) begin + count <= 0; + end else begin + count <= count+1; + end + end + end + assign clkA = count[1]; + + always@(negedge fclk_w) begin + clkB <= clkA; + end + assign pclk_w = clkA | clkB; + + // slow + reg [24:0] ctr_q; + wire [24:0] ctr_d; + wire tick_w; + + // Sequential code (flip-flop) + always @(posedge clk) + ctr_q <= ctr_d; + + // Combinational code (boolean logic) + assign ctr_d = ctr_q + 1'b1; + assign tick_w = ctr_q[24]; + + assign fclk_w = tick_w; +endmodule diff --git a/examples/himbaechel/tangnano20k/oser4.v b/examples/himbaechel/tangnano20k/oser4.v new file mode 100644 index 00000000..a4038488 --- /dev/null +++ b/examples/himbaechel/tangnano20k/oser4.v @@ -0,0 +1,57 @@ +`default_nettype none +/* +* This example allows you to generate several OSER10 primitives and then check +* them with a logic analyzer. The PCLK, FCLK and Q outputs of the primitives +* are connected to the board pins. +*/ +module top(input wire clk, + input wire rst, + output wire oser_out, + output wire pclk_o, + output wire fclk_o); + + OSER4 os( + .D0(1'b0), + .D1(1'b1), + .D2(1'b0), + .D3(1'b1), + .TX0(1'b1), + .TX1(1'b1), + .FCLK(fclk_w), + .PCLK(pclk_w), + .RESET(1'b0), + .Q0(oser_out), + .Q1() + ); + defparam os.GSREN = "false"; + defparam os.LSREN = "true"; + + wire clk_w; + wire pclk_w; + wire fclk_w; + + assign pclk_o = pclk_w; + assign fclk_o = fclk_w; + + reg clkB; + + always@(negedge fclk_w) begin + clkB <= ~clkB; + end + assign pclk_w = clkB; + + // slow + reg [24:0] ctr_q; + wire [24:0] ctr_d; + wire tick_w; + + // Sequential code (flip-flop) + always @(posedge clk) + ctr_q <= ctr_d; + + // Combinational code (boolean logic) + assign ctr_d = ctr_q + 1'b1; + assign tick_w = ctr_q[24]; + + assign fclk_w = tick_w; +endmodule diff --git a/examples/himbaechel/tangnano20k/oser8.v b/examples/himbaechel/tangnano20k/oser8.v new file mode 100644 index 00000000..1d829976 --- /dev/null +++ b/examples/himbaechel/tangnano20k/oser8.v @@ -0,0 +1,63 @@ +`default_nettype none +/* +* This example allows you to generate several OSER10 primitives and then check +* them with a logic analyzer. The PCLK, FCLK and Q outputs of the primitives +* are connected to the board pins. +*/ +module top(input wire clk, + input wire rst, + output wire oser_out, + output wire pclk_o, + output wire fclk_o); + + OSER8 os( + .D0(1'b0), + .D1(1'b1), + .D2(1'b0), + .D3(1'b1), + .D4(1'b0), + .D5(1'b1), + .D6(1'b0), + .D7(1'b1), + .TX0(1'b1), + .TX1(1'b1), + .TX2(1'b1), + .TX3(1'b1), + .FCLK(fclk_w), + .PCLK(pclk_r[1]), + .RESET(1'b0), + .Q0(oser_out) + ); + defparam os.GSREN = "false"; + defparam os.LSREN = "true"; + defparam os.TXCLK_POL = 0; + defparam os.HWL = "false"; + + reg [1:0]pclk_r; + wire fclk_w; + + always @(posedge fclk_w) begin + if (rst) begin + pclk_r <= 2'b00; + end else begin + pclk_r <= pclk_r + 2'b01; + end + end + assign pclk_o = pclk_r[1]; + assign fclk_o = fclk_w; + + // slow + reg [24:0] ctr_q; + wire [24:0] ctr_d; + wire tick_w; + + // Sequential code (flip-flop) + always @(posedge clk) + ctr_q <= ctr_d; + + // Combinational code (boolean logic) + assign ctr_d = ctr_q + 1'b1; + assign tick_w = ctr_q[24]; + + assign fclk_w = tick_w; +endmodule diff --git a/examples/himbaechel/tangnano20k/ovideo.v b/examples/himbaechel/tangnano20k/ovideo.v new file mode 100644 index 00000000..966a2837 --- /dev/null +++ b/examples/himbaechel/tangnano20k/ovideo.v @@ -0,0 +1,76 @@ +`default_nettype none +/* +* This example allows you to generate several OSER10 primitives and then check +* them with a logic analyzer. The PCLK, FCLK and Q outputs of the primitives +* are connected to the board pins. +*/ +module top(input wire clk, + input wire rst, + output wire oser_out, + output wire pclk_o, + output wire fclk_o); + + OVIDEO os( + .D0(1'b1), + .D1(1'b0), + .D2(1'b1), + .D3(1'b0), + .D4(1'b1), + .D5(1'b0), + .D6(1'b1), + .FCLK(fclk_w), + .PCLK(pclk_w), + .RESET(1'b0), + .Q(oser_out) + ); + defparam os.GSREN = "false"; + defparam os.LSREN = "true"; + + wire clk_w; + wire pclk_w; + wire fclk_w; + + assign pclk_o = pclk_w; + assign fclk_o = fclk_w; + + // div by 3.5 + reg [6:0]cnt_r; + reg ps0_r; + reg ps3_r; + reg ps4_r; + always @(posedge fclk_w) begin + if (rst) begin + cnt_r[6:0] <= 7'b000_0001; + end else begin + cnt_r[6:0] <= {cnt_r[5:0], cnt_r[6]}; + end + end + + always @(negedge fclk_w) begin + if (rst) begin + ps0_r <= 1'b0; + ps3_r <= 1'b0; + ps4_r <= 1'b0; + end else begin + ps0_r <= cnt_r[0]; + ps3_r <= cnt_r[3]; + ps4_r <= cnt_r[4]; + end + end + assign pclk_w = (ps0_r | cnt_r[0] | cnt_r[1]) | (ps3_r | ps4_r | cnt_r[4]); + + // slow + reg [24:0] ctr_q; + wire [24:0] ctr_d; + wire tick_w; + + // Sequential code (flip-flop) + always @(posedge clk) + ctr_q <= ctr_d; + + // Combinational code (boolean logic) + assign ctr_d = ctr_q + 1'b1; + assign tick_w = ctr_q[24]; + + assign fclk_w = tick_w; +endmodule diff --git a/examples/himbaechel/tangnano20k/shift.v b/examples/himbaechel/tangnano20k/shift.v new file mode 100644 index 00000000..a33f3b1f --- /dev/null +++ b/examples/himbaechel/tangnano20k/shift.v @@ -0,0 +1,44 @@ +module top ( + input clk, + input rst, + output [`LEDS_NR-1:0] led +); + +wire rst_s; +wire tick_hz; + +localparam HZ_PRESC = 12_000_000, + HZ_SIZE = $clog2(HZ_PRESC); + +reg [HZ_SIZE-1:0] hertz_cpt; +wire [HZ_SIZE-1:0] hertz_cpt_d = hertz_cpt - 1'b1; + +always @(posedge clk) begin + /* 1Hz clk */ + if (tick_hz) begin + hertz_cpt <= HZ_PRESC; + end else begin + hertz_cpt <= hertz_cpt_d; + end +end + + +reg [`LEDS_NR-1:0] ctr_q; +wire [`LEDS_NR-1:0] ctr_d; + +// Sequential code (flip-flop) +always @(posedge clk or posedge rst_s) begin + if (rst_s) begin + ctr_q <= 'd1; + end else if (tick_hz) begin + ctr_q <= ctr_d; + end +end + +// Combinational code (boolean logic) +assign ctr_d = {ctr_q[0], ctr_q[`LEDS_NR-1:1]}; +assign led = ctr_q; +assign tick_hz = (hertz_cpt == 0); +assign rst_s = rst; + +endmodule diff --git a/examples/himbaechel/tangnano20k/tlvds.v b/examples/himbaechel/tangnano20k/tlvds.v new file mode 100644 index 00000000..8b8656f2 --- /dev/null +++ b/examples/himbaechel/tangnano20k/tlvds.v @@ -0,0 +1,31 @@ +/* Using an oscilloscope you can see on pins tlvds_p and tlvds_n the signal with changing polarity. +* You can also use a 100 Ohm resistor and two LEDs connected in opposite directions between these pins. +*/ +module top ( + input clk, + output tlvds_p, + output tlvds_n, + input key +); + +reg [24:0] ctr_q; +wire [24:0] ctr_d; +wire i_tick; + +// Sequential code (flip-flop) +always @(posedge clk) + ctr_q <= ctr_d; + +// Combinational code (boolean logic) +assign ctr_d = ctr_q + 1'b1; +assign i_tick = |ctr_q[24:23]; + +TLVDS_TBUF diff_buf( + .OEN(key), + .O(tlvds_p), + .OB(tlvds_n), + .I(i_tick) + ); + +endmodule + From e14fba2c73c9901f657f085511d2b1b27331d4a9 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Tue, 5 Sep 2023 20:17:50 +1000 Subject: [PATCH 3/6] Himbaechel. Unify examples. As suggested by the Pepijn de Vos button, the buttons are treated uniformly, the difference is taken into account in the synthesis via a command line parameter. Signed-off-by: YRabbit --- examples/himbaechel/Makefile.himbaechel | 46 +++--- examples/himbaechel/blinky-oddr.v | 7 +- examples/himbaechel/blinky-osc.v | 4 +- examples/himbaechel/blinky-pll-vr.v | 3 +- examples/himbaechel/blinky-pll.v | 3 +- examples/himbaechel/blinky-tbuf.v | 4 +- examples/himbaechel/blinky.v | 4 +- examples/himbaechel/elvds.v | 4 +- examples/himbaechel/ides10.v | 3 +- examples/himbaechel/ides16.v | 3 +- examples/himbaechel/ides4.v | 3 +- examples/himbaechel/ides8.v | 3 +- examples/himbaechel/ivideo.v | 3 +- examples/himbaechel/oddr-elvds.v | 4 +- examples/himbaechel/oddr-tlvds.v | 3 +- examples/himbaechel/oser10.v | 3 +- examples/himbaechel/oser16.v | 3 +- examples/himbaechel/oser4.v | 3 +- examples/himbaechel/oser8.v | 3 +- examples/himbaechel/ovideo.v | 3 +- examples/himbaechel/pll-nanolcd/TOP.v | 3 +- examples/himbaechel/primer20k.cst | 4 +- examples/himbaechel/runber.cst | 4 +- examples/himbaechel/shift.v | 3 +- examples/himbaechel/szfpga.cst | 4 +- examples/himbaechel/tangnano.cst | 4 +- examples/himbaechel/tangnano1k.cst | 8 +- examples/himbaechel/tangnano20k.cst | 8 +- examples/himbaechel/tangnano20k/TOP.v | 106 -------------- examples/himbaechel/tangnano20k/attosoc.v | 133 ------------------ examples/himbaechel/tangnano20k/blinky-oddr.v | 36 ----- examples/himbaechel/tangnano20k/blinky-osc.v | 44 ------ examples/himbaechel/tangnano20k/blinky-tbuf.v | 25 ---- examples/himbaechel/tangnano20k/blinky.v | 21 --- examples/himbaechel/tangnano20k/elvds.v | 31 ---- examples/himbaechel/tangnano20k/ides10.v | 52 ------- examples/himbaechel/tangnano20k/ides4.v | 29 ---- examples/himbaechel/tangnano20k/ides8.v | 38 ----- examples/himbaechel/tangnano20k/ivideo.v | 51 ------- examples/himbaechel/tangnano20k/oddr-elvds.v | 43 ------ examples/himbaechel/tangnano20k/oddr-tlvds.v | 44 ------ examples/himbaechel/tangnano20k/oser10.v | 74 ---------- examples/himbaechel/tangnano20k/oser4.v | 57 -------- examples/himbaechel/tangnano20k/oser8.v | 63 --------- examples/himbaechel/tangnano20k/ovideo.v | 76 ---------- examples/himbaechel/tangnano20k/shift.v | 44 ------ examples/himbaechel/tangnano20k/tlvds.v | 31 ---- examples/himbaechel/tangnano4k.cst | 4 +- examples/himbaechel/tangnano9k.cst | 4 +- examples/himbaechel/tec0117.cst | 4 +- examples/himbaechel/tlvds.v | 3 +- 51 files changed, 97 insertions(+), 1066 deletions(-) delete mode 100644 examples/himbaechel/tangnano20k/TOP.v delete mode 100644 examples/himbaechel/tangnano20k/attosoc.v delete mode 100644 examples/himbaechel/tangnano20k/blinky-oddr.v delete mode 100644 examples/himbaechel/tangnano20k/blinky-osc.v delete mode 100644 examples/himbaechel/tangnano20k/blinky-tbuf.v delete mode 100644 examples/himbaechel/tangnano20k/blinky.v delete mode 100644 examples/himbaechel/tangnano20k/elvds.v delete mode 100644 examples/himbaechel/tangnano20k/ides10.v delete mode 100644 examples/himbaechel/tangnano20k/ides4.v delete mode 100644 examples/himbaechel/tangnano20k/ides8.v delete mode 100644 examples/himbaechel/tangnano20k/ivideo.v delete mode 100644 examples/himbaechel/tangnano20k/oddr-elvds.v delete mode 100644 examples/himbaechel/tangnano20k/oddr-tlvds.v delete mode 100644 examples/himbaechel/tangnano20k/oser10.v delete mode 100644 examples/himbaechel/tangnano20k/oser4.v delete mode 100644 examples/himbaechel/tangnano20k/oser8.v delete mode 100644 examples/himbaechel/tangnano20k/ovideo.v delete mode 100644 examples/himbaechel/tangnano20k/shift.v delete mode 100644 examples/himbaechel/tangnano20k/tlvds.v diff --git a/examples/himbaechel/Makefile.himbaechel b/examples/himbaechel/Makefile.himbaechel index 16729528..06930bda 100644 --- a/examples/himbaechel/Makefile.himbaechel +++ b/examples/himbaechel/Makefile.himbaechel @@ -146,14 +146,14 @@ clean: %-tangnano20k.json: %-tangnano20k-synth.json tangnano20k.cst $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW2A-18C.bin --vopt partno=GW2AR-LV18QN88C8/I7 --vopt cst=tangnano20k.cst -%-tangnano20k-synth.json: tangnano20k/%.v - $(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@" +%-tangnano20k-synth.json: %.v + $(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -D INV_BTN=1 -p "read_verilog $^; synth_gowin -json $@" -pll-nanolcd-tangnano20k-synth.json: pll/GW2A-18-dyn.vh tangnano20k/TOP.v pll-nanolcd/VGAMod.v - $(YOSYS) -p "read_verilog $^; synth_gowin -json $@" +pll-nanolcd-tangnano20k-synth.json: pll/GW2A-18-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v + $(YOSYS) -D INV_BTN=1 -p "read_verilog $^; synth_gowin -json $@" -attosoc-tangnano20k-synth.json: tangnano20k/attosoc.v attosoc/picorv32.v - $(YOSYS) -p "read_verilog $^; synth_gowin -json $@" +attosoc-tangnano20k-synth.json: attosoc/attosoc.v attosoc/picorv32.v + $(YOSYS) -D INV_BTN=1 -p "read_verilog $^; synth_gowin -json $@" # ============================================================ # TangPrimer20k @@ -164,13 +164,13 @@ attosoc-tangnano20k-synth.json: tangnano20k/attosoc.v attosoc/picorv32.v $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW2A-18.bin --vopt partno=GW2A-LV18PG256C8/I7 --vopt cst=primer20k.cst %-primer20k-synth.json: %.v - $(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" pll-nanolcd-primer20k-synth.json: pll/GW2A-18-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v - $(YOSYS) -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" attosoc-%-synth.json: attosoc/attosoc.v attosoc/picorv32.v - $(YOSYS) -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" # ============================================================ # Tangnano (GW1N-1) @@ -181,10 +181,10 @@ attosoc-%-synth.json: attosoc/attosoc.v attosoc/picorv32.v $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-1.bin --vopt partno=GW1N-LV1QN48C6/I5 --vopt cst=tangnano.cst %-tangnano-synth.json: %.v - $(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCH -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCH -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" pll-nanolcd-tangnano-synth.json: pll/GW1N-1-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v - $(YOSYS) -p "read_verilog $^; synth_gowin -noalu -json $@" + $(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -noalu -json $@" # ============================================================ # Tangnano1k (GW1NZ-1) @@ -195,13 +195,13 @@ pll-nanolcd-tangnano-synth.json: pll/GW1N-1-dyn.vh pll-nanolcd/TOP.v pll-nanolcd $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1NZ-1.bin --vopt partno=GW1NZ-LV1QN48C6/I5 --vopt cst=tangnano1k.cst %-tangnano1k-synth.json: %.v - $(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCZ -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCZ -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" pll-nanolcd-tangnano1k.fs: pll-nanolcd-tangnano1k.json gowin_pack -d GW1NZ-1 --sspi_as_gpio --mspi_as_gpio -o $@ $^ pll-nanolcd-tangnano1k-synth.json: pll/GW1NZ-1-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v - $(YOSYS) -p "read_verilog $^; synth_gowin -noalu -json $@" + $(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -noalu -json $@" # ============================================================ # Tangnano4k (GW1NS-4) @@ -212,10 +212,10 @@ pll-nanolcd-tangnano1k-synth.json: pll/GW1NZ-1-dyn.vh pll-nanolcd/TOP.v pll-nano $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1NS-4.bin --vopt partno=GW1NSR-LV4CQN48PC7/I6 --vopt cst=tangnano4k.cst %-tangnano4k-synth.json: %.v - $(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSCZ -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSCZ -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" blinky-pll-tangnano4k-synth.json: pll/GW1NS-4-dyn.vh blinky-pll-vr.v - $(YOSYS) -D LEDS_NR=6 -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D INV_BTN=0 -D LEDS_NR=6 -p "read_verilog $^; synth_gowin -json $@" # ============================================================ # Tangnano9k (GW1N-9C) @@ -226,10 +226,10 @@ blinky-pll-tangnano4k-synth.json: pll/GW1NS-4-dyn.vh blinky-pll-vr.v $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-9C.bin --vopt partno=GW1NR-LV9QN88PC6/I5 --vopt cst=tangnano9k.cst %-tangnano9k-synth.json: %.v - $(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" pll-nanolcd-tangnano9k-synth.json: pll/GW1N-9C-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v - $(YOSYS) -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" pll-nanolcd-tangnano9k.fs: pll-nanolcd-tangnano9k.json gowin_pack -d GW1N-9C --sspi_as_gpio --mspi_as_gpio -o $@ $^ @@ -243,10 +243,10 @@ pll-nanolcd-tangnano9k.fs: pll-nanolcd-tangnano9k.json $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-9.bin --vopt partno=GW1NR-LV9LQ144PC6/I5 --vopt cst=szfpga.cst %-szfpga-synth.json: %.v - $(YOSYS) -D LEDS_NR=4 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D LEDS_NR=4 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" blinky-pll-szfpga-synth.json: pll/GW1N-9-dyn.vh blinky-pll.v - $(YOSYS) -D LEDS_NR=4 -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D INV_BTN=0 -D LEDS_NR=4 -p "read_verilog $^; synth_gowin -json $@" # ============================================================ # tec0117 (GW1N-9) @@ -257,10 +257,10 @@ blinky-pll-szfpga-synth.json: pll/GW1N-9-dyn.vh blinky-pll.v $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-9.bin --vopt partno=GW1NR-LV9QN88C6/I5 --vopt cst=tec0117.cst %-tec0117-synth.json: %.v - $(YOSYS) -D LEDS_NR=8 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D LEDS_NR=8 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" blinky-pll-tec0117-synth.json: pll/GW1N-9-dyn.vh blinky-pll.v - $(YOSYS) -D LEDS_NR=8 -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D INV_BTN=0 -D LEDS_NR=8 -p "read_verilog $^; synth_gowin -json $@" # ============================================================ # runber (GW1N-4) @@ -271,10 +271,10 @@ blinky-pll-tec0117-synth.json: pll/GW1N-9-dyn.vh blinky-pll.v $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-4.bin --vopt partno=GW1N-UV4LQ144C6/I5 --vopt cst=runber.cst %-runber-synth.json: %.v - $(YOSYS) -D LEDS_NR=8 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D LEDS_NR=8 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" blinky-pll-runber-synth.json: pll/GW1N-4-dyn.vh blinky-pll.v - $(YOSYS) -D LEDS_NR=8 -p "read_verilog $^; synth_gowin -json $@" + $(YOSYS) -D INV_BTN=0 -D LEDS_NR=8 -p "read_verilog $^; synth_gowin -json $@" # ============================================================ # Upack diff --git a/examples/himbaechel/blinky-oddr.v b/examples/himbaechel/blinky-oddr.v index c44daa4f..79b104e9 100644 --- a/examples/himbaechel/blinky-oddr.v +++ b/examples/himbaechel/blinky-oddr.v @@ -3,11 +3,14 @@ */ module top ( input clk, - input key, - input rst, + input key_i, + input rst_i, output [`LEDS_NR-1:0] led ); +wire key = key_i ^ `INV_BTN; +wire rst = rst_i ^ `INV_BTN; + reg [24:0] ctr_q; wire [24:0] ctr_d; diff --git a/examples/himbaechel/blinky-osc.v b/examples/himbaechel/blinky-osc.v index 5789b090..154fc3d5 100644 --- a/examples/himbaechel/blinky-osc.v +++ b/examples/himbaechel/blinky-osc.v @@ -1,5 +1,5 @@ module top ( - input key, + input key_i, output [`LEDS_NR-1:0] led ); @@ -27,6 +27,8 @@ OSCH osc( `endif defparam osc.FREQ_DIV=16; +wire key = key_i ^ `INV_BTN; + reg [25:0] ctr_q; wire [25:0] ctr_d; diff --git a/examples/himbaechel/blinky-pll-vr.v b/examples/himbaechel/blinky-pll-vr.v index 2c83b64a..bcb2df33 100644 --- a/examples/himbaechel/blinky-pll-vr.v +++ b/examples/himbaechel/blinky-pll-vr.v @@ -1,6 +1,6 @@ (* top *) module top ( - input key, + input key_i, input clk, output [`LEDS_NR-1:0] led ); @@ -46,6 +46,7 @@ defparam pllvr_inst.CLKOUTD_SRC = "CLKOUTP"; defparam pllvr_inst.CLKOUTD3_SRC = "CLKOUTP"; defparam pllvr_inst.DEVICE = "GW1NSR-4C"; +wire key = key_i ^ `INV_BTN; reg [25:0] ctr_q; wire [25:0] ctr_d; diff --git a/examples/himbaechel/blinky-pll.v b/examples/himbaechel/blinky-pll.v index bc386a15..a1b99f82 100644 --- a/examples/himbaechel/blinky-pll.v +++ b/examples/himbaechel/blinky-pll.v @@ -1,6 +1,6 @@ (* top *) module top ( - input key, + input key_i, input clk, output [`LEDS_NR-1:0] led ); @@ -43,6 +43,7 @@ rPLL pll( defparam pll.DYN_SDIV_SEL=1; // 9MHz --- pixel clock defparam pll.PSDA_SEL="0000"; +wire key = key_i ^ `INV_BTN; reg [25:0] ctr_q; wire [25:0] ctr_d; diff --git a/examples/himbaechel/blinky-tbuf.v b/examples/himbaechel/blinky-tbuf.v index c35fd4b4..7759332c 100644 --- a/examples/himbaechel/blinky-tbuf.v +++ b/examples/himbaechel/blinky-tbuf.v @@ -1,9 +1,11 @@ module top ( input clk, - input key, + input key_i, output [`LEDS_NR-1:0] led ); +wire key = key_i ^ `INV_BTN; + reg [25:0] ctr_q; wire [25:0] ctr_d; diff --git a/examples/himbaechel/blinky.v b/examples/himbaechel/blinky.v index eec6a46c..2df4ea18 100644 --- a/examples/himbaechel/blinky.v +++ b/examples/himbaechel/blinky.v @@ -1,9 +1,11 @@ module top ( input clk, - input key, + input key_i, output [`LEDS_NR-1:0] led ); +wire key = key_i ^ `INV_BTN; + reg [25:0] ctr_q; wire [25:0] ctr_d; diff --git a/examples/himbaechel/elvds.v b/examples/himbaechel/elvds.v index afc6e26d..cca35a3b 100644 --- a/examples/himbaechel/elvds.v +++ b/examples/himbaechel/elvds.v @@ -5,9 +5,11 @@ module top ( input clk, output elvds_p, output elvds_n, - input key + input key_i ); +wire key = key_i ^ `INV_BTN; + reg [24:0] ctr_q; wire [24:0] ctr_d; wire i_tick; diff --git a/examples/himbaechel/ides10.v b/examples/himbaechel/ides10.v index ed17ec1b..ab342f65 100644 --- a/examples/himbaechel/ides10.v +++ b/examples/himbaechel/ides10.v @@ -1,11 +1,12 @@ `default_nettype none module top(input wire clk, - input wire rst, + input wire rst_i, input wire fclk_i, input wire data_i, output wire pclk_o, output wire [7:0]q_o); + wire rst = rst_i ^ `INV_BTN; wire dummy[1:0]; IDES10 ides( diff --git a/examples/himbaechel/ides16.v b/examples/himbaechel/ides16.v index 24714133..01844dac 100644 --- a/examples/himbaechel/ides16.v +++ b/examples/himbaechel/ides16.v @@ -1,11 +1,12 @@ `default_nettype none module top(input wire clk, - input wire rst, + input wire rst_i, input wire fclk_i, input wire data_i, output wire pclk_o, output wire [7:0]q_o); + wire rst = rst_i ^ `INV_BTN; wire [7:0]dummy_w; IDES16 ides( diff --git a/examples/himbaechel/ides4.v b/examples/himbaechel/ides4.v index 16176c28..9e513b30 100644 --- a/examples/himbaechel/ides4.v +++ b/examples/himbaechel/ides4.v @@ -1,11 +1,12 @@ `default_nettype none module top(input wire clk, - input wire rst, + input wire rst_i, input wire fclk_i, input wire data_i, output wire pclk_o, output wire [7:0]q_o); + wire rst = rst_i ^ `INV_BTN; IDES4 ides( .D(data_i), .FCLK(fclk_i), diff --git a/examples/himbaechel/ides8.v b/examples/himbaechel/ides8.v index 1498cda5..7e0a2314 100644 --- a/examples/himbaechel/ides8.v +++ b/examples/himbaechel/ides8.v @@ -1,11 +1,12 @@ `default_nettype none module top(input wire clk, - input wire rst, + input wire rst_i, input wire fclk_i, input wire data_i, output wire pclk_o, output wire [7:0]q_o); + wire rst = rst_i ^ `INV_BTN; IDES8 ides( .D(data_i), .FCLK(fclk_i), diff --git a/examples/himbaechel/ivideo.v b/examples/himbaechel/ivideo.v index 9a265795..4775fd1c 100644 --- a/examples/himbaechel/ivideo.v +++ b/examples/himbaechel/ivideo.v @@ -1,11 +1,12 @@ `default_nettype none module top(input wire clk, - input wire rst, + input wire rst_i, input wire fclk_i, input wire data_i, output wire pclk_o, output wire [7:0]q_o); + wire rst = rst_i ^ `INV_BTN; IVIDEO ides( .D(data_i), .FCLK(fclk_i), diff --git a/examples/himbaechel/oddr-elvds.v b/examples/himbaechel/oddr-elvds.v index 0dc43e03..b7142ffb 100644 --- a/examples/himbaechel/oddr-elvds.v +++ b/examples/himbaechel/oddr-elvds.v @@ -4,11 +4,13 @@ */ module top ( input clk, - input key, + input key_i, output elvds_p, output elvds_n ); +wire key = key_i ^ `INV_BTN; + reg [24:0] ctr_q; wire [24:0] ctr_d; wire i_tick; diff --git a/examples/himbaechel/oddr-tlvds.v b/examples/himbaechel/oddr-tlvds.v index 97783304..6b28b0d6 100644 --- a/examples/himbaechel/oddr-tlvds.v +++ b/examples/himbaechel/oddr-tlvds.v @@ -4,11 +4,12 @@ */ module top ( input clk, - input key, + input key_i, output tlvds_p, output tlvds_n ); +wire key = key_i ^ `INV_BTN; reg [24:0] ctr_q; wire [24:0] ctr_d; wire i_tick; diff --git a/examples/himbaechel/oser10.v b/examples/himbaechel/oser10.v index 0d97c769..add93453 100644 --- a/examples/himbaechel/oser10.v +++ b/examples/himbaechel/oser10.v @@ -5,11 +5,12 @@ * are connected to the board pins. */ module top(input wire clk, - input wire rst, + input wire rst_i, output wire oser_out, output wire pclk_o, output wire fclk_o); + wire rst = rst_i ^ `INV_BTN; OSER10 os( .D0(1'b0), .D1(1'b1), diff --git a/examples/himbaechel/oser16.v b/examples/himbaechel/oser16.v index 58cab673..1186ba2a 100644 --- a/examples/himbaechel/oser16.v +++ b/examples/himbaechel/oser16.v @@ -5,11 +5,12 @@ * are connected to the board pins. */ module top(input wire clk, - input wire rst, + input wire rst_i, output wire io16, output wire pclk_o, output wire fclk_o); + wire rst = rst_i ^ `INV_BTN; OSER16 oser( .D0(1'b0), .D1(1'b1), diff --git a/examples/himbaechel/oser4.v b/examples/himbaechel/oser4.v index a4038488..3bda8d63 100644 --- a/examples/himbaechel/oser4.v +++ b/examples/himbaechel/oser4.v @@ -5,11 +5,12 @@ * are connected to the board pins. */ module top(input wire clk, - input wire rst, + input wire rst_i, output wire oser_out, output wire pclk_o, output wire fclk_o); + wire rst = rst_i ^ `INV_BTN; OSER4 os( .D0(1'b0), .D1(1'b1), diff --git a/examples/himbaechel/oser8.v b/examples/himbaechel/oser8.v index bfc79746..ccb687b5 100644 --- a/examples/himbaechel/oser8.v +++ b/examples/himbaechel/oser8.v @@ -5,11 +5,12 @@ * are connected to the board pins. */ module top(input wire clk, - input wire rst, + input wire rst_i, output wire oser_out, output wire pclk_o, output wire fclk_o); + wire rst = rst_i ^ `INV_BTN; OSER8 os( .D0(1'b0), .D1(1'b1), diff --git a/examples/himbaechel/ovideo.v b/examples/himbaechel/ovideo.v index 7ed46c93..cd539f68 100644 --- a/examples/himbaechel/ovideo.v +++ b/examples/himbaechel/ovideo.v @@ -5,11 +5,12 @@ * are connected to the board pins. */ module top(input wire clk, - input wire rst, + input wire rst_i, output wire oser_out, output wire pclk_o, output wire fclk_o); + wire rst = rst_i ^ `INV_BTN; OVIDEO os( .D0(1'b1), .D1(1'b0), diff --git a/examples/himbaechel/pll-nanolcd/TOP.v b/examples/himbaechel/pll-nanolcd/TOP.v index 34d1c8cb..c2cac11b 100644 --- a/examples/himbaechel/pll-nanolcd/TOP.v +++ b/examples/himbaechel/pll-nanolcd/TOP.v @@ -1,7 +1,7 @@ (* top *) module TOP ( - input rst, + input rst_i, input clk, output LCD_CLK, @@ -18,6 +18,7 @@ module TOP ); + wire rst = rst_i ^ `INV_BTN; wire CLK_SYS; wire CLK_PIX; diff --git a/examples/himbaechel/primer20k.cst b/examples/himbaechel/primer20k.cst index 7403afad..9f8358c5 100644 --- a/examples/himbaechel/primer20k.cst +++ b/examples/himbaechel/primer20k.cst @@ -1,6 +1,6 @@ IO_LOC "clk" IOT27A; -IO_LOC "key" T3; -IO_LOC "rst" T10; +IO_LOC "key_i" T3; +IO_LOC "rst_i" T10; IO_LOC "led[0]" C13; diff --git a/examples/himbaechel/runber.cst b/examples/himbaechel/runber.cst index 5770a2d9..d8d96110 100644 --- a/examples/himbaechel/runber.cst +++ b/examples/himbaechel/runber.cst @@ -1,6 +1,6 @@ IO_LOC "clk" 4; -IO_LOC "rst" 58; -IO_LOC "key" 59; +IO_LOC "rst_i" 58; +IO_LOC "key_i" 59; IO_LOC "led[0]" 25; IO_LOC "led[1]" 26; IO_LOC "led[2]" 23; diff --git a/examples/himbaechel/shift.v b/examples/himbaechel/shift.v index d81bd344..4552f76c 100644 --- a/examples/himbaechel/shift.v +++ b/examples/himbaechel/shift.v @@ -1,9 +1,10 @@ module top ( input clk, - input rst, + input rst_i, output [`LEDS_NR-1:0] led ); +wire rst = rst_i ^ `INV_BTN; wire rst_s; wire tick_hz; diff --git a/examples/himbaechel/szfpga.cst b/examples/himbaechel/szfpga.cst index 3d9dc27d..a55e3f9d 100644 --- a/examples/himbaechel/szfpga.cst +++ b/examples/himbaechel/szfpga.cst @@ -3,8 +3,8 @@ IO_LOC "clk" 98; -IO_LOC "rst" 27; // key0 -IO_LOC "key" 28; +IO_LOC "rst_i" 27; // key0 +IO_LOC "key_i" 28; IO_LOC "led[0]" 29; IO_LOC "led[1]" 30; diff --git a/examples/himbaechel/tangnano.cst b/examples/himbaechel/tangnano.cst index 92fddc82..fb1e4c11 100644 --- a/examples/himbaechel/tangnano.cst +++ b/examples/himbaechel/tangnano.cst @@ -4,8 +4,8 @@ IO_LOC "clk" 35; IO_LOC "led[0]" 16; IO_LOC "led[1]" 17; IO_LOC "led[2]" 18; -IO_LOC "key" 15; -IO_LOC "rst" 14; +IO_LOC "key_i" 15; +IO_LOC "rst_i" 14; // oser IO_LOC "oser_out" 16; diff --git a/examples/himbaechel/tangnano1k.cst b/examples/himbaechel/tangnano1k.cst index a23b9772..ec3263f3 100644 --- a/examples/himbaechel/tangnano1k.cst +++ b/examples/himbaechel/tangnano1k.cst @@ -6,10 +6,10 @@ IO_LOC "led[2]" 11; IO_PORT "led[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; -IO_LOC "rst" 13; -IO_PORT "rst" IO_TYPE=LVCMOS33 PULL_MODE=UP; -IO_LOC "key" 44; -IO_PORT "key" IO_TYPE=LVCMOS33 PULL_MODE=UP; +IO_LOC "rst_i" 13; +IO_PORT "rst_i" IO_TYPE=LVCMOS33 PULL_MODE=UP; +IO_LOC "key_i" 44; +IO_PORT "key_i" IO_TYPE=LVCMOS33 PULL_MODE=UP; IO_LOC "clk" 47; IO_PORT "clk" IO_TYPE=LVCMOS33; diff --git a/examples/himbaechel/tangnano20k.cst b/examples/himbaechel/tangnano20k.cst index 3992d521..d595987a 100644 --- a/examples/himbaechel/tangnano20k.cst +++ b/examples/himbaechel/tangnano20k.cst @@ -9,10 +9,10 @@ IO_LOC "led[3]" 18; IO_LOC "led[4]" 19; IO_LOC "led[5]" 20; -IO_LOC "key" 87; -IO_PORT "key" IO_TYPE=LVCMOS33; -IO_LOC "rst" 88; -IO_PORT "rst" IO_TYPE=LVCMOS33; +IO_LOC "key_i" 87; +IO_PORT "key_i" IO_TYPE=LVCMOS33; +IO_LOC "rst_i" 88; +IO_PORT "rst_i" IO_TYPE=LVCMOS33; IO_LOC "LED_R" 15; diff --git a/examples/himbaechel/tangnano20k/TOP.v b/examples/himbaechel/tangnano20k/TOP.v deleted file mode 100644 index 9f5db57b..00000000 --- a/examples/himbaechel/tangnano20k/TOP.v +++ /dev/null @@ -1,106 +0,0 @@ -(* top *) -module TOP -( - input rst, - input clk, - - output LCD_CLK, - output LCD_HYNC, - output LCD_SYNC, - output LCD_DEN, - output [4:0] LCD_R, - output [5:0] LCD_G, - output [4:0] LCD_B, - - output LED_R, - output LED_G, - output LED_B - -); - - wire CLK_SYS; - wire CLK_PIX; - -/* //使用内部时钟 - Gowin_OSC chip_osc( - .oscout(oscout_o) //output oscout - ); -*/ -rPLL pll( - .CLKOUT(CLK_PIX), // 9MHz - .CLKIN(clk), - .CLKFB(GND), - .RESET(GND), - .RESET_P(GND), - .FBDSEL({GND,GND,GND,GND,GND,GND}), - .IDSEL({GND,GND,GND,GND,GND,GND}), - .ODSEL({GND,GND,GND,GND,GND,GND}), - .DUTYDA({GND,GND,GND,GND}), - .PSDA({GND,GND,GND,GND}), - .FDLY({GND,GND,GND,GND}) - ); - defparam pll.DEVICE = `PLL_DEVICE; - defparam pll.FCLKIN = `PLL_FCLKIN; - defparam pll.FBDIV_SEL = `PLL_FBDIV_SEL_LCD; - defparam pll.IDIV_SEL = `PLL_IDIV_SEL_LCD; - defparam pll.ODIV_SEL = `PLL_ODIV_SEL; - defparam pll.CLKFB_SEL="internal"; - defparam pll.CLKOUTD3_SRC="CLKOUT"; - defparam pll.CLKOUTD_BYPASS="true"; - defparam pll.CLKOUTD_SRC="CLKOUT"; - defparam pll.CLKOUTP_BYPASS="false"; - defparam pll.CLKOUTP_DLY_STEP=0; - defparam pll.CLKOUTP_FT_DIR=1'b1; - defparam pll.CLKOUT_BYPASS="false"; - defparam pll.CLKOUT_DLY_STEP=0; - defparam pll.CLKOUT_FT_DIR=1'b1; - defparam pll.DUTYDA_SEL="1000"; - defparam pll.DYN_DA_EN="false"; - defparam pll.DYN_FBDIV_SEL="false"; - defparam pll.DYN_IDIV_SEL="false"; - defparam pll.DYN_ODIV_SEL="false"; - defparam pll.DYN_SDIV_SEL=1; // 9MHz --- pixel clock - defparam pll.PSDA_SEL="0000"; - - VGAMod D1 - ( - .CLK ( CLK_SYS ), - .nRST ( !rst ), - - .PixelClk ( CLK_PIX ), - .LCD_DE ( LCD_DEN ), - .LCD_HSYNC ( LCD_HYNC ), - .LCD_VSYNC ( LCD_SYNC ), - - .LCD_B ( LCD_B ), - .LCD_G ( LCD_G ), - .LCD_R ( LCD_R ) - ); - - assign LCD_CLK = CLK_PIX; - assign CLK_SYS = CLK_PIX; - - - //RGB LED TEST - reg [24:0] Count; - reg [1:0] rgb_data; - always @( posedge CLK_SYS or posedge rst ) - begin - if( rst ) - begin - Count <= 25'd0; - rgb_data <= 2'b00; - end - else if ( Count == 1200000 ) - begin - Count <= 4'b0; - rgb_data <= rgb_data + 1'b1; - end - else - Count <= Count + 1'b1; - end - assign LED_R = ~(rgb_data == 2'b01); - assign LED_G = ~(rgb_data == 2'b10); - assign LED_B = ~(rgb_data == 2'b11); - -endmodule diff --git a/examples/himbaechel/tangnano20k/attosoc.v b/examples/himbaechel/tangnano20k/attosoc.v deleted file mode 100644 index 9cbdc192..00000000 --- a/examples/himbaechel/tangnano20k/attosoc.v +++ /dev/null @@ -1,133 +0,0 @@ -/* - * ECP5 PicoRV32 demo - * - * Copyright (C) 2017 Clifford Wolf - * Copyright (C) 2018 David Shah - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -`ifdef PICORV32_V -`error "attosoc.v must be read before picorv32.v!" -`endif - -`define PICORV32_REGS picosoc_regs - -(* top *) -module attosoc ( - input clk, - output reg [7:0] led -); - - wire lock_o; - wire clkoutp_o; - wire clkoutd_o; - wire clkoutd3_o; - - reg [5:0] reset_cnt = 0; - wire resetn = &reset_cnt; - - always @(posedge clk) begin - reset_cnt <= reset_cnt + !resetn; - end - - parameter integer MEM_WORDS = 256; - parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory - parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // ROM at 0x0 - parameter integer ROM_BYTES = 256; - - reg [7:0] rom [0:ROM_BYTES-1]; - wire [31:0] rom_rdata = {rom[mem_addr+3], rom[mem_addr+2], rom[mem_addr+1], rom[mem_addr+0]}; - initial $readmemh("attosoc/firmware.hex", rom); - - wire mem_valid; - wire mem_instr; - wire mem_ready; - wire [31:0] mem_addr; - wire [31:0] mem_wdata; - wire [3:0] mem_wstrb; - wire [31:0] mem_rdata; - - wire rom_ready = mem_valid && mem_addr[31:24] == 8'h00; - - wire iomem_valid; - wire iomem_ready; - wire [31:0] iomem_addr; - wire [31:0] iomem_wdata; - wire [3:0] iomem_wstrb; - wire [31:0] iomem_rdata; - - assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01); - assign iomem_ready = 1'b1; - assign iomem_wstrb = mem_wstrb; - assign iomem_addr = mem_addr; - assign iomem_wdata = mem_wdata; - - wire [31:0] spimemio_cfgreg_do; - - - always @(posedge clk) - if (iomem_valid && iomem_wstrb[0]) - led <= iomem_wdata[7:0]; - - assign mem_ready = (iomem_valid && iomem_ready) || rom_ready; - - assign mem_rdata = rom_rdata; - - picorv32 #( - .STACKADDR(STACKADDR), - .PROGADDR_RESET(PROGADDR_RESET), - .PROGADDR_IRQ(32'h 0000_0000), - .BARREL_SHIFTER(0), - .COMPRESSED_ISA(0), - .ENABLE_MUL(0), - .ENABLE_DIV(0), - .ENABLE_IRQ(0), - .ENABLE_IRQ_QREGS(0) - ) cpu ( - .clk (clk ), - .resetn (resetn ), - .mem_valid (mem_valid ), - .mem_instr (mem_instr ), - .mem_ready (mem_ready ), - .mem_addr (mem_addr ), - .mem_wdata (mem_wdata ), - .mem_wstrb (mem_wstrb ), - .mem_rdata (mem_rdata ) - ); - - - -endmodule - -// Implementation note: -// Replace the following two modules with wrappers for your SRAM cells. - -module picosoc_regs ( - input clk, wen, - input [5:0] waddr, - input [5:0] raddr1, - input [5:0] raddr2, - input [31:0] wdata, - output [31:0] rdata1, - output [31:0] rdata2 -); - reg [31:0] regs [0:31]; - - always @(posedge clk) - if (wen) regs[waddr[4:0]] <= wdata; - - assign rdata1 = regs[raddr1[4:0]]; - assign rdata2 = regs[raddr2[4:0]]; -endmodule diff --git a/examples/himbaechel/tangnano20k/blinky-oddr.v b/examples/himbaechel/tangnano20k/blinky-oddr.v deleted file mode 100644 index cc10be89..00000000 --- a/examples/himbaechel/tangnano20k/blinky-oddr.v +++ /dev/null @@ -1,36 +0,0 @@ -/* -* led[0] is connected directly, led[1] --- via ODDR. This primitive needs 4 clock cycles to start working, so be patient:) -*/ -module top ( - input clk, - input key, - input rst, - output [`LEDS_NR-1:0] led -); - -reg [24:0] ctr_q; -wire [24:0] ctr_d; - -// Sequential code (flip-flop) -always @(posedge clk) begin - if (!rst) begin - ctr_q <= ctr_d; - end -end - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign led[`LEDS_NR-1:2] = {(`LEDS_NR - 2){1'b1}}; -assign led[0] = ctr_q[24:24]; - -ODDRC oddr_0( - .D0(1'b0), - .D1(1'b1), - .CLK(ctr_q[24:24]), - .Q0(led[1]), - .Q1(), - .TX(1'b1), - .CLEAR(key) -); - -endmodule diff --git a/examples/himbaechel/tangnano20k/blinky-osc.v b/examples/himbaechel/tangnano20k/blinky-osc.v deleted file mode 100644 index f434a445..00000000 --- a/examples/himbaechel/tangnano20k/blinky-osc.v +++ /dev/null @@ -1,44 +0,0 @@ -module top ( - input rst, - output [`LEDS_NR-1:0] led -); - -wire clk; - -`ifdef OSC_TYPE_OSC -OSC osc( - .OSCOUT(clk) -); -`elsif OSC_TYPE_OSCZ -OSCZ osc( - .OSCEN(1'b1), - .OSCOUT(clk) -); -`elsif OSC_TYPE_OSCF -OSCF osc( - .OSCEN(1'b1), - .OSCOUT(clk), - .OSCOUT30M() -); -`elsif OSC_TYPE_OSCH -OSCH osc( - .OSCOUT(clk) -); -`endif -defparam osc.FREQ_DIV=16; - -reg [25:0] ctr_q; -wire [25:0] ctr_d; - -// Sequential code (flip-flop) -always @(posedge clk) begin - if (!rst) begin - ctr_q <= ctr_d; - end -end - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign led = ctr_q[25:25-(`LEDS_NR - 1)]; - -endmodule diff --git a/examples/himbaechel/tangnano20k/blinky-tbuf.v b/examples/himbaechel/tangnano20k/blinky-tbuf.v deleted file mode 100644 index 136e1f3f..00000000 --- a/examples/himbaechel/tangnano20k/blinky-tbuf.v +++ /dev/null @@ -1,25 +0,0 @@ -module top ( - input clk, - input key, - output [`LEDS_NR-1:0] led -); - -reg [25:0] ctr_q; -wire [25:0] ctr_d; - -// Sequential code (flip-flop) -always @(posedge clk) begin - ctr_q <= ctr_d; -end - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign led[`LEDS_NR - 1:1] = ctr_q[25:25-(`LEDS_NR - 2)]; - -TBUF tbuf( - .I(ctr_q[25 - (`LEDS_NR - 1)]), - .O(led[0]), - .OEN(key) -); - -endmodule diff --git a/examples/himbaechel/tangnano20k/blinky.v b/examples/himbaechel/tangnano20k/blinky.v deleted file mode 100644 index c8b0699b..00000000 --- a/examples/himbaechel/tangnano20k/blinky.v +++ /dev/null @@ -1,21 +0,0 @@ -module top ( - input clk, - input key, - output [`LEDS_NR-1:0] led -); - -reg [25:0] ctr_q; -wire [25:0] ctr_d; - -// Sequential code (flip-flop) -always @(posedge clk) begin - if (!key) begin - ctr_q <= ctr_d; - end -end - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign led = ctr_q[25:25-(`LEDS_NR - 1)]; - -endmodule diff --git a/examples/himbaechel/tangnano20k/elvds.v b/examples/himbaechel/tangnano20k/elvds.v deleted file mode 100644 index 7fd20470..00000000 --- a/examples/himbaechel/tangnano20k/elvds.v +++ /dev/null @@ -1,31 +0,0 @@ -/* Using an oscilloscope you can see on pins tlvds_p and tlvds_n the signal with changing polarity. -* You can also use a 100 Ohm resistor and two LEDs connected in opposite directions between these pins. -*/ -module top ( - input clk, - output elvds_p, - output elvds_n, - input key -); - -reg [24:0] ctr_q; -wire [24:0] ctr_d; -wire i_tick; - -// Sequential code (flip-flop) -always @(posedge clk) - ctr_q <= ctr_d; - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign i_tick = |ctr_q[24:23]; - -ELVDS_TBUF diff_buf( - .OEN(key), - .O(elvds_p), - .OB(elvds_n), - .I(i_tick) - ); - -endmodule - diff --git a/examples/himbaechel/tangnano20k/ides10.v b/examples/himbaechel/tangnano20k/ides10.v deleted file mode 100644 index 70cd4ff8..00000000 --- a/examples/himbaechel/tangnano20k/ides10.v +++ /dev/null @@ -1,52 +0,0 @@ -`default_nettype none -module top(input wire clk, - input wire rst, - input wire fclk_i, - input wire data_i, - output wire pclk_o, - output wire [7:0]q_o); - - wire dummy[1:0]; - - IDES10 ides( - .D(data_i), - .FCLK(fclk_i), - .PCLK(pclk_o), - .CALIB(1'b0), - .RESET(rst), - .Q0(q_o[0]), - .Q1(q_o[1]), - .Q2(q_o[2]), - .Q3(q_o[3]), - .Q4(q_o[4]), - .Q5(q_o[5]), - .Q6(q_o[6]), - .Q7(q_o[7]), - .Q8(dummy[0]), - .Q9(dummy[1]) - ); - defparam ides.GSREN="false"; - defparam ides.LSREN="true"; - - // div by 5 - reg [2:0] count; - wire clkA; - reg clkB; - always @(posedge fclk_i) begin - if (rst) begin - count <= 0; - end else begin - if (count == 3'd4) begin - count <= 0; - end else begin - count <= count+1; - end - end - end - assign clkA = count[1]; - - always@(negedge fclk_i) begin - clkB <= clkA; - end - assign pclk_o = clkA | clkB; -endmodule diff --git a/examples/himbaechel/tangnano20k/ides4.v b/examples/himbaechel/tangnano20k/ides4.v deleted file mode 100644 index 6128eeef..00000000 --- a/examples/himbaechel/tangnano20k/ides4.v +++ /dev/null @@ -1,29 +0,0 @@ -`default_nettype none -module top(input wire clk, - input wire rst, - input wire fclk_i, - input wire data_i, - output wire pclk_o, - output wire [7:0]q_o); - - IDES4 ides( - .D(data_i), - .FCLK(fclk_i), - .PCLK(pclk_o), - .CALIB(1'b0), - .RESET(rst), - .Q0(q_o[0]), - .Q1(q_o[1]), - .Q2(q_o[2]), - .Q3(q_o[3]) - ); - defparam ides.GSREN="false"; - defparam ides.LSREN="true"; - - reg pclk_r; - always @(posedge fclk_i) begin - pclk_r <= !pclk_r; - end - assign pclk_o = pclk_r; - -endmodule diff --git a/examples/himbaechel/tangnano20k/ides8.v b/examples/himbaechel/tangnano20k/ides8.v deleted file mode 100644 index 284a013c..00000000 --- a/examples/himbaechel/tangnano20k/ides8.v +++ /dev/null @@ -1,38 +0,0 @@ -`default_nettype none -module top(input wire clk, - input wire rst, - input wire fclk_i, - input wire data_i, - output wire pclk_o, - output wire [7:0]q_o); - - IDES8 ides( - .D(data_i), - .FCLK(fclk_i), - .PCLK(pclk_o), - .CALIB(1'b0), - .RESET(rst), - .Q0(q_o[0]), - .Q1(q_o[1]), - .Q2(q_o[2]), - .Q3(q_o[3]), - .Q4(q_o[4]), - .Q5(q_o[5]), - .Q6(q_o[6]), - .Q7(q_o[7]), - ); - defparam ides.GSREN="false"; - defparam ides.LSREN="true"; - - reg [1:0]pclk_r; - - always @(posedge fclk_i) begin - if (rst) begin - pclk_r <= 2'b00; - end else begin - pclk_r <= pclk_r + 2'b01; - end - end - assign pclk_o = pclk_r[1]; - -endmodule diff --git a/examples/himbaechel/tangnano20k/ivideo.v b/examples/himbaechel/tangnano20k/ivideo.v deleted file mode 100644 index fb1f4aef..00000000 --- a/examples/himbaechel/tangnano20k/ivideo.v +++ /dev/null @@ -1,51 +0,0 @@ -`default_nettype none -module top(input wire clk, - input wire rst, - input wire fclk_i, - input wire data_i, - output wire pclk_o, - output wire [7:0]q_o); - - IVIDEO ides( - .D(data_i), - .FCLK(fclk_i), - .PCLK(pclk_o), - .CALIB(1'b0), - .RESET(rst), - .Q0(q_o[0]), - .Q1(q_o[1]), - .Q2(q_o[2]), - .Q3(q_o[3]), - .Q4(q_o[4]), - .Q5(q_o[5]), - .Q6(q_o[6]) - ); - defparam ides.GSREN="false"; - defparam ides.LSREN="true"; - - // div by 3.5 - reg [6:0]cnt_r; - reg ps0_r; - reg ps3_r; - reg ps4_r; - always @(posedge fclk_i) begin - if (rst) begin - cnt_r[6:0] <= 7'b000_0001; - end else begin - cnt_r[6:0] <= {cnt_r[5:0], cnt_r[6]}; - end - end - - always @(negedge fclk_i) begin - if (rst) begin - ps0_r <= 1'b0; - ps3_r <= 1'b0; - ps4_r <= 1'b0; - end else begin - ps0_r <= cnt_r[0]; - ps3_r <= cnt_r[3]; - ps4_r <= cnt_r[4]; - end - end - assign pclk_o = (ps0_r | cnt_r[0] | cnt_r[1]) | (ps3_r | ps4_r | cnt_r[4]); -endmodule diff --git a/examples/himbaechel/tangnano20k/oddr-elvds.v b/examples/himbaechel/tangnano20k/oddr-elvds.v deleted file mode 100644 index 91e49a0f..00000000 --- a/examples/himbaechel/tangnano20k/oddr-elvds.v +++ /dev/null @@ -1,43 +0,0 @@ -/* Using an oscilloscope you can see on pins tlvds_p and tlvds_n the signal with changing polarity. -* You can also use a 100 Ohm resistor and two LEDs connected in opposite directions between these pins. -* ODDR needs 4 clock cycles to start working, so be patient:) -*/ -module top ( - input clk, - input key, - output elvds_p, - output elvds_n -); - -reg [24:0] ctr_q; -wire [24:0] ctr_d; -wire i_tick; -wire w_ddr; -wire oen; - -// Sequential code (flip-flop) -always @(posedge clk) - ctr_q <= ctr_d; - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign i_tick = |ctr_q[24:23]; - -ODDR oddr_0( - .D0(1'b0), - .D1(1'b1), - .CLK(i_tick), - .Q0(w_ddr), - .Q1(oen), - .TX(key) -); - -ELVDS_TBUF diff_buf( - .OEN(oen), - .O(elvds_p), - .OB(elvds_n), - .I(w_ddr) - ); - -endmodule - diff --git a/examples/himbaechel/tangnano20k/oddr-tlvds.v b/examples/himbaechel/tangnano20k/oddr-tlvds.v deleted file mode 100644 index 488ad76d..00000000 --- a/examples/himbaechel/tangnano20k/oddr-tlvds.v +++ /dev/null @@ -1,44 +0,0 @@ -/* Using an oscilloscope you can see on pins tlvds_p and tlvds_n the signal with changing polarity. -* You can also use a 100 Ohm resistor and two LEDs connected in opposite directions between these pins. -* ODDR needs 4 clock cycles to start working, so be patient:) -*/ -module top ( - input clk, - input key, - output tlvds_p, - output tlvds_n -); - -reg [24:0] ctr_q; -wire [24:0] ctr_d; -wire i_tick; -wire w_ddr; - -// Sequential code (flip-flop) -always @(posedge clk) - ctr_q <= ctr_d; - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign i_tick = |ctr_q[24:23]; - -wire w_oen; - -ODDR oddr_0( - .D0(1'b0), - .D1(1'b1), - .CLK(i_tick), - .Q0(w_ddr), - .Q1(w_oen), - .TX(key) -); - -TLVDS_TBUF diff_buf( - .OEN(w_oen), - .O(tlvds_p), - .OB(tlvds_n), - .I(w_ddr) - ); - -endmodule - diff --git a/examples/himbaechel/tangnano20k/oser10.v b/examples/himbaechel/tangnano20k/oser10.v deleted file mode 100644 index 41039d01..00000000 --- a/examples/himbaechel/tangnano20k/oser10.v +++ /dev/null @@ -1,74 +0,0 @@ -`default_nettype none -/* -* This example allows you to generate several OSER10 primitives and then check -* them with a logic analyzer. The PCLK, FCLK and Q outputs of the primitives -* are connected to the board pins. -*/ -module top(input wire clk, - input wire rst, - output wire oser_out, - output wire pclk_o, - output wire fclk_o); - - OSER10 os( - .D0(1'b0), - .D1(1'b1), - .D2(1'b0), - .D3(1'b1), - .D4(1'b0), - .D5(1'b1), - .D6(1'b0), - .D7(1'b1), - .D8(1'b0), - .D9(1'b1), - .FCLK(fclk_w), - .PCLK(pclk_w), - .RESET(1'b0), - .Q(oser_out) - ); - defparam os.GSREN = "false"; - defparam os.LSREN = "true"; - - wire clk_w; - wire pclk_w; - wire fclk_w; - - assign pclk_o = pclk_w; - assign fclk_o = fclk_w; - - reg [2:0] count; - wire clkA; - reg clkB; - always @(posedge fclk_w) begin - if (rst) begin - count <= 0; - end else begin - if (count == 3'd4) begin - count <= 0; - end else begin - count <= count+1; - end - end - end - assign clkA = count[1]; - - always@(negedge fclk_w) begin - clkB <= clkA; - end - assign pclk_w = clkA | clkB; - - // slow - reg [24:0] ctr_q; - wire [24:0] ctr_d; - wire tick_w; - - // Sequential code (flip-flop) - always @(posedge clk) - ctr_q <= ctr_d; - - // Combinational code (boolean logic) - assign ctr_d = ctr_q + 1'b1; - assign tick_w = ctr_q[24]; - - assign fclk_w = tick_w; -endmodule diff --git a/examples/himbaechel/tangnano20k/oser4.v b/examples/himbaechel/tangnano20k/oser4.v deleted file mode 100644 index a4038488..00000000 --- a/examples/himbaechel/tangnano20k/oser4.v +++ /dev/null @@ -1,57 +0,0 @@ -`default_nettype none -/* -* This example allows you to generate several OSER10 primitives and then check -* them with a logic analyzer. The PCLK, FCLK and Q outputs of the primitives -* are connected to the board pins. -*/ -module top(input wire clk, - input wire rst, - output wire oser_out, - output wire pclk_o, - output wire fclk_o); - - OSER4 os( - .D0(1'b0), - .D1(1'b1), - .D2(1'b0), - .D3(1'b1), - .TX0(1'b1), - .TX1(1'b1), - .FCLK(fclk_w), - .PCLK(pclk_w), - .RESET(1'b0), - .Q0(oser_out), - .Q1() - ); - defparam os.GSREN = "false"; - defparam os.LSREN = "true"; - - wire clk_w; - wire pclk_w; - wire fclk_w; - - assign pclk_o = pclk_w; - assign fclk_o = fclk_w; - - reg clkB; - - always@(negedge fclk_w) begin - clkB <= ~clkB; - end - assign pclk_w = clkB; - - // slow - reg [24:0] ctr_q; - wire [24:0] ctr_d; - wire tick_w; - - // Sequential code (flip-flop) - always @(posedge clk) - ctr_q <= ctr_d; - - // Combinational code (boolean logic) - assign ctr_d = ctr_q + 1'b1; - assign tick_w = ctr_q[24]; - - assign fclk_w = tick_w; -endmodule diff --git a/examples/himbaechel/tangnano20k/oser8.v b/examples/himbaechel/tangnano20k/oser8.v deleted file mode 100644 index 1d829976..00000000 --- a/examples/himbaechel/tangnano20k/oser8.v +++ /dev/null @@ -1,63 +0,0 @@ -`default_nettype none -/* -* This example allows you to generate several OSER10 primitives and then check -* them with a logic analyzer. The PCLK, FCLK and Q outputs of the primitives -* are connected to the board pins. -*/ -module top(input wire clk, - input wire rst, - output wire oser_out, - output wire pclk_o, - output wire fclk_o); - - OSER8 os( - .D0(1'b0), - .D1(1'b1), - .D2(1'b0), - .D3(1'b1), - .D4(1'b0), - .D5(1'b1), - .D6(1'b0), - .D7(1'b1), - .TX0(1'b1), - .TX1(1'b1), - .TX2(1'b1), - .TX3(1'b1), - .FCLK(fclk_w), - .PCLK(pclk_r[1]), - .RESET(1'b0), - .Q0(oser_out) - ); - defparam os.GSREN = "false"; - defparam os.LSREN = "true"; - defparam os.TXCLK_POL = 0; - defparam os.HWL = "false"; - - reg [1:0]pclk_r; - wire fclk_w; - - always @(posedge fclk_w) begin - if (rst) begin - pclk_r <= 2'b00; - end else begin - pclk_r <= pclk_r + 2'b01; - end - end - assign pclk_o = pclk_r[1]; - assign fclk_o = fclk_w; - - // slow - reg [24:0] ctr_q; - wire [24:0] ctr_d; - wire tick_w; - - // Sequential code (flip-flop) - always @(posedge clk) - ctr_q <= ctr_d; - - // Combinational code (boolean logic) - assign ctr_d = ctr_q + 1'b1; - assign tick_w = ctr_q[24]; - - assign fclk_w = tick_w; -endmodule diff --git a/examples/himbaechel/tangnano20k/ovideo.v b/examples/himbaechel/tangnano20k/ovideo.v deleted file mode 100644 index 966a2837..00000000 --- a/examples/himbaechel/tangnano20k/ovideo.v +++ /dev/null @@ -1,76 +0,0 @@ -`default_nettype none -/* -* This example allows you to generate several OSER10 primitives and then check -* them with a logic analyzer. The PCLK, FCLK and Q outputs of the primitives -* are connected to the board pins. -*/ -module top(input wire clk, - input wire rst, - output wire oser_out, - output wire pclk_o, - output wire fclk_o); - - OVIDEO os( - .D0(1'b1), - .D1(1'b0), - .D2(1'b1), - .D3(1'b0), - .D4(1'b1), - .D5(1'b0), - .D6(1'b1), - .FCLK(fclk_w), - .PCLK(pclk_w), - .RESET(1'b0), - .Q(oser_out) - ); - defparam os.GSREN = "false"; - defparam os.LSREN = "true"; - - wire clk_w; - wire pclk_w; - wire fclk_w; - - assign pclk_o = pclk_w; - assign fclk_o = fclk_w; - - // div by 3.5 - reg [6:0]cnt_r; - reg ps0_r; - reg ps3_r; - reg ps4_r; - always @(posedge fclk_w) begin - if (rst) begin - cnt_r[6:0] <= 7'b000_0001; - end else begin - cnt_r[6:0] <= {cnt_r[5:0], cnt_r[6]}; - end - end - - always @(negedge fclk_w) begin - if (rst) begin - ps0_r <= 1'b0; - ps3_r <= 1'b0; - ps4_r <= 1'b0; - end else begin - ps0_r <= cnt_r[0]; - ps3_r <= cnt_r[3]; - ps4_r <= cnt_r[4]; - end - end - assign pclk_w = (ps0_r | cnt_r[0] | cnt_r[1]) | (ps3_r | ps4_r | cnt_r[4]); - - // slow - reg [24:0] ctr_q; - wire [24:0] ctr_d; - wire tick_w; - - // Sequential code (flip-flop) - always @(posedge clk) - ctr_q <= ctr_d; - - // Combinational code (boolean logic) - assign ctr_d = ctr_q + 1'b1; - assign tick_w = ctr_q[24]; - - assign fclk_w = tick_w; -endmodule diff --git a/examples/himbaechel/tangnano20k/shift.v b/examples/himbaechel/tangnano20k/shift.v deleted file mode 100644 index a33f3b1f..00000000 --- a/examples/himbaechel/tangnano20k/shift.v +++ /dev/null @@ -1,44 +0,0 @@ -module top ( - input clk, - input rst, - output [`LEDS_NR-1:0] led -); - -wire rst_s; -wire tick_hz; - -localparam HZ_PRESC = 12_000_000, - HZ_SIZE = $clog2(HZ_PRESC); - -reg [HZ_SIZE-1:0] hertz_cpt; -wire [HZ_SIZE-1:0] hertz_cpt_d = hertz_cpt - 1'b1; - -always @(posedge clk) begin - /* 1Hz clk */ - if (tick_hz) begin - hertz_cpt <= HZ_PRESC; - end else begin - hertz_cpt <= hertz_cpt_d; - end -end - - -reg [`LEDS_NR-1:0] ctr_q; -wire [`LEDS_NR-1:0] ctr_d; - -// Sequential code (flip-flop) -always @(posedge clk or posedge rst_s) begin - if (rst_s) begin - ctr_q <= 'd1; - end else if (tick_hz) begin - ctr_q <= ctr_d; - end -end - -// Combinational code (boolean logic) -assign ctr_d = {ctr_q[0], ctr_q[`LEDS_NR-1:1]}; -assign led = ctr_q; -assign tick_hz = (hertz_cpt == 0); -assign rst_s = rst; - -endmodule diff --git a/examples/himbaechel/tangnano20k/tlvds.v b/examples/himbaechel/tangnano20k/tlvds.v deleted file mode 100644 index 8b8656f2..00000000 --- a/examples/himbaechel/tangnano20k/tlvds.v +++ /dev/null @@ -1,31 +0,0 @@ -/* Using an oscilloscope you can see on pins tlvds_p and tlvds_n the signal with changing polarity. -* You can also use a 100 Ohm resistor and two LEDs connected in opposite directions between these pins. -*/ -module top ( - input clk, - output tlvds_p, - output tlvds_n, - input key -); - -reg [24:0] ctr_q; -wire [24:0] ctr_d; -wire i_tick; - -// Sequential code (flip-flop) -always @(posedge clk) - ctr_q <= ctr_d; - -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign i_tick = |ctr_q[24:23]; - -TLVDS_TBUF diff_buf( - .OEN(key), - .O(tlvds_p), - .OB(tlvds_n), - .I(i_tick) - ); - -endmodule - diff --git a/examples/himbaechel/tangnano4k.cst b/examples/himbaechel/tangnano4k.cst index 1ba4aac7..26e53f63 100644 --- a/examples/himbaechel/tangnano4k.cst +++ b/examples/himbaechel/tangnano4k.cst @@ -5,8 +5,8 @@ IO_LOC "led[2]" 29; IO_LOC "led[3]" 30; IO_LOC "led[4]" 31; IO_LOC "led[5]" 32; -IO_LOC "key" 15; -IO_LOC "rst" 14; +IO_LOC "key_i" 15; +IO_LOC "rst_i" 14; IO_LOC "clk" 45; // oser diff --git a/examples/himbaechel/tangnano9k.cst b/examples/himbaechel/tangnano9k.cst index ccb078b8..a31e2270 100644 --- a/examples/himbaechel/tangnano9k.cst +++ b/examples/himbaechel/tangnano9k.cst @@ -7,8 +7,8 @@ IO_LOC "led[2]" 13; IO_LOC "led[3]" 14; IO_LOC "led[4]" 15; IO_LOC "led[5]" 16; -IO_LOC "key" 3; -IO_LOC "rst" 4; +IO_LOC "key_i" 3; +IO_LOC "rst_i" 4; IO_LOC "LED_R" 10; IO_LOC "LED_G" 11; diff --git a/examples/himbaechel/tec0117.cst b/examples/himbaechel/tec0117.cst index e9789e9e..2ef57d1a 100644 --- a/examples/himbaechel/tec0117.cst +++ b/examples/himbaechel/tec0117.cst @@ -7,8 +7,8 @@ IO_LOC "clk" 35; IO_PORT "clk" IO_TYPE=LVCMOS33; -IO_LOC "rst" 77; -IO_LOC "key" 68; +IO_LOC "rst_i" 77; +IO_LOC "key_i" 68; IO_LOC "sd_out" 47; // PMOD header pin 1 IO_PORT "sd_out" IO_TYPE=LVCMOS33; IO_LOC "led[0]" 86; diff --git a/examples/himbaechel/tlvds.v b/examples/himbaechel/tlvds.v index e709ecc7..072b5a40 100644 --- a/examples/himbaechel/tlvds.v +++ b/examples/himbaechel/tlvds.v @@ -5,9 +5,10 @@ module top ( input clk, output tlvds_p, output tlvds_n, - input key + input key_i ); +wire key = key_i ^ `INV_BTN; reg [24:0] ctr_q; wire [24:0] ctr_d; wire i_tick; From ddd6aba68d8f378414e98f6d6fafe6de1fbd7211 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Fri, 8 Sep 2023 20:12:15 +1000 Subject: [PATCH 4/6] Cheat CI Set another Python version Signed-off-by: YRabbit --- .github/workflows/chipdb.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/chipdb.yml b/.github/workflows/chipdb.yml index 717af6cc..5188676c 100644 --- a/.github/workflows/chipdb.yml +++ b/.github/workflows/chipdb.yml @@ -301,7 +301,7 @@ jobs: sudo make install cd ../nextpnr git checkout ${{ matrix.nextpnr }} - cmake . -DBUILD_PYTHON=OFF -DARCH="gowin;himbaechel" -DHIMBAECHEL_GOWIN_DEVICES="GW1N-1;GW1NZ-1;GW1N-4;GW1N-9;GW1N-9C;GW1NS-4;GW2A-18;GW2A-18C" -DPython3_EXECUTABLE=/opt/hostedtoolcache/Python/3.9.17/x64/bin/python + cmake . -DBUILD_PYTHON=OFF -DARCH="gowin;himbaechel" -DHIMBAECHEL_GOWIN_DEVICES="GW1N-1;GW1NZ-1;GW1N-4;GW1N-9;GW1N-9C;GW1NS-4;GW2A-18;GW2A-18C" -DPython3_EXECUTABLE=/opt/hostedtoolcache/Python/3.9.18/x64/bin/python make -j$(nproc) sudo make install cd ../examples From 084408a805aa9eff4836d1414f9d7b1b78f5764c Mon Sep 17 00:00:00 2001 From: YRabbit Date: Sat, 16 Sep 2023 18:44:42 +1000 Subject: [PATCH 5/6] Himbaechel. Use the new nextpnr UI Signed-off-by: YRabbit --- examples/himbaechel/Makefile.himbaechel | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/examples/himbaechel/Makefile.himbaechel b/examples/himbaechel/Makefile.himbaechel index 06930bda..de3493d5 100644 --- a/examples/himbaechel/Makefile.himbaechel +++ b/examples/himbaechel/Makefile.himbaechel @@ -1,7 +1,6 @@ YOSYS ?= yosys -NEXTPNR ?= nextpnr-himbaechel --uarch gowin +NEXTPNR ?= nextpnr-himbaechel -CHIPDB_PATH ?= /usr/local/share/nextpnr/himbaechel/gowin HIMBAECHEL_OUT ?= ./himbaechel-out .DEFAULT_GOAL := all @@ -144,7 +143,7 @@ clean: gowin_pack -d GW2A-18C -o $@ $< %-tangnano20k.json: %-tangnano20k-synth.json tangnano20k.cst - $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW2A-18C.bin --vopt partno=GW2AR-LV18QN88C8/I7 --vopt cst=tangnano20k.cst + $(NEXTPNR) --json $< --write $@ --device GW2AR-LV18QN88C8/I7 --vopt family=GW2A-18C --vopt cst=tangnano20k.cst %-tangnano20k-synth.json: %.v $(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -D INV_BTN=1 -p "read_verilog $^; synth_gowin -json $@" @@ -161,7 +160,7 @@ attosoc-tangnano20k-synth.json: attosoc/attosoc.v attosoc/picorv32.v gowin_pack -d GW2A-18 -o $@ $< %-primer20k.json: %-primer20k-synth.json primer20k.cst - $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW2A-18.bin --vopt partno=GW2A-LV18PG256C8/I7 --vopt cst=primer20k.cst + $(NEXTPNR) --json $< --write $@ --device GW2A-LV18PG256C8/I7 --vopt family=GW2A-18 --vopt cst=primer20k.cst %-primer20k-synth.json: %.v $(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" @@ -178,7 +177,7 @@ attosoc-%-synth.json: attosoc/attosoc.v attosoc/picorv32.v gowin_pack -d GW1N-1 -o $@ $^ %-tangnano.json: %-tangnano-synth.json tangnano.cst - $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-1.bin --vopt partno=GW1N-LV1QN48C6/I5 --vopt cst=tangnano.cst + $(NEXTPNR) --json $< --write $@ --device GW1N-LV1QN48C6/I5 --vopt cst=tangnano.cst %-tangnano-synth.json: %.v $(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCH -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" @@ -192,7 +191,7 @@ pll-nanolcd-tangnano-synth.json: pll/GW1N-1-dyn.vh pll-nanolcd/TOP.v pll-nanolcd gowin_pack -d GW1NZ-1 -o $@ $^ %-tangnano1k.json: %-tangnano1k-synth.json tangnano1k.cst - $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1NZ-1.bin --vopt partno=GW1NZ-LV1QN48C6/I5 --vopt cst=tangnano1k.cst + $(NEXTPNR) --json $< --write $@ --device GW1NZ-LV1QN48C6/I5 --vopt cst=tangnano1k.cst %-tangnano1k-synth.json: %.v $(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCZ -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" @@ -209,7 +208,7 @@ pll-nanolcd-tangnano1k-synth.json: pll/GW1NZ-1-dyn.vh pll-nanolcd/TOP.v pll-nano gowin_pack -d GW1NS-4 -o $@ $^ %-tangnano4k.json: %-tangnano4k-synth.json tangnano4k.cst - $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1NS-4.bin --vopt partno=GW1NSR-LV4CQN48PC7/I6 --vopt cst=tangnano4k.cst + $(NEXTPNR) --json $< --write $@ --device GW1NSR-LV4CQN48PC7/I6 --vopt cst=tangnano4k.cst %-tangnano4k-synth.json: %.v $(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSCZ -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" @@ -223,7 +222,7 @@ blinky-pll-tangnano4k-synth.json: pll/GW1NS-4-dyn.vh blinky-pll-vr.v gowin_pack -d GW1N-9C -o $@ $^ %-tangnano9k.json: %-tangnano9k-synth.json tangnano9k.cst - $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-9C.bin --vopt partno=GW1NR-LV9QN88PC6/I5 --vopt cst=tangnano9k.cst + $(NEXTPNR) --json $< --write $@ --device GW1NR-LV9QN88PC6/I5 --vopt family=GW1N-9C --vopt cst=tangnano9k.cst %-tangnano9k-synth.json: %.v $(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" @@ -240,7 +239,7 @@ pll-nanolcd-tangnano9k.fs: pll-nanolcd-tangnano9k.json gowin_pack -d GW1N-9 -o $@ $< %-szfpga.json: %-szfpga-synth.json szfpga.cst - $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-9.bin --vopt partno=GW1NR-LV9LQ144PC6/I5 --vopt cst=szfpga.cst + $(NEXTPNR) --json $< --write $@ --device GW1NR-LV9LQ144PC6/I5 --vopt family=GW1N-9 --vopt cst=szfpga.cst %-szfpga-synth.json: %.v $(YOSYS) -D LEDS_NR=4 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" @@ -254,7 +253,7 @@ blinky-pll-szfpga-synth.json: pll/GW1N-9-dyn.vh blinky-pll.v gowin_pack -d GW1N-9 -o $@ $< %-tec0117.json: %-tec0117-synth.json tec0117.cst - $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-9.bin --vopt partno=GW1NR-LV9QN88C6/I5 --vopt cst=tec0117.cst + $(NEXTPNR) --json $< --write $@ --device GW1NR-LV9QN88C6/I5 --vopt family=GW1N-9 --vopt cst=tec0117.cst %-tec0117-synth.json: %.v $(YOSYS) -D LEDS_NR=8 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" @@ -268,7 +267,7 @@ blinky-pll-tec0117-synth.json: pll/GW1N-9-dyn.vh blinky-pll.v gowin_pack -d GW1N-4 -o $@ $< %-runber.json: %-runber-synth.json runber.cst - $(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-4.bin --vopt partno=GW1N-UV4LQ144C6/I5 --vopt cst=runber.cst + $(NEXTPNR) --json $< --write $@ --device GW1N-UV4LQ144C6/I5 --vopt cst=runber.cst %-runber-synth.json: %.v $(YOSYS) -D LEDS_NR=8 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@" From 984885f50fe8ce20f6ec83473f9572068553b5f9 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Sun, 17 Sep 2023 20:38:41 +0200 Subject: [PATCH 6/6] Try to get path from setup_python --- .github/workflows/chipdb.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/chipdb.yml b/.github/workflows/chipdb.yml index 5188676c..93b75e81 100644 --- a/.github/workflows/chipdb.yml +++ b/.github/workflows/chipdb.yml @@ -279,6 +279,7 @@ jobs: path: dist - name: Set up Python uses: actions/setup-python@v4 + id: pysetup with: python-version: '3.9' - name: Install and build @@ -301,7 +302,7 @@ jobs: sudo make install cd ../nextpnr git checkout ${{ matrix.nextpnr }} - cmake . -DBUILD_PYTHON=OFF -DARCH="gowin;himbaechel" -DHIMBAECHEL_GOWIN_DEVICES="GW1N-1;GW1NZ-1;GW1N-4;GW1N-9;GW1N-9C;GW1NS-4;GW2A-18;GW2A-18C" -DPython3_EXECUTABLE=/opt/hostedtoolcache/Python/3.9.18/x64/bin/python + cmake . -DBUILD_PYTHON=OFF -DARCH="gowin;himbaechel" -DHIMBAECHEL_GOWIN_DEVICES="GW1N-1;GW1NZ-1;GW1N-4;GW1N-9;GW1N-9C;GW1NS-4;GW2A-18;GW2A-18C" -DPython3_EXECUTABLE=${{ steps.pysetup.outputs.python-path }} make -j$(nproc) sudo make install cd ../examples