diff --git a/apycula/gowin_unpack.py b/apycula/gowin_unpack.py
index 1f59298a..60db8650 100644
--- a/apycula/gowin_unpack.py
+++ b/apycula/gowin_unpack.py
@@ -307,7 +307,7 @@ def get_bsram_main_cell(db, row, col, typ):
     if typ[-4:] == '_AUX':
         col -= 1
         if 'BSRAM_AUX' in db.grid[row][col].bels:
-            col -= 2
+            col -= 1
     return row, col
 
 # The DSP has 9 cells: the main one and a group of auxiliary ones.
@@ -372,7 +372,7 @@ def parse_tile_(db, row, col, tile, default=True, noalias=False, noiostd = True)
             if not attrvals:
                 continue
             #print(row, col, name, idx, tiledata.ttyp, attrvals)
-            bels[f'{name}'] = {}
+            bels[f'{name}{idx}'] = {}
             continue
         if name.startswith("ALU54D"):
             continue
@@ -942,12 +942,16 @@ def tile2verilog(dbrow, dbcol, bels, pips, clock_pips, mod, cst, db):
             for port, wname in portmap.items():
                 pll.portmap[port] = f"R{row}C{col}_{wname}"
         elif typ.startswith("BSRAM"):
+            #print(dbrow, dbcol, typ, bel, idx)
+            if idx.startswith("_AUX"):
+                continue
+            bel_name = "BSRAM"
             name = f"BSRAM_{idx}"
             pll = mod.primitives.setdefault(name, codegen.Primitive("BSRAM", name))
             for paramval in flags:
                 param, _, val = paramval.partition('=')
                 pll.params[param] = val
-            portmap = db.grid[dbrow][dbcol].bels[bel].portmap
+            portmap = db.grid[dbrow][dbcol].bels[bel_name].portmap
             for port, wname in portmap.items():
                 pll.portmap[port] = f"R{row}C{col}_{wname}"
         elif typ == "ALU":
diff --git a/examples/himbaechel/Makefile.himbaechel b/examples/himbaechel/Makefile.himbaechel
index 61143ba0..fb44e95a 100644
--- a/examples/himbaechel/Makefile.himbaechel
+++ b/examples/himbaechel/Makefile.himbaechel
@@ -119,6 +119,7 @@ unpacked:\
 	bsram-DPB-tangnano20k-unpacked.v bsram-pROMX9-tangnano20k-unpacked.v \
 	bsram-SDPX9B-tangnano20k-unpacked.v bsram-SPX9-tangnano-unpacked.v \
 	bsram-DPX9B-tangnano20k-unpacked.v \
+	femto-riscv-15-tangnano20k-unpacked.v femto-riscv-16-tangnano20k-unpacked.v femto-riscv-18-tangnano20k-unpacked.v \
 	\
 	blinky-primer20k-unpacked.v shift-primer20k-unpacked.v blinky-tbuf-primer20k-unpacked.v \
 	blinky-oddr-primer20k-unpacked.v blinky-osc-primer20k-unpacked.v tlvds-primer20k-unpacked.v \
@@ -131,6 +132,7 @@ unpacked:\
 	bsram-DPB-primer20k-unpacked.v bsram-pROMX9-primer20k-unpacked.v \
 	bsram-SDPX9B-primer20k-unpacked.v bsram-SPX9-tangnano-unpacked.v \
 	bsram-DPX9B-primer20k-unpacked.v \
+	femto-riscv-15-primer20k-unpacked.v femto-riscv-16-primer20k-unpacked.v femto-riscv-18-primer20k-unpacked.v \
 	\
 	blinky-tangnano-unpacked.v shift-tangnano-unpacked.v blinky-tbuf-tangnano-unpacked.v \
 	blinky-oddr-tangnano-unpacked.v blinky-osc-tangnano-unpacked.v elvds-tangnano-unpacked.v \
@@ -159,6 +161,7 @@ unpacked:\
 	ovideo-tangnano4k-unpacked.v oser8-tangnano4k-unpacked.v oser10-tangnano4k-unpacked.v \
 	ides16-tangnano4k-unpacked.v ides4-tangnano4k-unpacked.v ivideo-tangnano4k-unpacked.v \
 	ides8-tangnano4k-unpacked.v ides10-tangnano4k-unpacked.v oser10-tlvds-tangnano4k-unpacked.v \
+	femto-riscv-15-tangnano4k-unpacked.v femto-riscv-16-tangnano4k-unpacked.v femto-riscv-18-tangnano4k-unpacked.v \
 	\
 	blinky-tangnano9k-unpacked.v shift-tangnano9k-unpacked.v blinky-tbuf-tangnano9k-unpacked.v \
 	blinky-oddr-tangnano9k-unpacked.v blinky-osc-tangnano9k-unpacked.v tlvds-tangnano9k-unpacked.v \
@@ -171,6 +174,7 @@ unpacked:\
 	bsram-DPB-tangnano9k-unpacked.v bsram-pROMX9-tangnano9k-unpacked.v \
 	bsram-SDPX9B-tangnano9k-unpacked.v bsram-SPX9-tangnano-unpacked.v \
 	bsram-DPX9B-tangnano9k-unpacked.v \
+	femto-riscv-15-tangnano9k-unpacked.v femto-riscv-16-tangnano9k-unpacked.v femto-riscv-18-tangnano9k-unpacked.v \
 	\
 	blinky-szfpga-unpacked.v shift-szfpga-unpacked.v blinky-tbuf-szfpga-unpacked.v \
 	blinky-oddr-szfpga-unpacked.v blinky-osc-szfpga-unpacked.v tlvds-szfpga-unpacked.v \
@@ -182,6 +186,7 @@ unpacked:\
 	bsram-pROM-szfpga-unpacked.v bsram-SDPB-szfpga-unpacked.v bsram-SP-szfpga-unpacked.v \
 	bsram-SDPX9B-szfpga-unpacked.v bsram-SPX9-tangnano-unpacked.v \
 	bsram-pROMX9-szfpga-unpacked.v \
+	femto-riscv-15-szfpga-unpacked.v femto-riscv-16-szfpga-unpacked.v femto-riscv-18-szfpga-unpacked.v \
 	\
 	blinky-tec0117-unpacked.v shift-tec0117-unpacked.v blinky-tbuf-tec0117-unpacked.v \
 	blinky-oddr-tec0117-unpacked.v blinky-osc-tec0117-unpacked.v tlvds-tec0117-unpacked.v \
@@ -190,6 +195,7 @@ unpacked:\
 	oser4-tec0117-unpacked.v ovideo-tec0117-unpacked.v oser8-tec0117-unpacked.v \
 	oser10-tec0117-unpacked.v ides16-tec0117-unpacked.v ides4-tec0117-unpacked.v \
 	ivideo-tec0117-unpacked.v ides8-tec0117-unpacked.v ides10-tec0117-unpacked.v \
+	femto-riscv-15-tangnano9k-unpacked.v femto-riscv-16-tangnano9k-unpacked.v femto-riscv-18-tangnano9k-unpacked.v \
 	\
 	blinky-runber-unpacked.v shift-runber-unpacked.v blinky-tbuf-runber-unpacked.v \
 	blinky-oddr-runber-unpacked.v blinky-osc-runber-unpacked.v tlvds-runber-unpacked.v \