Missing .v files ?

[hlide]

I fail to find the definitions of modules alu_shregand ex_o_shreg.

Also:

• rtl/inst_mem_infer.v seems to contain the old instructions instead of MIPS I-like instructions.
• doc/cpu_top.pdf is probably referring to the old ISA without external/internal loopback.
• due to a lack of detailed instruction definitions in a document (the 2012 ISA version was great in details in that regard), it is unclear what MULT or MULTU really do for instance (32x32->32 or 30x18->32 or 16x16->32 ?). It seems there is only one DSP48E1 running.
• it looks like iDEA ISA 2013 and iDEA ISA 2015 have different goals since there are major differences: no MACC/MADD/MSUB and no predicate flags inside instructions.

[hycheah]

The missing modules are added to the repository: alu_intermediate_shreg.v, ex_o_shreg.v, and inst_mem.v. Try executingvsim -do run.do` in one of the folders with a do script file.

Yes, the old cpu_top.pdf refers to the initial architecture. I don't have as a detailed architecture diagram for the newer version. The architecture does not change much, only the signal names are different and there is an additional internal feedback path. The feedback path is inside the DSP and does not change the external design of the processor. Multiplication is actually 25x18, but I would advise to use only 16x16.

MACC/MADD/MSUB is removed for this version, as I wanted to concentrate on the loopback instructions. You can add them if you wish. Modify these files: defines.v, control.v, input_map.v and the shift register files (*shreg.v) that propagates the control signals. You may want to have a verification framework in place if you want to make any modifications, just to help you speed-up the debugging process.