'make project' does not work successfully

[girijabhagwat]

I am trying to implement rocket chip on zedboard. I have given rocket chip and testchipip's paths in ..common/Makefrag. Also, I have initialized the submodules. When I run the command 'make project' in my board's directory I am getting following errors. When I looked into files for errors I learned that there are some definitions missing or there are different definitions. I am not getting how to solve these issues.

[info] Compiling 7 Scala sources to /home/hardwaresec/fpga-zynq/common/target/scala-2.11/classes...
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/Configs.scala:20: value copy is not a member of Option[freechips.rocketchip.subsystem.MasterPortParams]
[error] case ExtMem => up(ExtMem, site).copy(idBits = 6)
[error] ^
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/Configs.scala:20: not found: value idBits
[error] case ExtMem => up(ExtMem, site).copy(idBits = 6)
[error] ^
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/Configs.scala:21: value copy is not a member of Option[freechips.rocketchip.subsystem.SlavePortParams]
[error] case ExtIn => up(ExtIn, site).copy(beatBytes = 4, idBits = 12)
[error] ^
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/Configs.scala:21: not found: value beatBytes
[error] case ExtIn => up(ExtIn, site).copy(beatBytes = 4, idBits = 12)
[error] ^
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/Configs.scala:21: not found: value idBits
[error] case ExtIn => up(ExtIn, site).copy(beatBytes = 4, idBits = 12)
[error] ^
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/TestHarness.scala:38: value beatBytes is not a member of Option[freechips.rocketchip.subsystem.SlavePortParams]
[error] val zynq = LazyModule(new ZynqAdapterCore(base, config.beatBytes))
[error] ^
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/Top.scala:38: not found: type HasMasterAXI4MemPort
[error] with HasMasterAXI4MemPort
[error] ^
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/Top.scala:50: not found: type HasMasterAXI4MemPortModuleImp
[error] with HasMasterAXI4MemPortModuleImp
[error] ^
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/TestHarness.scala:26: value connectSimAXIMem is not a member of zynq.FPGAZynqTopModule
[error] dut.connectSimAXIMem()
[error] ^
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/Top.scala:17: type mismatch;
[error] found : Option[freechips.rocketchip.subsystem.SlavePortParams]
[error] required: freechips.rocketchip.subsystem.SlavePortParams
[error] val adapter = Module(LazyModule(new ZynqAdapter(address, config)).module)
[error] ^
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/Top.scala:19: value mem_axi4 is not a member of zynq.FPGAZynqTopModule
[error] require(target.mem_axi4.size == 1)
[error] ^
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/Top.scala:23: value mem_axi4 is not a member of zynq.FPGAZynqTopModule
[error] val mem_axi = target.mem_axi4.head.cloneType
[error] ^
[error] 12 errors found
[error] (compile:compileIncremental) Compilation failed
[error] Total time: 10 s, completed Jul 6, 2018 3:25:26 PM
../common/Makefrag:91: recipe for target '/home/hardwaresec/fpga-zynq/common/build/Top.ZynqFPGAConfig.fir' failed
make: *** [/home/hardwaresec/fpga-zynq/common/build/Top.ZynqFPGAConfig.fir] Error 1

Is repository not updated or I am following some wrong instructions?
Thanks.

[zhemao]

Which branch of rocket-chip are you using? You seem to be on a more recent branch than the one submoduled by fpga-zynq. There were backwards-breaking changes introduced in the latest rocket-chip master, so that's why you're seeing these issues.

[girijabhagwat]

Thanks. Currently, I have installed rocket chip master branch. As per mentioned on this page, I can understand this repository does not support rocket chip master. So, can you please suggest which branch should I install?

[zhemao]

Just use the commit pointed to by the submodule. You can create a new branch from it and then add your changes.

cd fpga-zynq
git submodule update rocket-chip
git checkout -b hardwaresec

[girijabhagwat]

I am still getting same error. I Followed the suggested steps and created the new branch. But I am not sure which changes to add.

[hoangt]

I made some changes

In /common/src/main/scala/Configs.scala
case ExtMem => MasterPortParams(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=6)
case ExtIn => SlavePortParams(beatBytes=8, idBits=8, sourceBits=2)

In /common/src/main/scala/Top.scala
    //with HasMasterAXI4MemPort
   with CanHaveMasterAXI4MemPort
  ...
    with HasRTCModuleImp
    //with HasMasterAXI4MemPortModuleImp

Still facing these errors which are very odd

[error] val zynq = LazyModule(new ZynqAdapterCore(base, config.beatBytes))
....
[error] val adapter = Module(LazyModule(new ZynqAdapter(address, config)).module)

[hoangt]

Fixed errors remained
In /common/src/main/scala/TestHarness.scala, add follow line (after val config = p(ExtIn) )
val param = config.get
And use param.beatBytes instead of config.beatBytes

[girijabhagwat]

Thank you so much. I followed the instructions and it worked for that part. But, I am getting another set of errors in further execution.

[info] Compiling 7 Scala sources to /home/hardwaresec/fpga-zynq/common/target/scala-2.11/classes...
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/TestHarness.scala:26: value connectSimAXIMem is not a member of zynq.FPGAZynqTopModule
[error] dut.connectSimAXIMem()
[error] ^
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/Top.scala:17: type mismatch;
[error] found : Option[freechips.rocketchip.subsystem.SlavePortParams]
[error] required: freechips.rocketchip.subsystem.SlavePortParams
[error] val adapter = Module(LazyModule(new ZynqAdapter(address, config)).module)
[error] ^
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/Top.scala:19: value mem_axi4 is not a member of zynq.FPGAZynqTopModule
[error] require(target.mem_axi4.size == 1)
[error] ^
[error] /home/hardwaresec/fpga-zynq/common/src/main/scala/Top.scala:23: value mem_axi4 is not a member of zynq.FPGAZynqTopModule
[error] val mem_axi = target.mem_axi4.head.cloneType
[error] ^
[error] four errors found
[error] (compile:compileIncremental) Compilation failed
[error] Total time: 9 s, completed Jul 26, 2018 1:15:17 PM
../common/Makefrag:91: recipe for target '/home/hardwaresec/fpga-zynq/common/build/Top.ZynqFPGAConfig.fir' failed
make: *** [/home/hardwaresec/fpga-zynq/common/build/Top.ZynqFPGAConfig.fir] Error 1

Can you please help?
Thanks.