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USB3.ldf
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<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="USB3" device="LFE5U-45F-6BG381C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options/>
<Source name="core/usb3/usb3_crc.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core/usb3/usb3_descramble.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core/usb3/usb3_descrip_rom.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core/usb3/usb3_ep.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core/usb3/usb3_ep_ram.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core/usb3/usb3_ep0.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core/usb3/usb3_ep0in_ram.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core/usb3/usb3_lfsr.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core/usb3/usb3_link.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core/usb3/usb3_ltssm.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core/usb3/usb3_pipe.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core/usb3/usb3_protocol.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core/usb3/usb3_scramble.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core/usb3/usb3_top.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="USB3.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="USB31.sty"/>
</BaliProject>