[ptl-001-drop-stable] intel_adsp: clk: Configure correct cardinal clock divider for ACE3.0 #81
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Unlike previous platforms the Audio integration PLL is faster: 442.368 MHz instead 393.216 MHz. The default divider of 16 will result incorrect cardinal clock speed. Change it to 18 for 24.576 MHz cardinal clock. Signed-off-by: Peter Ujfalusi <[email protected]>
plbossart
approved these changes
Aug 12, 2024
|
We also need to compensate the |
In this PR? |
Let's do that as a followup if it is needed at all. |
abonislawski
approved these changes
Aug 14, 2024
abonislawski
merged commit 0e5cbee
into
thesofproject:ptl-001-drop-stable
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Unlike previous platforms the Audio integration PLL is faster: 442.368 MHz instead 393.216 MHz.
The default divider of 16 will result incorrect cardinal clock speed. Change it to 18 for 24.576 MHz cardinal clock.