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thejpsterthejpster
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Adds ARMv6 targets.
Targets added in rust-lang/rust#150138. Tested with local build of rustc.
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‎.cargo/config.toml‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,12 +16,21 @@ runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nogr
1616
[target.armv7a-none-eabi]
1717
runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
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19+
[target.armv6-none-eabihf]
20+
runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"
21+
22+
[target.armv6-none-eabi]
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runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"
24+
1925
[target.armv5te-none-eabi]
2026
runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"
2127

2228
[target.armv4t-none-eabi]
2329
runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"
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31+
[target.thumbv6-none-eabi]
32+
runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"
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2534
[target.thumbv5te-none-eabi]
2635
runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"
2736

‎aarch32-cpu/src/register/cpsr.rs‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,11 @@ impl Cpsr {
7575
/// `thumb*` targets, as Thumb-1 cannot do an MRS.
7676
#[cfg_attr(not(feature = "check-asm"), inline)]
7777
#[cfg_attr(
78-
any(arm_architecture = "v4t", arm_architecture = "v5te"),
78+
any(
79+
arm_architecture = "v4t",
80+
arm_architecture = "v5te",
81+
arm_architecture = "v6"
82+
),
7983
instruction_set(arm::a32)
8084
)]
8185
pub fn read() -> Self {
@@ -108,7 +112,11 @@ impl Cpsr {
108112
/// `thumb*` targets, as Thumb-1 cannot do an MSR.
109113
#[cfg_attr(not(feature = "check-asm"), inline)]
110114
#[cfg_attr(
111-
any(arm_architecture = "v4t", arm_architecture = "v5te"),
115+
any(
116+
arm_architecture = "v4t",
117+
arm_architecture = "v5te",
118+
arm_architecture = "v6"
119+
),
112120
instruction_set(arm::a32)
113121
)]
114122
pub unsafe fn write(_value: Self) {

‎aarch32-cpu/src/register/mod.rs‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -225,7 +225,11 @@ pub trait SysRegRead: SysReg {
225225
/// may have side-effects.
226226
#[cfg_attr(not(feature = "check-asm"), inline)]
227227
#[cfg_attr(
228-
any(arm_architecture = "v4t", arm_architecture = "v5te"),
228+
any(
229+
arm_architecture = "v4t",
230+
arm_architecture = "v5te",
231+
arm_architecture = "v6"
232+
),
229233
instruction_set(arm::a32)
230234
)]
231235
unsafe fn read_raw() -> u32 {
@@ -261,7 +265,11 @@ pub trait SysRegWrite: SysReg {
261265
/// writing valid data here.
262266
#[cfg_attr(not(feature = "check-asm"), inline)]
263267
#[cfg_attr(
264-
any(arm_architecture = "v4t", arm_architecture = "v5te"),
268+
any(
269+
arm_architecture = "v4t",
270+
arm_architecture = "v5te",
271+
arm_architecture = "v6"
272+
),
265273
instruction_set(arm::a32)
266274
)]
267275
unsafe fn write_raw(_value: u32) {

‎arm-targets/src/lib.rs‎

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -224,7 +224,10 @@ impl Arch {
224224
Some(Arch::Armv7A)
225225
} else if target.starts_with("aarch64-") || target.starts_with("aarch64be-") {
226226
Some(Arch::Armv8A)
227-
} else if target.starts_with("arm-") {
227+
} else if target.starts_with("arm-")
228+
|| target.starts_with("armv6-")
229+
|| target.starts_with("thumbv6-")
230+
{
228231
// If not specified, assume Armv6
229232
Some(Arch::Armv6)
230233
} else {
@@ -409,6 +412,26 @@ mod test {
409412
assert_eq!(target_info.abi(), Some(Abi::Eabi));
410413
}
411414

415+
#[test]
416+
fn armv6_none_eabi() {
417+
let target = "armv6-none-eabi";
418+
let target_info = process_target(target);
419+
assert_eq!(target_info.isa(), Some(Isa::A32));
420+
assert_eq!(target_info.arch(), Some(Arch::Armv6));
421+
assert_eq!(target_info.profile(), Some(Profile::Legacy));
422+
assert_eq!(target_info.abi(), Some(Abi::Eabi));
423+
}
424+
425+
#[test]
426+
fn armv6_none_eabihf() {
427+
let target = "armv6-none-eabihf";
428+
let target_info = process_target(target);
429+
assert_eq!(target_info.isa(), Some(Isa::A32));
430+
assert_eq!(target_info.arch(), Some(Arch::Armv6));
431+
assert_eq!(target_info.profile(), Some(Profile::Legacy));
432+
assert_eq!(target_info.abi(), Some(Abi::EabiHf));
433+
}
434+
412435
#[test]
413436
fn arm_unknown_linux_gnueabi() {
414437
let target = "arm-unknown-linux-gnueabi";

‎examples/versatileab/reference/abt-exception-a32-armv6-none-eabi.out‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
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Hello, this is an data abort exception example
2+
data abort occurred
3+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
4+
DFSR Status: Ok(AlignmentFault)
5+
caught unaligned_from_a32
6+
caught fault on COUNTER
7+
Doing it again
8+
data abort occurred
9+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
10+
DFSR Status: Ok(AlignmentFault)
11+
caught unaligned_from_a32
12+
caught fault on COUNTER
13+
Skipping instruction
14+
Recovered from fault OK!

‎examples/versatileab/reference/abt-exception-a32-armv6-none-eabihf.out‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
Hello, this is an data abort exception example
2+
data abort occurred
3+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
4+
DFSR Status: Ok(AlignmentFault)
5+
caught unaligned_from_a32
6+
caught fault on COUNTER
7+
Doing it again
8+
data abort occurred
9+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
10+
DFSR Status: Ok(AlignmentFault)
11+
caught unaligned_from_a32
12+
caught fault on COUNTER
13+
Skipping instruction
14+
Recovered from fault OK!

‎examples/versatileab/reference/abt-exception-a32-thumbv6-none-eabi.out‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
Hello, this is an data abort exception example
2+
data abort occurred
3+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
4+
DFSR Status: Ok(AlignmentFault)
5+
caught unaligned_from_a32
6+
caught fault on COUNTER
7+
Doing it again
8+
data abort occurred
9+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
10+
DFSR Status: Ok(AlignmentFault)
11+
caught unaligned_from_a32
12+
caught fault on COUNTER
13+
Skipping instruction
14+
Recovered from fault OK!

‎examples/versatileab/reference/abt-exception-t32-armv6-none-eabi.out‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
Hello, this is an data abort exception example
2+
data abort occurred
3+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
4+
DFSR Status: Ok(AlignmentFault)
5+
caught unaligned_from_t32
6+
caught fault on COUNTER
7+
Doing it again
8+
data abort occurred
9+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
10+
DFSR Status: Ok(AlignmentFault)
11+
caught unaligned_from_t32
12+
caught fault on COUNTER
13+
Skipping instruction
14+
Recovered from fault OK!

‎examples/versatileab/reference/abt-exception-t32-armv6-none-eabihf.out‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
Hello, this is an data abort exception example
2+
data abort occurred
3+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
4+
DFSR Status: Ok(AlignmentFault)
5+
caught unaligned_from_t32
6+
caught fault on COUNTER
7+
Doing it again
8+
data abort occurred
9+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
10+
DFSR Status: Ok(AlignmentFault)
11+
caught unaligned_from_t32
12+
caught fault on COUNTER
13+
Skipping instruction
14+
Recovered from fault OK!

‎examples/versatileab/reference/abt-exception-t32-thumbv6-none-eabi.out‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
Hello, this is an data abort exception example
2+
data abort occurred
3+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
4+
DFSR Status: Ok(AlignmentFault)
5+
caught unaligned_from_t32
6+
caught fault on COUNTER
7+
Doing it again
8+
data abort occurred
9+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
10+
DFSR Status: Ok(AlignmentFault)
11+
caught unaligned_from_t32
12+
caught fault on COUNTER
13+
Skipping instruction
14+
Recovered from fault OK!

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