Minor.

Author: sybreon

rtl/verilog/dpsram.v

@@ -41,16 +41,5 @@ module dpsram (/*AUTOARG*/
    assign 	   dat_o = rRAM[rADR];
    assign 	   xdat_o = rRAM[rXADR];   
 
-   // --- SIMULATION ONLY ------------------------------------
-   // synopsys translate_off
-   integer 	   i;
-   initial begin
-      for (i=0; i<(1<<AW); i=i+1) 
-	begin
-	   rRAM[i] <= {(DW){1'b0}};
-	end
-   end
-   // synopsys translate_on
-   
 endmodule // dpram
 

rtl/verilog/t5_ctrl.v

@@ -1,5 +1,5 @@
 /*
- Copyright 2018 Aeste Works (M) Sdn Bhd.
+ Copyright 2018 Shawn Tan <[email protected]>
  
  Licensed under the Apache License, Version 2.0 (the "License");
  you may not use this file except in compliance with the License.