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pin_assignment_de1_soc.csv
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# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# File: C:\Users\Mauro\Developer\Workspace\Quartus\midi-sequencer\pin_assignment_de1_soc.csv
# Generated on: Sun Sep 16 21:54:57 2018
# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software.
To,Direction,Location,I/O Bank,VREF Group,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair,Transceiver Analog Settings Protocol,VCCR_GXB/VCCT_GXB Voltage,Transceiver I/O Pin Termination,Transceiver Dedicated Refclk Pin Termination,Transmitter Common Mode Driver Voltage,Transmitter Slew Rate Control,Transmitter Differential Output Voltage,Receiver Buffer Common Mode Voltage
i_btn_down,Input,PIN_AA15,3B,B3B_N0,,,,,,,,,,,,,
i_btn_left,Input,PIN_Y16,3B,B3B_N0,,,,,,,,,,,,,
i_btn_right,Input,PIN_AA14,3B,B3B_N0,,,,,,,,,,,,,
i_btn_up,Input,PIN_W15,3B,B3B_N0,,,,,,,,,,,,,
i_clk,Input,PIN_AF14,3B,B3B_N0,,,,,,,,,,,,,
i_midi_in,Input,PIN_AA21,4A,B4A_N0,,,,,,,,,,,,,
i_reset_n,Input,PIN_AE12,3A,B3A_N0,,,,,,,,,,,,,
i_tr_mute[7],Input,PIN_AC9,3A,B3A_N0,,,,,,,,,,,,,
i_tr_mute[6],Input,PIN_AE11,3A,B3A_N0,,,,,,,,,,,,,
i_tr_mute[5],Input,PIN_AD12,3A,B3A_N0,,,,,,,,,,,,,
i_tr_mute[4],Input,PIN_AD11,3A,B3A_N0,,,,,,,,,,,,,
i_tr_mute[3],Input,PIN_AF10,3A,B3A_N0,,,,,,,,,,,,,
i_tr_mute[2],Input,PIN_AF9,3A,B3A_N0,,,,,,,,,,,,,
i_tr_mute[1],Input,PIN_AC12,3A,B3A_N0,,,,,,,,,,,,,
i_tr_mute[0],Input,PIN_AB12,3A,B3A_N0,,,,,,,,,,,,,
o_clip,Output,PIN_Y21,5A,B5A_N0,,,,,,,,,,,,,
o_dac_out_l[7],Output,PIN_AJ19,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_l[6],Output,PIN_AK19,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_l[5],Output,PIN_AK18,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_l[4],Output,PIN_AK16,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_l[3],Output,PIN_Y18,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_l[2],Output,PIN_AD17,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_l[1],Output,PIN_Y17,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_l[0],Output,PIN_AC18,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_r[7],Output,PIN_AA19,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_r[6],Output,PIN_AA18,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_r[5],Output,PIN_AG17,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_r[4],Output,PIN_AF16,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_r[3],Output,PIN_AE16,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_r[2],Output,PIN_AG16,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_r[1],Output,PIN_AH17,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_dac_out_r[0],Output,PIN_AH18,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_display_a[5],Output,,,,,,,,,,,,,,,,
o_display_a[4],Output,,,,,,,,,,,,,,,,
o_display_a[3],Output,,,,,,,,,,,,,,,,
o_display_a[2],Output,,,,,,,,,,,,,,,,
o_display_a[1],Output,,,,,,,,,,,,,,,,
o_display_a[0],Output,,,,,,,,,,,,,,,,
o_display_a[0][0],Output,PIN_AE26,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[0][1],Output,PIN_AE27,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[0][2],Output,PIN_AE28,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[0][3],Output,PIN_AG27,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[0][4],Output,PIN_AF28,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[0][5],Output,PIN_AG28,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[0][6],Output,PIN_AH28,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[1][0],Output,PIN_AJ29,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[1][1],Output,PIN_AH29,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[1][2],Output,PIN_AH30,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[1][3],Output,PIN_AG30,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[1][4],Output,PIN_AF29,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[1][5],Output,PIN_AF30,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[1][6],Output,PIN_AD27,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[2][0],Output,PIN_AB23,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[2][1],Output,PIN_AE29,5B,B5B_N0,,,,,,,,,,,,,
o_display_a[2][2],Output,PIN_AD29,5B,B5B_N0,,,,,,,,,,,,,
o_display_a[2][3],Output,PIN_AC28,5B,B5B_N0,,,,,,,,,,,,,
o_display_a[2][4],Output,PIN_AD30,5B,B5B_N0,,,,,,,,,,,,,
o_display_a[2][5],Output,PIN_AC29,5B,B5B_N0,,,,,,,,,,,,,
o_display_a[2][6],Output,PIN_AC30,5B,B5B_N0,,,,,,,,,,,,,
o_display_a[3][0],Output,PIN_AD26,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[3][1],Output,PIN_AC27,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[3][2],Output,PIN_AD25,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[3][3],Output,PIN_AC25,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[3][4],Output,PIN_AB28,5B,B5B_N0,,,,,,,,,,,,,
o_display_a[3][5],Output,PIN_AB25,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[3][6],Output,PIN_AB22,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[4][0],Output,PIN_AA24,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[4][1],Output,PIN_Y23,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[4][2],Output,PIN_Y24,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[4][3],Output,PIN_W22,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[4][4],Output,PIN_W24,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[4][5],Output,PIN_V23,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[4][6],Output,PIN_W25,5B,B5B_N0,,,,,,,,,,,,,
o_display_a[5][0],Output,PIN_V25,5B,B5B_N0,,,,,,,,,,,,,
o_display_a[5][1],Output,PIN_AA28,5B,B5B_N0,,,,,,,,,,,,,
o_display_a[5][2],Output,PIN_Y27,5B,B5B_N0,,,,,,,,,,,,,
o_display_a[5][3],Output,PIN_AB27,5B,B5B_N0,,,,,,,,,,,,,
o_display_a[5][4],Output,PIN_AB26,5A,B5A_N0,,,,,,,,,,,,,
o_display_a[5][5],Output,PIN_AA26,5B,B5B_N0,,,,,,,,,,,,,
o_display_a[5][6],Output,PIN_AA25,5A,B5A_N0,,,,,,,,,,,,,
o_pwm,Output,PIN_AC23,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,
o_pwm_n,Output,PIN_AE23,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,,