From 5c356354500003d4fa48b48ea2eed6e790ffd5af Mon Sep 17 00:00:00 2001 From: Andy Cheng Date: Mon, 8 Apr 2024 19:47:00 -0400 Subject: [PATCH 1/2] Update cache extended tags to not use hardcoded values --- common/defs/cache_consts.svh | 2 ++ l2/rtl/l2_localmem.sv | 6 +++--- l2/rtl/l2_localmem_asic.sv | 12 ++++++------ llc/rtl/llc_localmem.sv | 4 ++-- 4 files changed, 13 insertions(+), 11 deletions(-) diff --git a/common/defs/cache_consts.svh b/common/defs/cache_consts.svh index 47cad8e..2555c49 100644 --- a/common/defs/cache_consts.svh +++ b/common/defs/cache_consts.svh @@ -58,6 +58,8 @@ `define WORD_OFFSET (1 << `BYTE_BITS) `define LINE_ADDR_BITS (`ADDR_BITS - `SET_RANGE_LO) +`define EXTENDED_TAG_BITS (`ADDR_BITS-8) + // Cache sizes `define BYTES_PER_WORD (1 << `BYTE_BITS) `define BITS_PER_WORD (`BYTES_PER_WORD << 3) diff --git a/l2/rtl/l2_localmem.sv b/l2/rtl/l2_localmem.sv index fb042e5..dbba260 100644 --- a/l2/rtl/l2_localmem.sv +++ b/l2/rtl/l2_localmem.sv @@ -34,7 +34,7 @@ module l2_localmem ( ); //for following 2 use BRAM data width to aviod warnings, only copy relevant bits to output data - logic [23:0] rd_data_tag_tmp[`L2_NUM_PORTS][`L2_TAG_BRAMS_PER_WAY]; + logic [`EXTENDED_TAG_BITS-1:0] rd_data_tag_tmp[`L2_NUM_PORTS][`L2_TAG_BRAMS_PER_WAY]; logic [3:0] rd_data_evict_way_tmp[`L2_EVICT_WAY_BRAMS]; state_t rd_data_state_tmp[`L2_NUM_PORTS][`L2_STATE_BRAMS_PER_WAY]; line_t rd_data_line_tmp[`L2_NUM_PORTS][`L2_LINE_BRAMS_PER_WAY]; @@ -60,8 +60,8 @@ module l2_localmem ( logic wr_en_line_bank[`L2_LINE_BRAMS_PER_WAY]; //extend to the appropriate BRAM width - logic [23:0] wr_data_tag_extended; - assign wr_data_tag_extended = {{(24-`L2_TAG_BITS){1'b0}}, wr_data_tag}; + logic [`EXTENDED_TAG_BITS-1:0] wr_data_tag_extended; + assign wr_data_tag_extended = {{(`EXTENDED_TAG_BITS-`L2_TAG_BITS){1'b0}}, wr_data_tag}; logic [3:0] wr_data_evict_way_extended; assign wr_data_evict_way_extended = {{(4-`L2_WAY_BITS){1'b0}}, wr_data_evict_way}; diff --git a/l2/rtl/l2_localmem_asic.sv b/l2/rtl/l2_localmem_asic.sv index 362c4cb..997367e 100644 --- a/l2/rtl/l2_localmem_asic.sv +++ b/l2/rtl/l2_localmem_asic.sv @@ -33,7 +33,7 @@ module l2_localmem_asic ( output state_t rd_data_state[`L2_NUM_PORTS] ); - logic [23:0] rd_data_mixed_tmp[`L2_NUM_PORTS][`L2_ASIC_SRAMS_PER_WAY]; + logic [`ADDR_BITS-8-1:0] rd_data_mixed_tmp[`L2_NUM_PORTS][`L2_ASIC_SRAMS_PER_WAY]; line_t rd_data_line_tmp[`L2_NUM_PORTS][`L2_ASIC_SRAMS_PER_WAY]; //write enable decoder for ways @@ -52,14 +52,14 @@ module l2_localmem_asic ( logic wr_en_mixed_bank[`L2_ASIC_SRAMS_PER_WAY]; logic wr_en_line_bank[`L2_ASIC_SRAMS_PER_WAY]; - logic [23:0] wr_data_mixed, wr_mixed_mask; - assign wr_data_mixed = {wr_data_hprot, wr_data_state, {(24 - 1 - `STABLE_STATE_BITS - `L2_TAG_BITS){1'b0}}, wr_data_tag}; + logic [`EXTENDED_TAG_BITS-1:0] wr_data_mixed, wr_mixed_mask; + assign wr_data_mixed = {wr_data_hprot, wr_data_state, {(`EXTENDED_TAG_BITS-1 - `STABLE_STATE_BITS - `L2_TAG_BITS){1'b0}}, wr_data_tag}; l2_way_t evict_way_arr [`L2_SETS]; //determine mask for writing to shared SRAM always_comb begin - wr_mixed_mask = 24'b0; + wr_mixed_mask = {`EXTENDED_TAG_BITS{1'b0}}; if (wr_en_put_reqs) begin wr_mixed_mask[`L2_ASIC_MIXED_SRAM_HPROT_INDEX] = 1'b1; @@ -121,7 +121,7 @@ module l2_localmem_asic ( .CE0(rd_en), .WEM0(wr_mixed_mask)); `else - sram_behav #(.DATA_WIDTH(24), .NUM_WORDS(512)) mixed_sram( + sram_behav #(.DATA_WIDTH(`EXTENDED_TAG_BITS), .NUM_WORDS(512)) mixed_sram( .clk_i(clk), .req_i(rd_en), .we_i(wr_en_port[i] & wr_en_mixed_bank[j]), @@ -142,7 +142,7 @@ module l2_localmem_asic ( .CE0(rd_en), .WEM0(wr_mixed_mask)); `else - sram_behav #(.DATA_WIDTH(24), .NUM_WORDS(512)) mixed_sram( + sram_behav #(.DATA_WIDTH(`EXTENDED_TAG_BITS), .NUM_WORDS(512)) mixed_sram( .clk_i(clk), .req_i(rd_en), .we_i(wr_en_port[i] & wr_en_mixed_bank[j]), diff --git a/llc/rtl/llc_localmem.sv b/llc/rtl/llc_localmem.sv index 5dc66eb..7476fd0 100644 --- a/llc/rtl/llc_localmem.sv +++ b/llc/rtl/llc_localmem.sv @@ -76,8 +76,8 @@ module llc_localmem ( //extend to the appropriate BRAM width logic [3:0] wr_data_state_extended; assign wr_data_state_extended = {{(4-`LLC_STATE_BITS){1'b0}}, wr_data_state}; - logic [23:0] wr_data_tag_extended; - assign wr_data_tag_extended = {{(24-`LLC_TAG_BITS){1'b0}}, wr_data_tag}; + logic [`EXTENDED_TAG_BITS-1:0] wr_data_tag_extended; + assign wr_data_tag_extended = {{(`EXTENDED_TAG_BITS-`LLC_TAG_BITS){1'b0}}, wr_data_tag}; logic [3:0] wr_data_evict_way_extended; always_comb begin From e19abb9e1e6f89c7800fdfa0339d9156c840dd39 Mon Sep 17 00:00:00 2001 From: Andy Cheng Date: Sun, 21 Jul 2024 20:18:12 -0400 Subject: [PATCH 2/2] Parameterize behavioral SRAM and extended_tag_bits --- common/defs/cache_consts.svh | 3 ++- llc/rtl/llc_localmem_asic.sv | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/common/defs/cache_consts.svh b/common/defs/cache_consts.svh index 2555c49..e23c3d6 100644 --- a/common/defs/cache_consts.svh +++ b/common/defs/cache_consts.svh @@ -58,7 +58,8 @@ `define WORD_OFFSET (1 << `BYTE_BITS) `define LINE_ADDR_BITS (`ADDR_BITS - `SET_RANGE_LO) -`define EXTENDED_TAG_BITS (`ADDR_BITS-8) +`define MIN_SET_BITS 5 +`define EXTENDED_TAG_BITS (((`ADDR_BITS-`OFFSET_BITS-`MIN_SET_BITS+8-1)/8)*8) // Cache sizes `define BYTES_PER_WORD (1 << `BYTE_BITS) diff --git a/llc/rtl/llc_localmem_asic.sv b/llc/rtl/llc_localmem_asic.sv index 8d9743a..70980e4 100644 --- a/llc/rtl/llc_localmem_asic.sv +++ b/llc/rtl/llc_localmem_asic.sv @@ -152,7 +152,7 @@ module llc_localmem_asic ( .CE0(rd_en), .WEM0(wr_mixed_mask)); `else - sram_behav #(.DATA_WIDTH(28), .NUM_WORDS(512)) mixed_sram( + sram_behav #(.DATA_WIDTH(28 + `ADDR_BITS - 32), .NUM_WORDS(512)) mixed_sram( .clk_i(clk), .req_i(rd_en), .we_i(wr_en_port[i] & wr_en_mixed_bank[j]), @@ -173,7 +173,7 @@ module llc_localmem_asic ( .CE0(rd_en), .WEM0(wr_mixed_mask)); `else - sram_behav #(.DATA_WIDTH(28), .NUM_WORDS(512)) mixed_sram( + sram_behav #(.DATA_WIDTH(28 + `ADDR_BITS - 32), .NUM_WORDS(512)) mixed_sram( .clk_i(clk), .req_i(rd_en), .we_i(wr_en_port[i] & wr_en_mixed_bank[j]),