forked from pulp-platform/axi
-
Notifications
You must be signed in to change notification settings - Fork 0
/
axi_intf.sv
446 lines (385 loc) · 15.9 KB
/
axi_intf.sv
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Fabian Schuiki <[email protected]>
//
// This file defines the interfaces we support.
/// An AXI4 interface.
interface AXI_BUS #(
parameter AXI_ADDR_WIDTH = -1,
parameter AXI_DATA_WIDTH = -1,
parameter AXI_ID_WIDTH = -1,
parameter AXI_USER_WIDTH = -1
);
localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8;
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_STRB_WIDTH-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
id_t aw_id;
addr_t aw_addr;
axi_pkg::len_t aw_len;
axi_pkg::size_t aw_size;
axi_pkg::burst_t aw_burst;
logic aw_lock;
axi_pkg::cache_t aw_cache;
axi_pkg::prot_t aw_prot;
axi_pkg::qos_t aw_qos;
axi_pkg::region_t aw_region;
axi_pkg::atop_t aw_atop;
user_t aw_user;
logic aw_valid;
logic aw_ready;
data_t w_data;
strb_t w_strb;
logic w_last;
user_t w_user;
logic w_valid;
logic w_ready;
id_t b_id;
axi_pkg::resp_t b_resp;
user_t b_user;
logic b_valid;
logic b_ready;
id_t ar_id;
addr_t ar_addr;
axi_pkg::len_t ar_len;
axi_pkg::size_t ar_size;
axi_pkg::burst_t ar_burst;
logic ar_lock;
axi_pkg::cache_t ar_cache;
axi_pkg::prot_t ar_prot;
axi_pkg::qos_t ar_qos;
axi_pkg::region_t ar_region;
user_t ar_user;
logic ar_valid;
logic ar_ready;
id_t r_id;
data_t r_data;
axi_pkg::resp_t r_resp;
logic r_last;
user_t r_user;
logic r_valid;
logic r_ready;
modport Master (
output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, input aw_ready,
output w_data, w_strb, w_last, w_user, w_valid, input w_ready,
input b_id, b_resp, b_user, b_valid, output b_ready,
output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, input ar_ready,
input r_id, r_data, r_resp, r_last, r_user, r_valid, output r_ready
);
modport Slave (
input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, output aw_ready,
input w_data, w_strb, w_last, w_user, w_valid, output w_ready,
output b_id, b_resp, b_user, b_valid, input b_ready,
input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, output ar_ready,
output r_id, r_data, r_resp, r_last, r_user, r_valid, input r_ready
);
endinterface
/// A clocked AXI4 interface for use in design verification.
interface AXI_BUS_DV #(
parameter AXI_ADDR_WIDTH = -1,
parameter AXI_DATA_WIDTH = -1,
parameter AXI_ID_WIDTH = -1,
parameter AXI_USER_WIDTH = -1
)(
input logic clk_i
);
localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8;
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_STRB_WIDTH-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
id_t aw_id;
addr_t aw_addr;
axi_pkg::len_t aw_len;
axi_pkg::size_t aw_size;
axi_pkg::burst_t aw_burst;
logic aw_lock;
axi_pkg::cache_t aw_cache;
axi_pkg::prot_t aw_prot;
axi_pkg::qos_t aw_qos;
axi_pkg::region_t aw_region;
axi_pkg::atop_t aw_atop;
user_t aw_user;
logic aw_valid;
logic aw_ready;
data_t w_data;
strb_t w_strb;
logic w_last;
user_t w_user;
logic w_valid;
logic w_ready;
id_t b_id;
axi_pkg::resp_t b_resp;
user_t b_user;
logic b_valid;
logic b_ready;
id_t ar_id;
addr_t ar_addr;
axi_pkg::len_t ar_len;
axi_pkg::size_t ar_size;
axi_pkg::burst_t ar_burst;
logic ar_lock;
axi_pkg::cache_t ar_cache;
axi_pkg::prot_t ar_prot;
axi_pkg::qos_t ar_qos;
axi_pkg::region_t ar_region;
user_t ar_user;
logic ar_valid;
logic ar_ready;
id_t r_id;
data_t r_data;
axi_pkg::resp_t r_resp;
logic r_last;
user_t r_user;
logic r_valid;
logic r_ready;
modport Master (
output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, input aw_ready,
output w_data, w_strb, w_last, w_user, w_valid, input w_ready,
input b_id, b_resp, b_user, b_valid, output b_ready,
output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, input ar_ready,
input r_id, r_data, r_resp, r_last, r_user, r_valid, output r_ready
);
modport Slave (
input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, output aw_ready,
input w_data, w_strb, w_last, w_user, w_valid, output w_ready,
output b_id, b_resp, b_user, b_valid, input b_ready,
input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, output ar_ready,
output r_id, r_data, r_resp, r_last, r_user, r_valid, input r_ready
);
modport Monitor (
input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, aw_ready,
w_data, w_strb, w_last, w_user, w_valid, w_ready,
b_id, b_resp, b_user, b_valid, b_ready,
ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, ar_ready,
r_id, r_data, r_resp, r_last, r_user, r_valid, r_ready
);
// pragma translate_off
`ifndef VERILATOR
// Single-Channel Assertions: Signals including valid must not change between valid and handshake.
// AW
assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_id)));
assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_addr)));
assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_len)));
assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_size)));
assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_burst)));
assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_lock)));
assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_cache)));
assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_prot)));
assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_qos)));
assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_region)));
assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_atop)));
assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_user)));
assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> aw_valid));
// W
assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> $stable(w_data)));
assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> $stable(w_strb)));
assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> $stable(w_last)));
assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> $stable(w_user)));
assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> w_valid));
// B
assert property (@(posedge clk_i) ( b_valid && ! b_ready |=> $stable(b_id)));
assert property (@(posedge clk_i) ( b_valid && ! b_ready |=> $stable(b_resp)));
assert property (@(posedge clk_i) ( b_valid && ! b_ready |=> $stable(b_user)));
assert property (@(posedge clk_i) ( b_valid && ! b_ready |=> b_valid));
// AR
assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_id)));
assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_addr)));
assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_len)));
assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_size)));
assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_burst)));
assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_lock)));
assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_cache)));
assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_prot)));
assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_qos)));
assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_region)));
assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_user)));
assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> ar_valid));
// R
assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_id)));
assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_data)));
assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_resp)));
assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_last)));
assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_user)));
assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> r_valid));
`endif
// pragma translate_on
endinterface
/// An asynchronous AXI4 interface.
interface AXI_BUS_ASYNC
#(
parameter AXI_ADDR_WIDTH = -1,
parameter AXI_DATA_WIDTH = -1,
parameter AXI_ID_WIDTH = -1,
parameter AXI_USER_WIDTH = -1,
parameter BUFFER_WIDTH = -1
);
localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8;
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_STRB_WIDTH-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
typedef logic [BUFFER_WIDTH-1:0] buffer_t;
id_t aw_id;
addr_t aw_addr;
axi_pkg::len_t aw_len;
axi_pkg::size_t aw_size;
axi_pkg::burst_t aw_burst;
logic aw_lock;
axi_pkg::cache_t aw_cache;
axi_pkg::prot_t aw_prot;
axi_pkg::qos_t aw_qos;
axi_pkg::region_t aw_region;
axi_pkg::atop_t aw_atop;
user_t aw_user;
buffer_t aw_writetoken;
buffer_t aw_readpointer;
data_t w_data;
strb_t w_strb;
logic w_last;
user_t w_user;
buffer_t w_writetoken;
buffer_t w_readpointer;
id_t b_id;
axi_pkg::resp_t b_resp;
user_t b_user;
buffer_t b_writetoken;
buffer_t b_readpointer;
id_t ar_id;
addr_t ar_addr;
axi_pkg::len_t ar_len;
axi_pkg::size_t ar_size;
axi_pkg::burst_t ar_burst;
logic ar_lock;
axi_pkg::cache_t ar_cache;
axi_pkg::prot_t ar_prot;
axi_pkg::qos_t ar_qos;
axi_pkg::region_t ar_region;
user_t ar_user;
buffer_t ar_writetoken;
buffer_t ar_readpointer;
id_t r_id;
data_t r_data;
axi_pkg::resp_t r_resp;
logic r_last;
user_t r_user;
buffer_t r_writetoken;
buffer_t r_readpointer;
modport Master (
output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_writetoken, input aw_readpointer,
output w_data, w_strb, w_last, w_user, w_writetoken, input w_readpointer,
input b_id, b_resp, b_user, b_writetoken, output b_readpointer,
output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_writetoken, input ar_readpointer,
input r_id, r_data, r_resp, r_last, r_user, r_writetoken, output r_readpointer
);
modport Slave (
input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_writetoken, output aw_readpointer,
input w_data, w_strb, w_last, w_user, w_writetoken, output w_readpointer,
output b_id, b_resp, b_user, b_writetoken, input b_readpointer,
input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_writetoken, output ar_readpointer,
output r_id, r_data, r_resp, r_last, r_user, r_writetoken, input r_readpointer
);
endinterface
/// An AXI4-Lite interface.
interface AXI_LITE #(
parameter AXI_ADDR_WIDTH = -1,
parameter AXI_DATA_WIDTH = -1
);
localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_STRB_WIDTH-1:0] strb_t;
// AW channel
addr_t aw_addr;
axi_pkg::prot_t aw_prot;
logic aw_valid;
logic aw_ready;
data_t w_data;
strb_t w_strb;
logic w_valid;
logic w_ready;
axi_pkg::resp_t b_resp;
logic b_valid;
logic b_ready;
addr_t ar_addr;
axi_pkg::prot_t ar_prot;
logic ar_valid;
logic ar_ready;
data_t r_data;
axi_pkg::resp_t r_resp;
logic r_valid;
logic r_ready;
modport Master (
output aw_addr, aw_prot, aw_valid, input aw_ready,
output w_data, w_strb, w_valid, input w_ready,
input b_resp, b_valid, output b_ready,
output ar_addr, ar_prot, ar_valid, input ar_ready,
input r_data, r_resp, r_valid, output r_ready
);
modport Slave (
input aw_addr, aw_prot, aw_valid, output aw_ready,
input w_data, w_strb, w_valid, output w_ready,
output b_resp, b_valid, input b_ready,
input ar_addr, ar_prot, ar_valid, output ar_ready,
output r_data, r_resp, r_valid, input r_ready
);
endinterface
/// A clocked AXI4-Lite interface for use in design verification.
interface AXI_LITE_DV #(
parameter AXI_ADDR_WIDTH = -1,
parameter AXI_DATA_WIDTH = -1
)(
input logic clk_i
);
localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_STRB_WIDTH-1:0] strb_t;
// AW channel
addr_t aw_addr;
axi_pkg::prot_t aw_prot;
logic aw_valid;
logic aw_ready;
data_t w_data;
strb_t w_strb;
logic w_valid;
logic w_ready;
axi_pkg::resp_t b_resp;
logic b_valid;
logic b_ready;
addr_t ar_addr;
axi_pkg::prot_t ar_prot;
logic ar_valid;
logic ar_ready;
data_t r_data;
axi_pkg::resp_t r_resp;
logic r_valid;
logic r_ready;
modport Master (
output aw_addr, aw_prot, aw_valid, input aw_ready,
output w_data, w_strb, w_valid, input w_ready,
input b_resp, b_valid, output b_ready,
output ar_addr, ar_prot, ar_valid, input ar_ready,
input r_data, r_resp, r_valid, output r_ready
);
modport Slave (
input aw_addr, aw_prot, aw_valid, output aw_ready,
input w_data, w_strb, w_valid, output w_ready,
output b_resp, b_valid, input b_ready,
input ar_addr, ar_prot, ar_valid, output ar_ready,
output r_data, r_resp, r_valid, input r_ready
);
endinterface