diff --git a/.gitignore b/.gitignore index 42fb95e..05e50c6 100644 --- a/.gitignore +++ b/.gitignore @@ -2,7 +2,6 @@ GNUmakefile.local # Build by-products -pdl MachineArithmetic # Smalltalk/X diff --git a/.gitmodules b/.gitmodules index cf61224..22ab78d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "makefiles"] path = makefiles url = https://github.com/janvrany/smalltalk-makefiles.git +[submodule "pdl/riscv/riscv-opcodes"] + path = pdl/riscv/riscv-opcodes + url = https://github.com/riscv/riscv-opcodes.git diff --git a/README.md b/README.md index 283b04c..7d8b429 100644 --- a/README.md +++ b/README.md @@ -27,19 +27,10 @@ Either use shortcut: 1. Clone the repository ``` - git clone https://github.com/shingarov/Pharo-ArchC ArchC - ``` - - 2. Get PDLs: - - ``` - cd ArchC - ./get-pdls.sh + git clone --recurse-submodules https://github.com/shingarov/Pharo-ArchC ArchC ``` - Alternatively, you may symlink `pdl` directory wherever you keep your PDLs - - 3. Download Pharo + 2. Download Pharo ``` mkdir ArchC/pharo @@ -49,7 +40,7 @@ Either use shortcut: curl https://get.pharo.org/64/80+vm | bash ``` - 4. Load code into Pharo image: + 3. Load code into Pharo image: ``` ./pharo Pharo.image save archc @@ -67,7 +58,7 @@ Either use shortcut: 2. Clone the repository: ```` - git clone https://github.com/shingarov/Pharo-ArchC.git.git + git clone --recurse-submodules https://github.com/shingarov/Pharo-ArchC.git.git ```` 3. In Smalltalk/X, execute: diff --git a/get-pdls.sh b/get-pdls.sh deleted file mode 100755 index f3f88bc..0000000 --- a/get-pdls.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/sh - -set -e - -path=pdl -repo=https://github.com/janvrany/Pharo-ArchC-PDL.git -branch=master - -if [ ! -d "$path" ]; then - mkdir -p "$path" - git clone --recurse-submodules --branch "$branch" "$repo" "$path" -elif [ -d "$path/.git" ]; then - echo "$path" - git -C "$path" pull -fi diff --git a/pdl/REFERENCE/ArchC-v2.0-RM.pdf b/pdl/REFERENCE/ArchC-v2.0-RM.pdf new file mode 100644 index 0000000..576dd25 Binary files /dev/null and b/pdl/REFERENCE/ArchC-v2.0-RM.pdf differ diff --git a/pdl/REFERENCE/AssGen-v1.5-RM.pdf b/pdl/REFERENCE/AssGen-v1.5-RM.pdf new file mode 100644 index 0000000..459e92c Binary files /dev/null and b/pdl/REFERENCE/AssGen-v1.5-RM.pdf differ diff --git a/pdl/REFERENCE/BinutilGen-v2.1-UM.pdf b/pdl/REFERENCE/BinutilGen-v2.1-UM.pdf new file mode 100644 index 0000000..5844198 Binary files /dev/null and b/pdl/REFERENCE/BinutilGen-v2.1-UM.pdf differ diff --git a/pdl/REFERENCE/retargeting-gcc-for-archc-models.pdf b/pdl/REFERENCE/retargeting-gcc-for-archc-models.pdf new file mode 100644 index 0000000..5e5459d Binary files /dev/null and b/pdl/REFERENCE/retargeting-gcc-for-archc-models.pdf differ diff --git a/pdl/arm/.gitignore b/pdl/arm/.gitignore new file mode 100644 index 0000000..a66d688 --- /dev/null +++ b/pdl/arm/.gitignore @@ -0,0 +1,24 @@ + +Makefile +Makefile.archc +arm.H +arm.cpp +*.o +*.x +*.a +arm_arch.H +arm_arch.cpp +arm_arch_ref.H +arm_arch_ref.cpp +arm_bhv_macros.H +arm_isa.H +arm_isa.cpp.tmpl +arm_isa_init.cpp +arm_parms.H +arm_syscall.H.tmpl +arm_syscall.cpp.tmpl +main.cpp +main.cpp.tmpl +arm_ih_bhv_macros.H +arm_intr_handlers.H +arm_intr_handlers.cpp* diff --git a/pdl/arm/CONTRIBUTING.md b/pdl/arm/CONTRIBUTING.md new file mode 100644 index 0000000..39b6280 --- /dev/null +++ b/pdl/arm/CONTRIBUTING.md @@ -0,0 +1,12 @@ +# Contributing + +## Submitting a Pull Request + +1. Fork it. +2. Create a branch (`git checkout -b my_project`) +3. Commit your changes (`git commit -a`) [Tips for better commit message](https://robots.thoughtbot.com/5-useful-tips-for-a-better-commit-message) +4. Push to the branch (`git push origin my_project`) +5. Open a [Pull Request][1] +6. Enjoy a refreshing Diet Coke and wait doing more + +[1]: https://github.com/ArchC/arm/pulls diff --git a/pdl/arm/COPYING b/pdl/arm/COPYING new file mode 100644 index 0000000..d445e88 --- /dev/null +++ b/pdl/arm/COPYING @@ -0,0 +1,74 @@ + ArchC DEVELOPMENT PUBLIC LICENSE + +Everyone is permitted to copy and distribute verbatim copies of this +license document, but changing it is not allowed. + + Preamble + +You received this software from a trusted source and for research +purposes. Using or modifying this Program implies full acceptance of +this license. Please contact the person who send or gave you access to +this program for further information. + + ArchC DEVELOPMENT PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + +This license extends to all Programs contained in the package that +you received, including all subdirectories from this root, except if +the file header indicates another license. + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. + + 1. You may copy verbatim copies of the Program's source code as you +receive it, in any medium, for personal use, provided that you copy +copyright notice and disclaimer of warranty; and keep intact all the +notices that refer to this License and to the absence of any warranty. + +Personal use can be extended to a laboratory facility or a shared room +only if you are in charge of a research group that contributes to this +program and only with developing and research purposes. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy such +modifications or work under the terms of Section 1 above, provided +that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must not share, publish or distribute this program, either + in parts or in original form. You must not share, publish or + distribute programs that use this Program, either in parts or in + its original form. + + + 3. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or using the Program (or any work based on the Program), you +indicate your acceptance of this License to do so, and all its terms +and conditions for copying, distributing or modifying the Program or +works based on it. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the software in its development phase. + + NO WARRANTY + + 4. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + END OF TERMS AND CONDITIONS + diff --git a/pdl/arm/HISTORY.md b/pdl/arm/HISTORY.md new file mode 100644 index 0000000..7e7f4bf --- /dev/null +++ b/pdl/arm/HISTORY.md @@ -0,0 +1,36 @@ +## 2.4.0 + +* Revision numbers following the ArchC release +* Instructions with cycles annotations +* Two new .ac files to use with MPSoCBench (block and nonblock) +* arm_isa.cpp using the reserved work DATA_PORT to data request. See the [commit message](https://github.com/ArchC/arm/commit/2eb30a551d11636adaede7db86167b43269d56e8). +* Interrupt handler support. It is inactive in standalone simulator. + +[Full changelog](https://github.com/ArchC/arm/compare/v2.3.0...v2.4.0) + +## 2.3.0 +* Revision numbers following the ArchC release ++ Added id register for core identification +* Special case in LSM/STM was handled. Now, it's possible use Rn in Rlist, e.g., 'push {sp, ...}' +* Fixed the number of register in 16 + +[Full changelog](https://github.com/ArchC/arm/compare/v1.0.1...v2.3.0) + +## 1.0.1 +* Bugfix in BX, RSC and SBC instructions + +[Full changelog](https://github.com/ArchC/arm/compare/v1.0.0...v1.0.1) + +## 1.0.0 +* ArchC 2.2 compliant + +[Full changelog](https://github.com/ArchC/arm/compare/v0.7.0...v1.0.0) + +## 0.7.0 + +* Model passed selected Mediabench and Mibench applications +* ArchC 2.1 compliant +* Support for automatic generation of binary tools +* Support for dynamic linker and loader when reading ELF files +* Support for GDB +* Support for compiled simulator and interpreted simulator diff --git a/pdl/arm/README.md b/pdl/arm/README.md new file mode 100644 index 0000000..6f1c5d3 --- /dev/null +++ b/pdl/arm/README.md @@ -0,0 +1,75 @@ +ARMv5e ArchC functional model +===== + +This is the ARMv5e ArchC functional model. + +License +------- + - ArchC models are provided under the ArchC license. + See [Copying](COPYING) file for details on this license. + +acsim +----- +This model has the system call emulation functions implemented, +so it is a good idea to turn on the ABI option. + +To use acsim, the interpreted simulator: + + acsim armv5e.ac -abi (create the simulator) + make (compile) + armv5e.x --load= [args] (run an application) + +The [args] are optional arguments for the application. + +There are two formats recognized for application : +- ELF binary matching ArchC specifications +- hexadecimal text file for ArchC + + + +Binary utilities +---------------- +To generate binary utilities use: + + acbingen.sh -i -a armv5e.ac + +This will generate the tools source files using the architecture +name (if omitted, armv5e is used), copy them to the +binutils source tree, build and install them into the directory + (which -must- be an absolute path). +Use "acbingen.sh -h" to get information about the command-line +options available. + + +Change history +------------ + +See [History](HISTORY.md) + + +Contributing +------------ + +See [Contributing](CONTRIBUTING.md) + + +More +---- + +Remember that ArchC models and SystemC library must be compiled with +the same GCC version, otherwise you will get compilation problems. + +Several documents which further information can be found in the 'doc' +subdirectory. + +You can find language overview, models, and documentation at +http://www.archc.org + + + +Thanks for the interest. We hope you enjoy using ArchC! + +The ArchC Team +Computer Systems Laboratory (LSC) +IC-UNICAMP +http://www.lsc.ic.unicamp.br diff --git a/pdl/arm/ac_rtld.relmap b/pdl/arm/ac_rtld.relmap new file mode 100644 index 0000000..d1ce62c --- /dev/null +++ b/pdl/arm/ac_rtld.relmap @@ -0,0 +1,18 @@ +# This file contains a one-to-one mapping between ARM ABI relocation +# codes and ArchC's generated linker relocation codes. Its intended +# use is to perform a conversion using the acrelconvert tool. + +# R_ARM_RELATIVE +23 = 1 +# R_ARM_COPY +20 = 2 +# R_ARM_JUMPSLOT +22 = 3 +# R_ARM_GLOBDAT +21 = 4 +# R_ARM_ABS32 +2 = 7 +# R_ARM_REL32 +3 = 10 + +# End of file diff --git a/pdl/arm/arm.ac b/pdl/arm/arm.ac new file mode 100644 index 0000000..3ac8f82 --- /dev/null +++ b/pdl/arm/arm.ac @@ -0,0 +1,39 @@ +/** + * @file arm.ac + * @author Danilo Marcolin Caravana + * Rafael Auler + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Apr 2012 + * + * @brief The ArchC ARMv5e functional model. + * + * @attention Copyright (C) 2002-2012 --- The ArchC Team + * + */ + +AC_ARCH(arm){ + ac_mem MEM:512M; + ac_regbank RB:16; + // ac_tlm_intr_port inta; // system level interrupt port + ac_reg R14_irq, R14_fiq, R14_svc, R14_abt, R14_und, R13_irq, R13_svc; + ac_reg R13_abt, R13_und, R13_fiq; + ac_reg SPSR_irq, SPSR_fiq, SPSR_svc, SPSR_abt, SPSR_und; + // FIQ private regs + ac_reg R12_fiq, R11_fiq, R10_fiq, R9_fiq, R8_fiq; + ac_wordsize 32; + ac_reg id; + ARCH_CTOR(arm) { + ac_isa("arm_isa.ac"); + ac_gdb("arm.xml"); + defines_gdb("defines_gdb"); + set_endian("little"); + }; +}; diff --git a/pdl/arm/arm.xml b/pdl/arm/arm.xml new file mode 100644 index 0000000..317bb23 --- /dev/null +++ b/pdl/arm/arm.xml @@ -0,0 +1,79 @@ + + + + arm + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pdl/arm/arm_block.ac b/pdl/arm/arm_block.ac new file mode 100644 index 0000000..8141f64 --- /dev/null +++ b/pdl/arm/arm_block.ac @@ -0,0 +1,46 @@ +/** + * @file arm.ac + * @author Danilo Marcolin Caravana + * Rafael Auler + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Apr 2012 + * + * @brief The ArchC ARMv5e functional model. + * + * @attention Copyright (C) 2002-2012 --- The ArchC Team + * + */ + +AC_ARCH(arm){ + ac_tlm2_port MEM:512M; + ac_icache IC("2w", 128, 32, "wb", "fifo"); + ac_dcache DC("2w", 512, 32, "wt", "fifo"); + + + ac_tlm2_intr_port intr_port; + + ac_regbank RB:16; + // ac_tlm_intr_port inta; // system level interrupt port + ac_reg R14_irq, R14_fiq, R14_svc, R14_abt, R14_und, R13_irq, R13_svc; + ac_reg R13_abt, R13_und, R13_fiq; + ac_reg SPSR_irq, SPSR_fiq, SPSR_svc, SPSR_abt, SPSR_und; + // FIQ private regs + ac_reg R12_fiq, R11_fiq, R10_fiq, R9_fiq, R8_fiq; + ac_wordsize 32; + ac_fetchsize 32; + ac_reg id; + ARCH_CTOR(arm) { + ac_isa("arm_isa.ac"); + set_endian("little"); + IC.bindTo(MEM); + DC.bindTo(MEM); + }; +}; \ No newline at end of file diff --git a/pdl/arm/arm_gdb_funcs.cpp b/pdl/arm/arm_gdb_funcs.cpp new file mode 100644 index 0000000..bca03e3 --- /dev/null +++ b/pdl/arm/arm_gdb_funcs.cpp @@ -0,0 +1,55 @@ +/** + * @file arm_gdb_funcs.cpp + * @author Danilo Marcolin Caravana + * Rafael Auler + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Apr 2012 + * + * @brief The ArchC ARMv5e functional model. + * + * @attention Copyright (C) 2002-2012 --- The ArchC Team + * + */ + +#include "arm.H" + +using namespace arm_parms; + +int arm::nRegs(void) { + return 16; +} + +ac_word arm::reg_read( int reg ) { + /* general purpose registers */ + if ( ( reg >= 0 ) && ( reg < 15 ) ) + return RB.read( reg ); + else if ( reg == 15 ) + return ac_pc; + return 0; +} + +void arm::reg_write( int reg, ac_word value ) { + /* general purpose registers */ + printf("Register is: %d, value is %x\n",reg,value); + if ( ( reg >= 0 ) && ( reg < 15 ) ) + RB.write( reg, value ); + else if ( reg == 15 ) + ac_pc = value; +} + +unsigned char arm::mem_read( unsigned int address ) { + return DATA_PORT->read_byte(address); +} + +void arm::mem_write( unsigned int address, unsigned char byte ) { + DATA_PORT->write_byte( address, byte ); +} + diff --git a/pdl/arm/arm_isa.ac b/pdl/arm/arm_isa.ac new file mode 100644 index 0000000..f4eeed0 --- /dev/null +++ b/pdl/arm/arm_isa.ac @@ -0,0 +1,1018 @@ +/** + * @file arm_isa.ac + * @author Danilo Marcolin Caravana + * Rafael Auler + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Apr 2012 + * + * @brief The ArchC ARMv5e functional model. + * + * @attention Copyright (C) 2002-2012 --- The ArchC Team + * + */ + +AC_ISA(arm) { + ac_helper { + #include "arm_isa_helper.H" + }; + + /* Data processing instructions - ALU */ + ac_format Type_DPI1 = "%cond:4 %op:3 %func1:4 %s:1 %rn:4 %rd:4 %shiftamount:5 %shift:2 %subop1:1 %rm:4"; + ac_format Type_DPI2 = "%cond:4 %op:3 %func1:4 %s:1 %rn:4 %rd:4 %rs:4 %subop2:1 %shift:2 %subop1:1 %rm:4"; + ac_format Type_DPI3 = "%cond:4 %op:3 %func1:4 %s:1 %rn:4 %rd:4 %rotate:4 %imm8:8"; + + /* Branch instructions - BBLT needs cond = 1111 - bx and blx2 use type MISC1*/ + ac_format Type_BBL = "%cond:4 %op:3 %h:1 %offset:24"; + ac_format Type_BBLT = "%cond:4 %op:3 %h:1 %offset:24"; + ac_format Type_MBXBLX = "%cond:4 %op:3 %func1:4 %s:1 %one1:4 %one2:4 %one3:4 %subop2:1 %func2:2 %subop1:1 %rm:4"; + + /* Swap and multiply */ + ac_format Type_MULT1 = "%cond:4 %op:3 %func1:4 %s:1 %rn:4 %rd:4 %rs:4 %subop2:1 %func2:2 %subop1:1 %rm:4"; + ac_format Type_MULT2 = "%cond:4 %op:3 %func1:4 %s:1 %rdhi:4 %rdlo:4 %rs:4 %subop2:1 %func2:2 %subop1:1 %rm:4"; + + /* Load/Store */ + ac_format Type_LSI = "%cond:4 %op:3 %p:1 %u:1 %b:1 %w:1 %l:1 %rn:4 %rd:4 %imm12:12"; + ac_format Type_LSR = "%cond:4 %op:3 %p:1 %u:1 %b:1 %w:1 %l:1 %rn:4 %rd:4 %shiftamount:5 %shift:2 %subop1:1 %rm:4"; + ac_format Type_LSE = "%cond:4 %op:3 %p:1 %u:1 %i:1 %w:1 %l:1 %rn:4 %rd:4 %addr1:4 %subop2:1 %ss:1 %hh:1 %subop1:1 %addr2:4"; + ac_format Type_LSM = "%cond:4 %op:3 %p:1 %u:1 %r:1 %w:1 %l:1 %rn:4 %rlist:16"; + + /* Coprocessor instructions */ + ac_format Type_CDP = "%cond:4 %op:3 %subop3:1 %funcc1:4 %crn:4 %crd:4 %cp_num:4 %funcc3:3 %subop1:1 %crm:4"; + ac_format Type_CRT = "%cond:4 %op:3 %subop3:1 %funcc2:3 %l:1 %crn:4 %rd:4 %cp_num:4 %funcc3:3 %subop1:1 %crm:4"; + ac_format Type_CLS = "%cond:4 %op:3 %p:1 %u:1 %n:1 %w:1 %l:1 %rn:4 %crd:4 %cp_num:4 %imm8:8"; + + /* Special instructions */ + ac_format Type_MBKPT = "%cond:4 %op:3 %func1:4 %s:1 %immediate:12 %subop2:1 %func2:2 %subop1:1 %rm:4"; + ac_format Type_MSWI = "%cond:4 %op:3 %subop3:1 %swinumber:24"; + ac_format Type_MCLZ = "%cond:4 %op:3 %func1:4 %s:1 %one1:4 %rd:4 %one3:4 %subop2:1 %func2:2 %subop1:1 %rm:4"; + ac_format Type_MMSR1 = "%cond:4 %op:3 %func11:2 %r:1 %func12:2 %fieldmask:4 %rd:4 %zero3:4 %subop2:1 %func2:2 %subop1:1 %rm:4"; + ac_format Type_MMSR2 = "%cond:4 %op:3 %func11:2 %r:1 %func12:2 %fieldmask:4 %one2:4 %rotate:4 %imm8:8"; + + /* Data processing instructions - ALU */ + ac_instr and1, eor1, sub1, rsb1, add1, adc1, sbc1, rsc1, tst1, teq1, cmp1, cmn1, orr1, mov1, bic1, mvn1; + ac_instr and2, eor2, sub2, rsb2, add2, adc2, sbc2, rsc2, tst2, teq2, cmp2, cmn2, orr2, mov2, bic2, mvn2; + ac_instr and3, eor3, sub3, rsb3, add3, adc3, sbc3, rsc3, tst3, teq3, cmp3, cmn3, orr3, mov3, bic3, mvn3; + + /* Branch instructions - BBLT needs cond = 1111 - bx and blx2 use type MISC1*/ + ac_instr blx1; + ac_instr b; + ac_instr bx, blx2; + + /* Swap and multiply */ + ac_instr swp, swpb, mla, mul; + ac_instr smlal, smull, umlal, umull; + + /* Load/Store */ + ac_instr ldrt1, ldrbt1, ldr1, ldrb1, strt1, strbt1, str1, strb1; + ac_instr ldrt2, ldrbt2, ldr2, ldrb2, strt2, strbt2, str2, strb2; + ac_instr ldrh, ldrsb, ldrsh, strh, ldrd, strd; // ldrd e strd sao instrucoes DSP + ac_instr ldm, stm; + + /* Coprocessor instructions */ + ac_instr cdp; + ac_instr mcr, mrc; + ac_instr ldc, stc; + + /* Special instructions */ + ac_instr bkpt; + ac_instr swi; + ac_instr clz; + ac_instr mrs, msr1; + ac_instr msr2; + + /* ARM register aliases */ + ac_asm_map reg { + "r"[0..15] = [0..15]; + "a"[1..4] = [0..3]; + "v"[1..8] = [4..11]; + "wr" = 7; + "sb" = 9; + "sl" = 10; + "fp" = 11; + "ip" = 12; + "sp" = 13; + "lr" = 14; + "pc" = 15; + } + + /* ARM instruction predicates */ + ac_asm_map cond { + "eq" = 0; + "ne" = 1; + "cs", "hs" = 2; + "cc", "lo" = 3; + "mi" = 4; + "pl" = 5; + "vs" = 6; + "vc" = 7; + "hi" = 8; + "ls" = 9; + "ge" = 10; + "lt" = 11; + "gt" = 12; + "le" = 13; + "" = 14; + } + + /* ARM operand shifting options */ + ac_asm_map shift { + "LSL", "ASL", "lsl", "asl" = 0; + "LSR", "lsr" = 1; + "ASR", "asr" = 2; + "ROR", "ror" = 3; + } + + /* ARM 's flag' switch */ + ac_asm_map sf { + "" = 0; + "s" = 1; + } + + /* MSR/MRS instruction special fields */ + ac_asm_map psr { + "cpsr" = 0; + "spsr" = 1; + } + + /* Multiple load/store stack specification aliases */ + ac_asm_map mlstype { + "da" = 0; + "ia" = 1; + "db" = 2; + "ib" = 3; + } + ac_asm_map lstype { + "fa" = 0; + "fd" = 1; + "ea" = 2; + "ed" = 3; + } + + ac_asm_map sstype { + "ed" = 0; + "ea" = 1; + "fd" = 2; + "fa" = 3; + } + + + ISA_CTOR(arm) { + + /* Defining assembler-specific constraints */ + assembler.set_comment("@"); + assembler.set_line_comment("@#"); + + /**************************************/ + /* Data processing instructions - ALU */ + /**************************************/ + + and1.set_asm("and%[cond]%sf %reg, %reg, %reg", cond, s, rd, rn, rm, shiftamount=0, shift=0); + and1.set_asm("and%[cond]%sf %reg, %reg, %reg, %shift #%imm", cond, s, rd, rn, rm, shift, shiftamount); + and1.set_asm("and%[cond]%sf %reg, %reg, %reg, rrx", cond, s, rd, rn, rm, shift=3, shiftamount=0); + and1.set_decoder(op=0x00, subop1=0x00, func1=0x00); + + //and1.set_cycles(1); + + + and2.set_asm("and%[cond]%sf %reg, %reg, %reg, %shift %reg", cond, s, rd, rn, rm, shift, rs); + and2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x00); + //and2.set_cycles(1); + and3.set_asm("and%[cond]%sf %reg, %reg, #%imm(aimm)", cond, s, rd, rn, rotate+imm8); + and3.set_decoder(op=0x01, func1=0x00); + + //and3.set_cycles(1); + + eor1.set_asm("eor%[cond]%sf %reg, %reg, %reg", cond, s, rd, rn, rm, shiftamount=0, shift=0); + eor1.set_asm("eor%[cond]%sf %reg, %reg, %reg, %shift #%imm", cond, s, rd, rn, rm, shift, shiftamount); + eor1.set_asm("eor%[cond]%sf %reg, %reg, %reg, rrx", cond, s, rd, rn, rm, shift=3, shiftamount=0); + eor1.set_decoder(op=0x00, subop1=0x00, func1=0x01); + + //eor1.set_cycles(1); + + eor2.set_asm("eor%[cond]%sf %reg, %reg, %reg, %shift %reg", cond, s, rd, rn, rm, shift, rs); + eor2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x01); + + // eor2.set_cycles(1); + + eor3.set_asm("eor%[cond]%sf %reg, %reg, #%imm(aimm)", cond, s, rd, rn, rotate+imm8); + eor3.set_decoder(op=0x01, func1=0x01); + + // eor3.set_cycles(1); + + sub1.set_asm("sub%[cond]%sf %reg, %reg, %reg", cond, s, rd, rn, rm, shiftamount=0, shift=0); + sub1.set_asm("sub%[cond]%sf %reg, %reg, %reg, %shift #%imm", cond, s, rd, rn, rm, shift, shiftamount); + sub1.set_asm("sub%[cond]%sf %reg, %reg, %reg, rrx", cond, s, rd, rn, rm, shift=3, shiftamount=0); + sub1.set_decoder(op=0x00, subop1=0x00, func1=0x02); + + // sub1.set_cycles(1); + + sub2.set_asm("sub%[cond]%sf %reg, %reg, %reg, %shift %reg", cond, s, rd, rn, rm, shift, rs); + sub2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x02); + + // sub2.set_cycles(1); + + sub3.set_asm("sub%[cond]%sf %reg, %reg, #%imm(aimm)", cond, s, rd, rn, rotate+imm8); + sub3.set_decoder(op=0x01, func1=0x02); + + // sub3.set_cycles(1); + + rsb1.set_asm("rsb%[cond]%sf %reg, %reg, %reg", cond, s, rd, rn, rm, shiftamount=0, shift=0); + rsb1.set_asm("rsb%[cond]%sf %reg, %reg, %reg, %shift #%imm", cond, s, rd, rn, rm, shift, shiftamount); + rsb1.set_asm("rsb%[cond]%sf %reg, %reg, %reg, rrx", cond, s, rd, rn, rm, shift=3, shiftamount=0); + rsb1.set_decoder(op=0x00, subop1=0x00, func1=0x03); + + rsb2.set_asm("rsb%[cond]%sf %reg, %reg, %reg, %shift %reg", cond, s, rd, rn, rm, shift, rs); + rsb2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x03); + + rsb3.set_asm("rsb%[cond]%sf %reg, %reg, #%imm(aimm)", cond, s, rd, rn, rotate+imm8); + rsb3.set_decoder(op=0x01, func1=0x03); + + + add1.set_asm("add%[cond]%sf %reg, %reg, %reg", cond, s, rd, rn, rm, shiftamount=0, shift=0); + add1.set_asm("add%[cond]%sf %reg, %reg, %reg, %shift #%imm", cond, s, rd, rn, rm, shift, shiftamount); + add1.set_asm("add%[cond]%sf %reg, %reg, %reg, rrx", cond, s, rd, rn, rm, shift=3, shiftamount=0); + add1.set_asm("add%[cond]%sf %reg, PC, %reg", cond, s, rd, rm, shiftamount=0, shift=0, rn=reg.map_to("pc")); + add1.set_decoder(op=0x00, subop1=0x00, func1=0x04); + + // add1.set_cycles(1); + + add2.set_asm("add%[cond]%sf %reg, %reg, %reg, %shift %reg", cond, s, rd, rn, rm, shift, rs); + add2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x04); + + // add2.set_cycles(1); + + add3.set_asm("add%[cond]%sf %reg, %reg, #%imm(aimm)", cond, s, rd, rn, rotate+imm8); + // Pseudo instruction: ADR + //add3.set_asm("adr%[cond]%sf %reg, %exp(pcrelrot)", cond, s, rd, func1+rotate+imm8, rn=reg.map_to("pc")); + add3.set_decoder(op=0x01, func1=0x04); + + // add3.set_cycles(1); + + adc1.set_asm("adc%[cond]%sf %reg, %reg, %reg", cond, s, rd, rn, rm, shiftamount=0, shift=0); + adc1.set_asm("adc%[cond]%sf %reg, %reg, %reg, %shift #%imm", cond, s, rd, rn, rm, shift, shiftamount); + adc1.set_asm("adc%[cond]%sf %reg, %reg, %reg, rrx", cond, s, rd, rn, rm, shift=3, shiftamount=0); + adc1.set_decoder(op=0x00, subop1=0x00, func1=0x05); + + adc2.set_asm("adc%[cond]%sf %reg, %reg, %reg, %shift %reg", cond, s, rd, rn, rm, shift, rs); + adc2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x05); + + adc3.set_asm("adc%[cond]%sf %reg, %reg, #%imm(aimm)", cond, s, rd, rn, rotate+imm8); + adc3.set_decoder(op=0x01, func1=0x05); + + + sbc1.set_asm("sbc%[cond]%sf %reg, %reg, %reg", cond, s, rd, rn, rm, shiftamount=0, shift=0); + sbc1.set_asm("sbc%[cond]%sf %reg, %reg, %reg, %shift #%imm", cond, s, rd, rn, rm, shift, shiftamount); + sbc1.set_asm("sbc%[cond]%sf %reg, %reg, %reg, rrx", cond, s, rd, rn, rm, shift=3, shiftamount=0); + sbc1.set_decoder(op=0x00, subop1=0x00, func1=0x06); + + sbc2.set_asm("sbc%[cond]%sf %reg, %reg, %reg, %shift %reg", cond, s, rd, rn, rm, shift, rs); + sbc2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x06); + + sbc3.set_asm("sbc%[cond]%sf %reg, %reg, #%imm(aimm)", cond, s, rd, rn, rotate+imm8); + sbc3.set_decoder(op=0x01, func1=0x06); + + + rsc1.set_asm("rsc%[cond]%sf %reg, %reg, %reg", cond, s, rd, rn, rm, shiftamount=0, shift=0); + rsc1.set_asm("rsc%[cond]%sf %reg, %reg, %reg, %shift #%imm", cond, s, rd, rn, rm, shift, shiftamount); + rsc1.set_asm("rsc%[cond]%sf %reg, %reg, %reg, rrx", cond, s, rd, rn, rm, shift=3, shiftamount=0); + rsc1.set_decoder(op=0x00, subop1=0x00, func1=0x07); + + rsc2.set_asm("rsc%[cond]%sf %reg, %reg, %reg, %shift %reg", cond, s, rd, rn, rm, shift, rs); + rsc2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x07); + + rsc3.set_asm("rsc%[cond]%sf %reg, %reg, #%imm(aimm)", cond, s, rd, rn, rotate+imm8); + rsc3.set_decoder(op=0x01, func1=0x07); + + + tst1.set_asm("tst%[cond] %reg, %reg", cond, rn, rm, rd=0, shiftamount=0, shift=0); + tst1.set_asm("tst%[cond] %reg, %reg, %shift #%imm", cond, rn, rm, shift, shiftamount, rd=0); + tst1.set_asm("tst%[cond] %reg, %reg, rrx", cond, rn, rm, shift=3, shiftamount=0, rd=0); + tst1.set_decoder(op=0x00, subop1=0x00, func1=0x08, s=0x01); + + tst2.set_asm("tst%[cond] %reg, %reg, %shift %reg", cond, rn, rm, shift, rs, rd=0); + tst2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x08, s=0x01); + + tst3.set_asm("tst%[cond] %reg, #%imm(aimm)", cond, rn, rotate+imm8, rd=0); + tst3.set_decoder(op=0x01, func1=0x08, s=0x01); + + + teq1.set_asm("teq%[cond] %reg, %reg", cond, rn, rm, rd=0, shiftamount=0, shift=0); + teq1.set_asm("teq%[cond] %reg, %reg, %shift #%imm", cond, rn, rm, shift, shiftamount, rd=0); + teq1.set_asm("teq%[cond] %reg, %reg, rrx", cond, rn, rm, shift=3, shiftamount=0, rd=0); + teq1.set_decoder(op=0x00, subop1=0x00, func1=0x09, s=0x01); + + teq2.set_asm("teq%[cond] %reg, %reg, %shift %reg", cond, rn, rm, shift, rs, rd=0); + teq2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x09, s=0x01); + + teq3.set_asm("teq%[cond] %reg, #%imm(aimm)", cond, rn, rotate+imm8, rd=0); + teq3.set_decoder(op=0x01, func1=0x09, s=0x01); + + + cmp1.set_asm("cmp%[cond] %reg, %reg", cond, rn, rm, rd=0, shiftamount=0, shift=0); + cmp1.set_asm("cmp%[cond] %reg, %reg, %shift #%imm", cond, rn, rm, shift, shiftamount, rd=0); + cmp1.set_asm("cmp%[cond] %reg, %reg, rrx", cond, rn, rm, shift=3, shiftamount=0, rd=0); + cmp1.set_decoder(op=0x00, subop1=0x00, func1=0x0A, s=0x01); + + cmp2.set_asm("cmp%[cond] %reg, %reg, %shift %reg", cond, rn, rm, shift, rs, rd=0); + cmp2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x0A, s=0x01); + + cmp3.set_asm("cmp%[cond] %reg, #%imm(aimm)", cond, rn, rotate+imm8, rd=0); + cmp3.set_decoder(op=0x01, func1=0x0A, s=0x01); + + + cmn1.set_asm("cmn%[cond] %reg, %reg", cond, rn, rm, rd=0, shiftamount=0, shift=0); + cmn1.set_asm("cmn%[cond] %reg, %reg, %shift #%imm", cond, rn, rm, shift, shiftamount, rd=0); + cmn1.set_asm("cmn%[cond] %reg, %reg, rrx", cond, rn, rm, shift=3, shiftamount=0, rd=0); + cmn1.set_decoder(op=0x00, subop1=0x00, func1=0x0B, s=0x01); + + cmn2.set_asm("cmn%[cond] %reg, %reg, %shift %reg", cond, rn, rm, shift, rs, rd=0); + cmn2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x0B, s=0x01); + + cmn3.set_asm("cmn%[cond] %reg, #%imm(aimm)", cond, rn, rotate+imm8, rd=0); + cmn3.set_decoder(op=0x01, func1=0x0B, s=0x01); + + + orr1.set_asm("orr%[cond]%sf %reg, %reg, %reg", cond, s, rd, rn, rm, shiftamount=0, shift=0); + orr1.set_asm("orr%[cond]%sf %reg, %reg, %reg, %shift #%imm", cond, s, rd, rn, rm, shift, shiftamount); + orr1.set_asm("orr%[cond]%sf %reg, %reg, %reg, rrx", cond, s, rd, rn, rm, shift=3, shiftamount=0); + orr1.set_decoder(op=0x00, subop1=0x00, func1=0x0C); + + orr2.set_asm("orr%[cond]%sf %reg, %reg, %reg, %shift %reg", cond, s, rd, rn, rm, shift, rs); + orr2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x0C); + + orr3.set_asm("orr%[cond]%sf %reg, %reg, #%imm(aimm)", cond, s, rd, rn, rotate+imm8); + orr3.set_decoder(op=0x01, func1=0x0C); + + + mov1.set_asm("mov%[cond]%sf %reg, %reg", cond, s, rd, rm, rn=0, shiftamount=0, shift=0); + mov1.set_asm("mov pc, lr", cond=0xE, s=0, rd=0xF, rm=0xE, rn=0, shiftamount=0, shift=0); + mov1.set_asm("mov r0, r0", cond=0xE, s=0, rd=0x0, rm=0x0, rn=0, shiftamount=0, shift=0); + mov1.set_asm("mov%[cond]%sf %reg, %reg, %shift #%imm", cond, s, rd, rm, shift, shiftamount, rn=0); + mov1.set_asm("mov%[cond]%sf %reg, %reg, rrx", cond, s, rd, rm, shift=3, shiftamount=0, rn=0); + mov1.set_decoder(op=0x00, subop1=0x00, func1=0x0D); + + mov2.set_asm("mov%[cond]%sf %reg, %reg, %shift %reg", cond, s, rd, rm, shift, rs, rn=0); + mov2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x0D); + + mov3.set_asm("mov%[cond]%sf %reg, #%imm(aimm)", cond, s, rd, rotate+imm8, rn=0); + mov3.set_decoder(op=0x01, func1=0x0D); + + + bic1.set_asm("bic%[cond]%sf %reg, %reg, %reg", cond, s, rd, rn, rm, shiftamount=0, shift=0); + bic1.set_asm("bic%[cond]%sf %reg, %reg, %reg, %shift #%imm", cond, s, rd, rn, rm, shift, shiftamount); + bic1.set_asm("bic%[cond]%sf %reg, %reg, %reg, rrx", cond, s, rd, rn, rm, shift=3, shiftamount=0); + bic1.set_decoder(op=0x00, subop1=0x00, func1=0x0E); + + bic2.set_asm("bic%[cond]%sf %reg, %reg, %reg, %shift %reg", cond, s, rd, rn, rm, shift, rs); + bic2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x0E); + + bic3.set_asm("bic%[cond]%sf %reg, %reg, #%imm(aimm)", cond, s, rd, rn, rotate+imm8); + bic3.set_decoder(op=0x01, func1=0x0E); + + + mvn1.set_asm("mvn%[cond]%sf %reg, %reg", cond, s, rd, rm, rn=0, shiftamount=0, shift=0); + mvn1.set_asm("mvn%[cond]%sf %reg, %reg, %shift #%imm", cond, s, rd, rm, shift, shiftamount, rn=0); + mvn1.set_asm("mvn%[cond]%sf %reg, %reg, rrx", cond, s, rd, rm, shift=3, shiftamount=0, rn=0); + mvn1.set_decoder(op=0x00, subop1=0x00, func1=0x0F); + + mvn2.set_asm("mvn%[cond]%sf %reg, %reg, %shift %reg", cond, s, rd, rm, shift, rs, rn=0); + mvn2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x0F); + + mvn3.set_asm("mvn%[cond]%sf %reg, #%imm(aimm)", cond, s, rd, rotate+imm8, rn=0); + mvn3.set_decoder(op=0x01, func1=0x0F); + + + /***********************/ + /* Branch instructions */ + /***********************/ + + blx1.set_asm("blx %exp(bximm)", h+offset); + blx1.set_decoder(op=0x05, cond=0x0F); + + // blx1.set_cycles(3); + + b.set_asm("b%[cond] %exp(bimm)", cond, offset, h=0); + b.set_asm("bl%[cond] %exp(bimm)", cond, offset, h=1); + b.set_decoder(op=0x05); + + // b.set_cycles(3); + + bx.set_asm("bx%[cond] %reg", cond, rm, one1=0xF, one2=0xF, one3=0xF); + bx.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x09, s=0x00, func2=0x00); + + // bx.set_cycles(3); + + blx2.set_asm("blx%[cond] %reg", cond, rm, one1=0xF, one2=0xF, one3=0xF); + blx2.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x09, s=0x00, func2=0x01); + + // blx2.set_cycles(3); + + /**************************************/ + /* Swap/Multiplication instructions */ + /**************************************/ + + swp.set_asm("swp%[cond] %reg, %reg, [%reg]", cond, rd, rm, rn, rs=0x00); + swp.set_decoder(op=0x00, subop1=0x01, subop2=0x01, func1=0x08, func2=0x00, s=0x00); + + // swp.set_cycles(3); + + + swpb.set_asm("swp%[cond]b %reg, %reg, [%reg]", cond, rd, rm, rn, rs=0x00); + swpb.set_decoder(op=0x00, subop1=0x01, subop2=0x01, func1=0x0A, func2=0x00, s=0x00); + + // swpb.set_cycles(3); + + mul.set_asm("mul%[cond]%sf %reg, %reg, %reg", cond, s, rn, rm ,rs, rd=0x00); + mul.set_decoder(op=0x00, subop1=0x01, subop2=0x01, func1=0x00, func2=0x00); + + // mul.set_cycles(3); + + mla.set_asm("mla%[cond]%sf %reg, %reg, %reg, %reg", cond, s, rn, rm, rs, rd); + mla.set_decoder(op=0x00, subop1=0x01, subop2=0x01, func1=0x01, func2=0x00); + + // mla.set_cycles(3); + + smlal.set_asm("smlal%[cond]%sf %reg, %reg, %reg, %reg", cond, s, rdlo, rdhi, rm, rs); + smlal.set_decoder(op=0x00, subop1=0x01, subop2=0x01, func1=0x07, func2=0x00); + + // smlal.set_cycles(4); + + smull.set_asm("smull%[cond]%sf %reg, %reg, %reg, %reg", cond, s, rdlo, rdhi, rm, rs); + smull.set_decoder(op=0x00, subop1=0x01, subop2=0x01, func1=0x06, func2=0x00); + + // smull.set_cycles(4); + + umlal.set_asm("umlal%[cond]%sf %reg, %reg, %reg, %reg", cond, s, rdlo, rdhi, rm ,rs); + umlal.set_decoder(op=0x00, subop1=0x01, subop2=0x01, func1=0x05, func2=0x00); + + // umlal.set_cycles(5); + + umull.set_asm("umull%[cond]%sf %reg, %reg, %reg, %reg", cond, s, rdlo, rdhi, rm, rs); + umull.set_decoder(op=0x00, subop1=0x01, subop2=0x01, func1=0x04, func2=0x00); + + // umull.set_cycles(4); + + /****************************/ + /* Load/store instructions */ + /****************************/ + + // Note: Extensive syntax overloading is used in these instructions due to the nature + // of the addressing modes syntax for load/store instructions. Therefore, each instruction + // is followed by comments regarding which addressing mode is implemented. For more + // information, please refer to any ARM Assembly Language guide. + + //LDRT + //Features only post-indexed addressing modes (addr. mode 2 - register indirect, base plus offset and base plus index) + ldrt1.set_asm("ldr%[cond]t %reg, [%reg]", cond, rd, rn, imm12=0x00, u=0x01); + ldrt1.set_asm("ldr%[cond]t %reg, [%reg], #+%imm", cond, rd, rn, imm12, u=0x01); + ldrt1.set_asm("ldr%[cond]t %reg, [%reg], #-%imm", cond, rd, rn, imm12, u=0x00); + ldrt1.set_asm("ldr%[cond]t %reg, [%reg], #%imm", cond, rd, rn, imm12, u=0x01); + ldrt1.set_decoder(op=0x02, p=0x00, b=0x00, w=0x01, l=0x01); + + // ldrt1.set_cycles(3); + + ldrt2.set_asm("ldr%[cond]t %reg, [%reg], +%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01); + ldrt2.set_asm("ldr%[cond]t %reg, [%reg], -%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x00); + ldrt2.set_asm("ldr%[cond]t %reg, [%reg], %reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01); + ldrt2.set_asm("ldr%[cond]t %reg, [%reg], +%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01); + ldrt2.set_asm("ldr%[cond]t %reg, [%reg], -%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x00); + ldrt2.set_asm("ldr%[cond]t %reg, [%reg], %reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01); + ldrt2.set_asm("ldr%[cond]t %reg, [%reg], +%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01); + ldrt2.set_asm("ldr%[cond]t %reg, [%reg], -%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x00); + ldrt2.set_asm("ldr%[cond]t %reg, [%reg], %reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01); + ldrt2.set_decoder(op=0x03, subop1=0x00, p=0x00, b=0x00, w=0x01, l=0x01); + + // ldrt2.set_cycles(3); + + //LDRBT + //Features only post-indexed addressing modes (addr. mode 2 - register indirect, base plus offset and base plus index) + ldrbt1.set_asm("ldr%[cond]bt %reg, [%reg]", cond, rd, rn, imm12=0x00, u=0x01); + ldrbt1.set_asm("ldr%[cond]bt %reg, [%reg], #+%imm", cond, rd, rn, imm12, u=0x01); + ldrbt1.set_asm("ldr%[cond]bt %reg, [%reg], #-%imm", cond, rd, rn, imm12, u=0x00); + ldrbt1.set_asm("ldr%[cond]bt %reg, [%reg], #%imm", cond, rd, rn, imm12, u=0x01); + ldrbt1.set_decoder(op=0x02, p=0x00, b=0x01, w=0x01, l=0x01); + + // ldrbt1.set_cycles(3); + + ldrbt2.set_asm("ldr%[cond]bt %reg, [%reg], +%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01); + ldrbt2.set_asm("ldr%[cond]bt %reg, [%reg], -%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x00); + ldrbt2.set_asm("ldr%[cond]bt %reg, [%reg], %reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01); + ldrbt2.set_asm("ldr%[cond]bt %reg, [%reg], +%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01); + ldrbt2.set_asm("ldr%[cond]bt %reg, [%reg], -%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x00); + ldrbt2.set_asm("ldr%[cond]bt %reg, [%reg], %reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01); + ldrbt2.set_asm("ldr%[cond]bt %reg, [%reg], +%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01); + ldrbt2.set_asm("ldr%[cond]bt %reg, [%reg], -%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x00); + ldrbt2.set_asm("ldr%[cond]bt %reg, [%reg], %reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01); + ldrbt2.set_decoder(op=0x03, subop1=0x00, p=0x00, b=0x01, w=0x01, l=0x01); + + // ldrbt2.set_cycles(3); + + //LDR + // Includes all addressing syntaxes in addressing mode 2 - load/store instructions + // Immediate offset/pre-indexed/post-indexed (Base plus offset addressing) + // Normal base plus offset/Register indirect (p=1 w=0) + ldr1.set_asm("ldr%[cond] %reg, [%reg]", cond, rd, rn, imm12=0x0, p=1, u=1, w=0); + ldr1.set_asm("ldr%[cond] %reg, [%reg, #+%imm]", cond, rd, rn, imm12, p=1, u=1, w=0); + ldr1.set_asm("ldr%[cond] %reg, [%reg, #-%imm]", cond, rd, rn, imm12, p=1, u=0, w=0); + ldr1.set_asm("ldr%[cond] %reg, [%reg, #%imm]", cond, rd, rn, imm12, p=1, u=1, w=0); + // Aditional LDR use (pseudo syntax?) - only for this instruction, not for variants - comforming to gas + ldr1.set_asm("ldr%[cond] %reg, %exp(pcrelldr)", cond, rd, u+imm12, rn=0x0f, p=1, w=0); + // Pre-indexed (p=1 w=1) + ldr1.set_asm("ldr%[cond] %reg, [%reg, #+%imm]!", cond, rd, rn, imm12, p=1, u=1, w=1); + ldr1.set_asm("ldr%[cond] %reg, [%reg, #-%imm]!", cond, rd, rn, imm12, p=1, u=0, w=1); + ldr1.set_asm("ldr%[cond] %reg, [%reg, #%imm]!", cond, rd, rn, imm12, p=1, u=1, w=1); + // Post-indexed (p=0 w=0) + ldr1.set_asm("ldr%[cond] %reg, [%reg], #+%imm", cond, rd, rn, imm12, u=0x01, p=0x00, w=0x00); + ldr1.set_asm("ldr%[cond] %reg, [%reg], #-%imm", cond, rd, rn, imm12, u=0x00, p=0x00, w=0x00); + ldr1.set_asm("ldr%[cond] %reg, [%reg], #%imm", cond, rd, rn, imm12, u=0x01, p=0x00, w=0x00); + ldr1.set_decoder(op=0x02, b=0x00, l=0x01); + + // ldr1.set_cycles(3); + + // Base plus (scaled) index addressing (normal/pre-indexed/post-indexed) + // Normal base plus index addressing (p=1 w=0) + ldr2.set_asm("ldr%[cond] %reg, [%reg, +%reg]", cond, rd, rn, rm, p=1, w=0, shiftamount=0, shift=0, u=1); + ldr2.set_asm("ldr%[cond] %reg, [%reg, -%reg]", cond, rd, rn, rm, p=1, w=0, shiftamount=0, shift=0, u=0); + ldr2.set_asm("ldr%[cond] %reg, [%reg, %reg]", cond, rd, rn, rm, p=1, w=0, shiftamount=0, shift=0, u=1); + ldr2.set_asm("ldr%[cond] %reg, [%reg, +%reg, %shift #%imm]", cond, rd, rn, rm, shift, shiftamount, p=1, w=0, u=1); + ldr2.set_asm("ldr%[cond] %reg, [%reg, -%reg, %shift #%imm]", cond, rd, rn, rm, shift, shiftamount, p=1, w=0, u=0); + ldr2.set_asm("ldr%[cond] %reg, [%reg, %reg, %shift #%imm]", cond, rd, rn, rm, shift, shiftamount, p=1, w=0, u=1); + ldr2.set_asm("ldr%[cond] %reg, [%reg, +%reg, rrx]", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=0, u=1); + ldr2.set_asm("ldr%[cond] %reg, [%reg, -%reg, rrx]", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=0, u=0); + ldr2.set_asm("ldr%[cond] %reg, [%reg, %reg, rrx]", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=0, u=1); + // Pre-indexed (p=1 w=1) + ldr2.set_asm("ldr%[cond] %reg, [%reg, +%reg]!", cond, rd, rn, rm, p=1, w=1, shiftamount=0, shift=0, u=1); + ldr2.set_asm("ldr%[cond] %reg, [%reg, -%reg]!", cond, rd, rn, rm, p=1, w=1, shiftamount=0, shift=0, u=0); + ldr2.set_asm("ldr%[cond] %reg, [%reg, %reg]!", cond, rd, rn, rm, p=1, w=1, shiftamount=0, shift=0, u=1); + ldr2.set_asm("ldr%[cond] %reg, [%reg, +%reg, %shift #%imm]!", cond, rd, rn, rm, shift, shiftamount, p=1, w=1, u=1); + ldr2.set_asm("ldr%[cond] %reg, [%reg, -%reg, %shift #%imm]!", cond, rd, rn, rm, shift, shiftamount, p=1, w=1, u=0); + ldr2.set_asm("ldr%[cond] %reg, [%reg, %reg, %shift #%imm]!", cond, rd, rn, rm, shift, shiftamount, p=1, w=1, u=1); + ldr2.set_asm("ldr%[cond] %reg, [%reg, +%reg, rrx]!", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=1, u=1); + ldr2.set_asm("ldr%[cond] %reg, [%reg, -%reg, rrx]!", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=1, u=0); + ldr2.set_asm("ldr%[cond] %reg, [%reg, %reg, rrx]!", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=1, u=1); + // Post-indexed (p=0 w=0) + ldr2.set_asm("ldr%[cond] %reg, [%reg], +%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01, p=0x00, w=0x00); + ldr2.set_asm("ldr%[cond] %reg, [%reg], -%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x00, p=0x00, w=0x00); + ldr2.set_asm("ldr%[cond] %reg, [%reg], %reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01, p=0x00, w=0x00); + ldr2.set_asm("ldr%[cond] %reg, [%reg], +%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01, p=0x00, w=0x00); + ldr2.set_asm("ldr%[cond] %reg, [%reg], -%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x00, p=0x00, w=0x00); + ldr2.set_asm("ldr%[cond] %reg, [%reg], %reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01, p=0x00, w=0x00); + ldr2.set_asm("ldr%[cond] %reg, [%reg], +%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01, p=0x00, w=0x00); + ldr2.set_asm("ldr%[cond] %reg, [%reg], -%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x00, p=0x00, w=0x00); + ldr2.set_asm("ldr%[cond] %reg, [%reg], %reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01, p=0x00, w=0x00); + ldr2.set_decoder(op=0x03, subop1=0x00, b=0x00, l=0x01); + + // ldr2.set_cycles(3); + + //LDRB + // Includes all addressing syntaxes in addressing mode 2 - load/store instructions + // Immediate offset/pre-indexed/post-indexed (Base plus offset addressing) + // Normal base plus offset/Register indirect (p=1 w=0) + ldrb1.set_asm("ldr%[cond]b %reg, [%reg]", cond, rd, rn, imm12=0x0, p=1, u=1, w=0); + ldrb1.set_asm("ldr%[cond]b %reg, [%reg, #+%imm]", cond, rd, rn, imm12, p=1, u=1, w=0); + ldrb1.set_asm("ldr%[cond]b %reg, [%reg, #-%imm]", cond, rd, rn, imm12, p=1, u=0, w=0); + ldrb1.set_asm("ldr%[cond]b %reg, [%reg, #%imm]", cond, rd, rn, imm12, p=1, u=1, w=0); + // Pre-indexed (p=1 w=1) + ldrb1.set_asm("ldr%[cond]b %reg, [%reg, #+%imm]!", cond, rd, rn, imm12, p=1, u=1, w=1); + ldrb1.set_asm("ldr%[cond]b %reg, [%reg, #-%imm]!", cond, rd, rn, imm12, p=1, u=0, w=1); + ldrb1.set_asm("ldr%[cond]b %reg, [%reg, #%imm]!", cond, rd, rn, imm12, p=1, u=1, w=1); + // Post-indexed (p=0 w=0) + ldrb1.set_asm("ldr%[cond]b %reg, [%reg], #+%imm", cond, rd, rn, imm12, u=0x01, p=0x00, w=0x00); + ldrb1.set_asm("ldr%[cond]b %reg, [%reg], #-%imm", cond, rd, rn, imm12, u=0x00, p=0x00, w=0x00); + ldrb1.set_asm("ldr%[cond]b %reg, [%reg], #%imm", cond, rd, rn, imm12, u=0x01, p=0x00, w=0x00); + ldrb1.set_decoder(op=0x02, b=0x01, l=0x01); + + // ldrb1.set_cycles(3); + + // Base plus (scaled) index addressing (normal/pre-indexed/post-indexed) + // Normal base plus index addressing (p=1 w=0) + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, +%reg]", cond, rd, rn, rm, p=1, w=0, shiftamount=0, shift=0, u=1); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, -%reg]", cond, rd, rn, rm, p=1, w=0, shiftamount=0, shift=0, u=0); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, %reg]", cond, rd, rn, rm, p=1, w=0, shiftamount=0, shift=0, u=1); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, +%reg, %shift #%imm]", cond, rd, rn, rm, shift, shiftamount, p=1, w=0, u=1); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, -%reg, %shift #%imm]", cond, rd, rn, rm, shift, shiftamount, p=1, w=0, u=0); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, %reg, %shift #%imm]", cond, rd, rn, rm, shift, shiftamount, p=1, w=0, u=1); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, +%reg, rrx]", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=0, u=1); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, -%reg, rrx]", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=0, u=0); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, %reg, rrx]", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=0, u=1); + // Pre-indexed (p=1 w=1) + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, +%reg]!", cond, rd, rn, rm, p=1, w=1, shiftamount=0, shift=0, u=1); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, -%reg]!", cond, rd, rn, rm, p=1, w=1, shiftamount=0, shift=0, u=0); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, %reg]!", cond, rd, rn, rm, p=1, w=1, shiftamount=0, shift=0, u=1); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, +%reg, %shift #%imm]!", cond, rd, rn, rm, shift, shiftamount, p=1, w=1, u=1); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, -%reg, %shift #%imm]!", cond, rd, rn, rm, shift, shiftamount, p=1, w=1, u=0); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, %reg, %shift #%imm]!", cond, rd, rn, rm, shift, shiftamount, p=1, w=1, u=1); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, +%reg, rrx]!", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=1, u=1); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, -%reg, rrx]!", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=1, u=0); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg, %reg, rrx]!", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=1, u=1); + // Post-indexed (p=0 w=0) + ldrb2.set_asm("ldr%[cond]b %reg, [%reg], +%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01, p=0x00, w=0x00); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg], -%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x00, p=0x00, w=0x00); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg], %reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01, p=0x00, w=0x00); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg], +%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01, p=0x00, w=0x00); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg], -%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x00, p=0x00, w=0x00); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg], %reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01, p=0x00, w=0x00); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg], +%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01, p=0x00, w=0x00); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg], -%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x00, p=0x00, w=0x00); + ldrb2.set_asm("ldr%[cond]b %reg, [%reg], %reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01, p=0x00, w=0x00); + ldrb2.set_decoder(op=0x03, subop1=0x00, b=0x01, l=0x01); + + // ldrb2.set_cycles(3); + + //LDRH + // Supports all adressing syntaxes in addressing mode 3 - miscellaneous load/store instructions + // (Like regular addressing modes 2, but without base plus scaled index addressing) + // Normal base plus offset or base plus index + ldrh.set_asm("ldr%[cond]h %reg, [%reg]", cond, rd, rn, addr1=0, addr2=0, u=1, p=1, w=0, i=1); + ldrh.set_asm("ldr%[cond]h %reg, [%reg, #+%imm]", cond, rd, rn, addr1+addr2, u=1, p=1, w=0, i=1); + ldrh.set_asm("ldr%[cond]h %reg, [%reg, #-%imm]", cond, rd, rn, addr1+addr2, u=0, p=1, w=0, i=1); + ldrh.set_asm("ldr%[cond]h %reg, [%reg, #%imm]", cond, rd, rn, addr1+addr2, u=1, p=1, w=0, i=1); + ldrh.set_asm("ldr%[cond]h %reg, [%reg, +%reg]", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=0, i=0); + ldrh.set_asm("ldr%[cond]h %reg, [%reg, -%reg]", cond, rd, rn, addr2, addr1=0x0, u=0, p=1, w=0, i=0); + ldrh.set_asm("ldr%[cond]h %reg, [%reg, %reg]", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=0, i=0); + // Pre-indexed (base plus offset/base plus index) + ldrh.set_asm("ldr%[cond]h %reg, [%reg, #+%imm]!", cond, rd, rn, addr1+addr2, u=1, p=1, w=1, i=1); + ldrh.set_asm("ldr%[cond]h %reg, [%reg, #-%imm]!", cond, rd, rn, addr1+addr2, u=0, p=1, w=1, i=1); + ldrh.set_asm("ldr%[cond]h %reg, [%reg, #%imm]!", cond, rd, rn, addr1+addr2, u=1, p=1, w=1, i=1); + ldrh.set_asm("ldr%[cond]h %reg, [%reg, +%reg]!", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=1, i=0); + ldrh.set_asm("ldr%[cond]h %reg, [%reg, -%reg]!", cond, rd, rn, addr2, addr1=0x0, u=0, p=1, w=1, i=0); + ldrh.set_asm("ldr%[cond]h %reg, [%reg, %reg]!", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=1, i=0); + // Post-indexed (base plus offset/base plus index) + ldrh.set_asm("ldr%[cond]h %reg, [%reg], #+%imm", cond, rd, rn, addr1+addr2, u=1, p=0, w=0, i=1); + ldrh.set_asm("ldr%[cond]h %reg, [%reg], #-%imm", cond, rd, rn, addr1+addr2, u=0, p=0, w=0, i=1); + ldrh.set_asm("ldr%[cond]h %reg, [%reg], #%imm", cond, rd, rn, addr1+addr2, u=1, p=0, w=0, i=1); + ldrh.set_asm("ldr%[cond]h %reg, [%reg], +%reg", cond, rd, rn, addr2, addr1=0x0, u=1, p=0, w=0, i=0); + ldrh.set_asm("ldr%[cond]h %reg, [%reg], -%reg", cond, rd, rn, addr2, addr1=0x0, u=0, p=0, w=0, i=0); + ldrh.set_asm("ldr%[cond]h %reg, [%reg], %reg", cond, rd, rn, addr2, addr1=0x0, u=1, p=0, w=0, i=0); + ldrh.set_decoder(op=0x00, subop1=0x01, subop2=0x01, ss=0x00, hh=0x01, l=0x01); + + // ldrh.set_cycles(3); + + //LDRSB + // Supports all adressing syntaxes in addressing mode 3 - miscellaneous load/store instructions + // (Like regular addressing modes 2, but without base plus scaled index addressing) + // Normal base plus offset or base plus index + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg]", cond, rd, rn, addr1=0, addr2=0, u=1, p=1, w=0, i=1); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg, #+%imm]", cond, rd, rn, addr1+addr2, u=1, p=1, w=0, i=1); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg, #-%imm]", cond, rd, rn, addr1+addr2, u=0, p=1, w=0, i=1); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg, #%imm]", cond, rd, rn, addr1+addr2, u=1, p=1, w=0, i=1); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg, +%reg]", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=0, i=0); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg, -%reg]", cond, rd, rn, addr2, addr1=0x0, u=0, p=1, w=0, i=0); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg, %reg]", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=0, i=0); + // Pre-indexed (base plus offset/base plus index) + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg, #+%imm]!", cond, rd, rn, addr1+addr2, u=1, p=1, w=1, i=1); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg, #-%imm]!", cond, rd, rn, addr1+addr2, u=0, p=1, w=1, i=1); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg, #%imm]!", cond, rd, rn, addr1+addr2, u=1, p=1, w=1, i=1); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg, +%reg]!", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=1, i=0); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg, -%reg]!", cond, rd, rn, addr2, addr1=0x0, u=0, p=1, w=1, i=0); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg, %reg]!", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=1, i=0); + // Post-indexed (base plus offset/base plus index) + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg], #+%imm", cond, rd, rn, addr1+addr2, u=1, p=0, w=0, i=1); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg], #-%imm", cond, rd, rn, addr1+addr2, u=0, p=0, w=0, i=1); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg], #%imm", cond, rd, rn, addr1+addr2, u=1, p=0, w=0, i=1); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg], +%reg", cond, rd, rn, addr2, addr1=0x0, u=1, p=0, w=0, i=0); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg], -%reg", cond, rd, rn, addr2, addr1=0x0, u=0, p=0, w=0, i=0); + ldrsb.set_asm("ldr%[cond]sb %reg, [%reg], %reg", cond, rd, rn, addr2, addr1=0x0, u=1, p=0, w=0, i=0); + ldrsb.set_decoder(op=0x00, subop1=0x01, subop2=0x01, ss=0x01, hh=0x00, l=0x01); + + // ldrsb.set_cycles(3); + + //LDRSH + // Supports all adressing syntaxes in addressing mode 3 - miscellaneous load/store instructions + // (Like regular addressing modes 2, but without base plus scaled index addressing) + // Normal base plus offset or base plus index + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg]", cond, rd, rn, addr1=0, addr2=0, u=1, p=1, w=0, i=1); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg, #+%imm]", cond, rd, rn, addr1+addr2, u=1, p=1, w=0, i=1); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg, #-%imm]", cond, rd, rn, addr1+addr2, u=0, p=1, w=0, i=1); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg, #%imm]", cond, rd, rn, addr1+addr2, u=1, p=1, w=0, i=1); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg, +%reg]", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=0, i=0); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg, -%reg]", cond, rd, rn, addr2, addr1=0x0, u=0, p=1, w=0, i=0); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg, %reg]", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=0, i=0); + // Pre-indexed (base plus offset/base plus index) + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg, #+%imm]!", cond, rd, rn, addr1+addr2, u=1, p=1, w=1, i=1); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg, #-%imm]!", cond, rd, rn, addr1+addr2, u=0, p=1, w=1, i=1); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg, #%imm]!", cond, rd, rn, addr1+addr2, u=1, p=1, w=1, i=1); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg, +%reg]!", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=1, i=0); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg, -%reg]!", cond, rd, rn, addr2, addr1=0x0, u=0, p=1, w=1, i=0); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg, %reg]!", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=1, i=0); + // Post-indexed (base plus offset/base plus index) + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg], #+%imm", cond, rd, rn, addr1+addr2, u=1, p=0, w=0, i=1); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg], #-%imm", cond, rd, rn, addr1+addr2, u=0, p=0, w=0, i=1); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg], #%imm", cond, rd, rn, addr1+addr2, u=1, p=0, w=0, i=1); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg], +%reg", cond, rd, rn, addr2, addr1=0x0, u=1, p=0, w=0, i=0); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg], -%reg", cond, rd, rn, addr2, addr1=0x0, u=0, p=0, w=0, i=0); + ldrsh.set_asm("ldr%[cond]sh %reg, [%reg], %reg", cond, rd, rn, addr2, addr1=0x0, u=1, p=0, w=0, i=0); + ldrsh.set_decoder(op=0x00, subop1=0x01, subop2=0x01, ss=0x01, hh=0x01, l=0x01); + + // ldrsh.set_cycles(3); + + //STRT + //Supports only post-indexed addressing modes (addr. mode 2 - register indirect, base plus offset and base plus index) + strt1.set_asm("str%[cond]t %reg, [%reg]", cond, rd, rn, imm12=0x00, u=0x01); + strt1.set_asm("str%[cond]t %reg, [%reg], #+%imm", cond, rd, rn, imm12, u=0x01); + strt1.set_asm("str%[cond]t %reg, [%reg], #-%imm", cond, rd, rn, imm12, u=0x00); + strt1.set_asm("str%[cond]t %reg, [%reg], #%imm", cond, rd, rn, imm12, u=0x01); + strt1.set_decoder(op=0x02, p=0x00, b=0x00, w=0x01, l=0x00); + + // strt1.set_cycles(2); + + strt2.set_asm("str%[cond]t %reg, [%reg], +%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01); + strt2.set_asm("str%[cond]t %reg, [%reg], -%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x00); + strt2.set_asm("str%[cond]t %reg, [%reg], %reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01); + strt2.set_asm("str%[cond]t %reg, [%reg], +%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01); + strt2.set_asm("str%[cond]t %reg, [%reg], -%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x00); + strt2.set_asm("str%[cond]t %reg, [%reg], %reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01); + strt2.set_asm("str%[cond]t %reg, [%reg], +%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01); + strt2.set_asm("str%[cond]t %reg, [%reg], -%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x00); + strt2.set_asm("str%[cond]t %reg, [%reg], %reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01); + strt2.set_decoder(op=0x03, subop1=0x00, p=0x00, b=0x00, w=0x01, l=0x00); + + // strt2.set_cycles(2); + + //STRBT + //Suppports only post-indexed addressing modes (addr. mode 2 - register indirect, base plus offset and base plus index) + strbt1.set_asm("str%[cond]bt %reg, [%reg]", cond, rd, rn, imm12=0x00, u=0x01); + strbt1.set_asm("str%[cond]bt %reg, [%reg], #+%imm", cond, rd, rn, imm12, u=0x01); + strbt1.set_asm("str%[cond]bt %reg, [%reg], #-%imm", cond, rd, rn, imm12, u=0x00); + strbt1.set_asm("str%[cond]bt %reg, [%reg], #%imm", cond, rd, rn, imm12, u=0x01); + strbt1.set_decoder(op=0x02, p=0x00, b=0x01, w=0x01, l=0x00); + + // strbt1.set_cycles(2); + + strbt2.set_asm("str%[cond]bt %reg, [%reg], +%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01); + strbt2.set_asm("str%[cond]bt %reg, [%reg], -%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x00); + strbt2.set_asm("str%[cond]bt %reg, [%reg], %reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01); + strbt2.set_asm("str%[cond]bt %reg, [%reg], +%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01); + strbt2.set_asm("str%[cond]bt %reg, [%reg], -%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x00); + strbt2.set_asm("str%[cond]bt %reg, [%reg], %reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01); + strbt2.set_asm("str%[cond]bt %reg, [%reg], +%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01); + strbt2.set_asm("str%[cond]bt %reg, [%reg], -%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x00); + strbt2.set_asm("str%[cond]bt %reg, [%reg], %reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01); + strbt2.set_decoder(op=0x03, subop1=0x00, p=0x00, b=0x01, w=0x01, l=0x00); + + // strbt2.set_cycles(2); + + //STR + // Includes all addressing syntaxes in addressing mode 2 - load/store instructions + // Immediate offset/pre-indexed/post-indexed (Base plus offset addressing) + // Normal base plus offset/Register indirect (p=1 w=0) + str1.set_asm("str%[cond] %reg, [%reg]", cond, rd, rn, imm12=0x0, p=1, u=1, w=0); + str1.set_asm("str%[cond] %reg, [%reg, #+%imm]", cond, rd, rn, imm12, p=1, u=1, w=0); + str1.set_asm("str%[cond] %reg, [%reg, #-%imm]", cond, rd, rn, imm12, p=1, u=0, w=0); + str1.set_asm("str%[cond] %reg, [%reg, #%imm]", cond, rd, rn, imm12, p=1, u=1, w=0); + // Pre-indexed (p=1 w=1) + str1.set_asm("str%[cond] %reg, [%reg, #+%imm]!", cond, rd, rn, imm12, p=1, u=1, w=1); + str1.set_asm("str%[cond] %reg, [%reg, #-%imm]!", cond, rd, rn, imm12, p=1, u=0, w=1); + str1.set_asm("str%[cond] %reg, [%reg, #%imm]!", cond, rd, rn, imm12, p=1, u=1, w=1); + // Post-indexed (p=0 w=0) + str1.set_asm("str%[cond] %reg, [%reg], #+%imm", cond, rd, rn, imm12, u=0x01, p=0x00, w=0x00); + str1.set_asm("str%[cond] %reg, [%reg], #-%imm", cond, rd, rn, imm12, u=0x00, p=0x00, w=0x00); + str1.set_asm("str%[cond] %reg, [%reg], #%imm", cond, rd, rn, imm12, u=0x01, p=0x00, w=0x00); + str1.set_decoder(op=0x02, b=0x00, l=0x00); + + // str1.set_cycles(1); + + // Base plus (scaled) index addressing (normal/pre-indexed/post-indexed) + // Normal base plus index addressing (p=1 w=0) + str2.set_asm("str%[cond] %reg, [%reg, +%reg]", cond, rd, rn, rm, p=1, w=0, shiftamount=0, shift=0, u=1); + str2.set_asm("str%[cond] %reg, [%reg, -%reg]", cond, rd, rn, rm, p=1, w=0, shiftamount=0, shift=0, u=0); + str2.set_asm("str%[cond] %reg, [%reg, %reg]", cond, rd, rn, rm, p=1, w=0, shiftamount=0, shift=0, u=1); + str2.set_asm("str%[cond] %reg, [%reg, +%reg, %shift #%imm]", cond, rd, rn, rm, shift, shiftamount, p=1, w=0, u=1); + str2.set_asm("str%[cond] %reg, [%reg, -%reg, %shift #%imm]", cond, rd, rn, rm, shift, shiftamount, p=1, w=0, u=0); + str2.set_asm("str%[cond] %reg, [%reg, %reg, %shift #%imm]", cond, rd, rn, rm, shift, shiftamount, p=1, w=0, u=1); + str2.set_asm("str%[cond] %reg, [%reg, +%reg, rrx]", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=0, u=1); + str2.set_asm("str%[cond] %reg, [%reg, -%reg, rrx]", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=0, u=0); + str2.set_asm("str%[cond] %reg, [%reg, %reg, rrx]", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=0, u=1); + // Pre-indexed (p=1 w=1) + str2.set_asm("str%[cond] %reg, [%reg, +%reg]!", cond, rd, rn, rm, p=1, w=1, shiftamount=0, shift=0, u=1); + str2.set_asm("str%[cond] %reg, [%reg, -%reg]!", cond, rd, rn, rm, p=1, w=1, shiftamount=0, shift=0, u=0); + str2.set_asm("str%[cond] %reg, [%reg, %reg]!", cond, rd, rn, rm, p=1, w=1, shiftamount=0, shift=0, u=1); + str2.set_asm("str%[cond] %reg, [%reg, +%reg, %shift #%imm]!", cond, rd, rn, rm, shift, shiftamount, p=1, w=1, u=1); + str2.set_asm("str%[cond] %reg, [%reg, -%reg, %shift #%imm]!", cond, rd, rn, rm, shift, shiftamount, p=1, w=1, u=0); + str2.set_asm("str%[cond] %reg, [%reg, %reg, %shift #%imm]!", cond, rd, rn, rm, shift, shiftamount, p=1, w=1, u=1); + str2.set_asm("str%[cond] %reg, [%reg, +%reg, rrx]!", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=1, u=1); + str2.set_asm("str%[cond] %reg, [%reg, -%reg, rrx]!", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=1, u=0); + str2.set_asm("str%[cond] %reg, [%reg, %reg, rrx]!", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=1, u=1); + // Post-indexed (p=0 w=0) + str2.set_asm("str%[cond] %reg, [%reg], +%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01, p=0x00, w=0x00); + str2.set_asm("str%[cond] %reg, [%reg], -%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x00, p=0x00, w=0x00); + str2.set_asm("str%[cond] %reg, [%reg], %reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01, p=0x00, w=0x00); + str2.set_asm("str%[cond] %reg, [%reg], +%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01, p=0x00, w=0x00); + str2.set_asm("str%[cond] %reg, [%reg], -%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x00, p=0x00, w=0x00); + str2.set_asm("str%[cond] %reg, [%reg], %reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01, p=0x00, w=0x00); + str2.set_asm("str%[cond] %reg, [%reg], +%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01, p=0x00, w=0x00); + str2.set_asm("str%[cond] %reg, [%reg], -%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x00, p=0x00, w=0x00); + str2.set_asm("str%[cond] %reg, [%reg], %reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01, p=0x00, w=0x00); + str2.set_decoder(op=0x03, subop1=0x00, b=0x00, l=0x00); + + // str2.set_cycles(1); + + //STRB + // Includes all addressing syntaxes in addressing mode 2 - load/store instructions + // Immediate offset/pre-indexed/post-indexed (Base plus offset addressing) + // Normal base plus offset/Register indirect (p=1 w=0) + strb1.set_asm("str%[cond]b %reg, [%reg]", cond, rd, rn, imm12=0x0, p=1, u=1, w=0); + strb1.set_asm("str%[cond]b %reg, [%reg, #+%imm]", cond, rd, rn, imm12, p=1, u=1, w=0); + strb1.set_asm("str%[cond]b %reg, [%reg, #-%imm]", cond, rd, rn, imm12, p=1, u=0, w=0); + strb1.set_asm("str%[cond]b %reg, [%reg, #%imm]", cond, rd, rn, imm12, p=1, u=1, w=0); + // Pre-indexed (p=1 w=1) + strb1.set_asm("str%[cond]b %reg, [%reg, #+%imm]!", cond, rd, rn, imm12, p=1, u=1, w=1); + strb1.set_asm("str%[cond]b %reg, [%reg, #-%imm]!", cond, rd, rn, imm12, p=1, u=0, w=1); + strb1.set_asm("str%[cond]b %reg, [%reg, #%imm]!", cond, rd, rn, imm12, p=1, u=1, w=1); + // Post-indexed (p=0 w=0) + strb1.set_asm("str%[cond]b %reg, [%reg], #+%imm", cond, rd, rn, imm12, u=0x01, p=0x00, w=0x00); + strb1.set_asm("str%[cond]b %reg, [%reg], #-%imm", cond, rd, rn, imm12, u=0x00, p=0x00, w=0x00); + strb1.set_asm("str%[cond]b %reg, [%reg], #%imm", cond, rd, rn, imm12, u=0x01, p=0x00, w=0x00); + strb1.set_decoder(op=0x02, b=0x01, l=0x00); + + // strb1.set_cycles(1); + + // Base plus (scaled) index addressing (normal/pre-indexed/post-indexed) + // Normal base plus index addressing (p=1 w=0) + strb2.set_asm("str%[cond]b %reg, [%reg, +%reg]", cond, rd, rn, rm, p=1, w=0, shiftamount=0, shift=0, u=1); + strb2.set_asm("str%[cond]b %reg, [%reg, -%reg]", cond, rd, rn, rm, p=1, w=0, shiftamount=0, shift=0, u=0); + strb2.set_asm("str%[cond]b %reg, [%reg, %reg]", cond, rd, rn, rm, p=1, w=0, shiftamount=0, shift=0, u=1); + strb2.set_asm("str%[cond]b %reg, [%reg, +%reg, %shift #%imm]", cond, rd, rn, rm, shift, shiftamount, p=1, w=0, u=1); + strb2.set_asm("str%[cond]b %reg, [%reg, -%reg, %shift #%imm]", cond, rd, rn, rm, shift, shiftamount, p=1, w=0, u=0); + strb2.set_asm("str%[cond]b %reg, [%reg, %reg, %shift #%imm]", cond, rd, rn, rm, shift, shiftamount, p=1, w=0, u=1); + strb2.set_asm("str%[cond]b %reg, [%reg, +%reg, rrx]", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=0, u=1); + strb2.set_asm("str%[cond]b %reg, [%reg, -%reg, rrx]", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=0, u=0); + strb2.set_asm("str%[cond]b %reg, [%reg, %reg, rrx]", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=0, u=1); + // Pre-indexed (p=1 w=1) + strb2.set_asm("str%[cond]b %reg, [%reg, +%reg]!", cond, rd, rn, rm, p=1, w=1, shiftamount=0, shift=0, u=1); + strb2.set_asm("str%[cond]b %reg, [%reg, -%reg]!", cond, rd, rn, rm, p=1, w=1, shiftamount=0, shift=0, u=0); + strb2.set_asm("str%[cond]b %reg, [%reg, %reg]!", cond, rd, rn, rm, p=1, w=1, shiftamount=0, shift=0, u=1); + strb2.set_asm("str%[cond]b %reg, [%reg, +%reg, %shift #%imm]!", cond, rd, rn, rm, shift, shiftamount, p=1, w=1, u=1); + strb2.set_asm("str%[cond]b %reg, [%reg, -%reg, %shift #%imm]!", cond, rd, rn, rm, shift, shiftamount, p=1, w=1, u=0); + strb2.set_asm("str%[cond]b %reg, [%reg, %reg, %shift #%imm]!", cond, rd, rn, rm, shift, shiftamount, p=1, w=1, u=1); + strb2.set_asm("str%[cond]b %reg, [%reg, +%reg, rrx]!", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=1, u=1); + strb2.set_asm("str%[cond]b %reg, [%reg, -%reg, rrx]!", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=1, u=0); + strb2.set_asm("str%[cond]b %reg, [%reg, %reg, rrx]!", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, p=1, w=1, u=1); + // Post-indexed (p=0 w=0) + strb2.set_asm("str%[cond]b %reg, [%reg], +%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01, p=0x00, w=0x00); + strb2.set_asm("str%[cond]b %reg, [%reg], -%reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x00, p=0x00, w=0x00); + strb2.set_asm("str%[cond]b %reg, [%reg], %reg", cond, rd, rn, rm, shiftamount=0x00, shift=0x00, u=0x01, p=0x00, w=0x00); + strb2.set_asm("str%[cond]b %reg, [%reg], +%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01, p=0x00, w=0x00); + strb2.set_asm("str%[cond]b %reg, [%reg], -%reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x00, p=0x00, w=0x00); + strb2.set_asm("str%[cond]b %reg, [%reg], %reg, %shift #%imm", cond, rd, rn, rm, shift, shiftamount, u=0x01, p=0x00, w=0x00); + strb2.set_asm("str%[cond]b %reg, [%reg], +%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01, p=0x00, w=0x00); + strb2.set_asm("str%[cond]b %reg, [%reg], -%reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x00, p=0x00, w=0x00); + strb2.set_asm("str%[cond]b %reg, [%reg], %reg, rrx", cond, rd, rn, rm, shift=0x03, shiftamount=0x00, u=0x01, p=0x00, w=0x00); + strb2.set_decoder(op=0x03, subop1=0x00, b=0x01, l=0x00); + + // strb2.set_cycles(1); + + //STRH + // Supports all adressing syntaxes in addressing mode 3 - miscellaneous load/store instructions + // (Like regular addressing modes 2, but without base plus scaled index addressing) + // Normal base plus offset or base plus index + strh.set_asm("str%[cond]h %reg, [%reg]", cond, rd, rn, addr1=0, addr2=0, u=1, p=1, w=0, i=1); + strh.set_asm("str%[cond]h %reg, [%reg, #+%imm]", cond, rd, rn, addr1+addr2, u=1, p=1, w=0, i=1); + strh.set_asm("str%[cond]h %reg, [%reg, #-%imm]", cond, rd, rn, addr1+addr2, u=0, p=1, w=0, i=1); + strh.set_asm("str%[cond]h %reg, [%reg, #%imm]", cond, rd, rn, addr1+addr2, u=1, p=1, w=0, i=1); + strh.set_asm("str%[cond]h %reg, [%reg, +%reg]", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=0, i=0); + strh.set_asm("str%[cond]h %reg, [%reg, -%reg]", cond, rd, rn, addr2, addr1=0x0, u=0, p=1, w=0, i=0); + strh.set_asm("str%[cond]h %reg, [%reg, %reg]", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=0, i=0); + // Pre-indexed (base plus offset/base plus index) + strh.set_asm("str%[cond]h %reg, [%reg, #+%imm]!", cond, rd, rn, addr1+addr2, u=1, p=1, w=1, i=1); + strh.set_asm("str%[cond]h %reg, [%reg, #-%imm]!", cond, rd, rn, addr1+addr2, u=0, p=1, w=1, i=1); + strh.set_asm("str%[cond]h %reg, [%reg, #%imm]!", cond, rd, rn, addr1+addr2, u=1, p=1, w=1, i=1); + strh.set_asm("str%[cond]h %reg, [%reg, +%reg]!", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=1, i=0); + strh.set_asm("str%[cond]h %reg, [%reg, -%reg]!", cond, rd, rn, addr2, addr1=0x0, u=0, p=1, w=1, i=0); + strh.set_asm("str%[cond]h %reg, [%reg, %reg]!", cond, rd, rn, addr2, addr1=0x0, u=1, p=1, w=1, i=0); + // Post-indexed (base plus offset/base plus index) + strh.set_asm("str%[cond]h %reg, [%reg], #+%imm", cond, rd, rn, addr1+addr2, u=1, p=0, w=0, i=1); + strh.set_asm("str%[cond]h %reg, [%reg], #-%imm", cond, rd, rn, addr1+addr2, u=0, p=0, w=0, i=1); + strh.set_asm("str%[cond]h %reg, [%reg], #%imm", cond, rd, rn, addr1+addr2, u=1, p=0, w=0, i=1); + strh.set_asm("str%[cond]h %reg, [%reg], +%reg", cond, rd, rn, addr2, addr1=0x0, u=1, p=0, w=0, i=0); + strh.set_asm("str%[cond]h %reg, [%reg], -%reg", cond, rd, rn, addr2, addr1=0x0, u=0, p=0, w=0, i=0); + strh.set_asm("str%[cond]h %reg, [%reg], %reg", cond, rd, rn, addr2, addr1=0x0, u=1, p=0, w=0, i=0); + strh.set_decoder(op=0x00, subop1=0x01, subop2=0x01, ss=0x00, hh=0x01, l=0x00); + + // strh.set_cycles(1); + + /** * Multiple data transfer instructions suffix: * + ** Stack Type | Suffix + ** Full ascending *FA / STMIB LDMDA + ** Empty ascending *EA / STMIA LDMDB + ** Full descending *FD / STMDB LDMIA + ** Empty descending *ED / STMDA LDMIB + ** -- + ** IB - Increment Before * IA - Increment After + ** DB - Decrement Before * DA - Decrement After + */ + +// ac_format Type_LSM = "%cond:4 %op:3 %p:1 %u:1 %r:1 %w:1 %l:1 %rn:4 %rlist:16"; + ldm.set_asm("ldm%cond%lstype %reg, {%reg...(dorlist)}", cond, p+u, rn, rlist, r=0,w=0); + ldm.set_asm("ldm%cond%lstype %reg!, {%reg...(dorlist)}", cond, p+u, rn, rlist, r=0, w=1); + ldm.set_asm("ldm%cond%lstype %reg, {%reg...(dorlist)}^", cond, p+u, rn, rlist, r=1,w=0); + ldm.set_asm("ldm%cond%lstype %reg!, {%reg...(dorlist)}^", cond, p+u, rn, rlist, r=1,w=1); + ldm.set_asm("ldm%cond%mlstype %reg, {%reg...(dorlist)}", cond, p+u, rn, rlist, r=0, w=0); + ldm.set_asm("ldm%cond%mlstype %reg!, {%reg...(dorlist)}", cond, p+u, rn, rlist,r=0, w=1); + ldm.set_asm("ldm%cond%mlstype %reg, {%reg...(dorlist)}^", cond, p+u, rn, rlist, r=1,w=0); + ldm.set_asm("ldm%cond%mlstype %reg!, {%reg...(dorlist)}^", cond, p+u, rn, rlist, r=1,w=1); + ldm.set_decoder(op=0x04, l=0x01); + + // ldm.set_cycles(2); + + stm.set_asm("stm%cond%sstype %reg, {%reg...(dorlist)}", cond, p+u, rn, rlist, r=0, w=0); + stm.set_asm("stm%cond%sstype %reg!, {%reg...(dorlist)}", cond, p+u, rn, rlist, r=0, w=1); + stm.set_asm("stm%cond%sstype %reg, {%reg...(dorlist)}^", cond, p+u, rn, rlist, r=1, w=0); + stm.set_asm("stm%cond%sstype %reg!, {%reg...(dorlist)}^", cond, p+u, rn, rlist, r=1, w=1); + stm.set_asm("stm%cond%mlstype %reg, {%reg...(dorlist)}", cond, p+u, rn, rlist, r=0, w=0); + stm.set_asm("stm%cond%mlstype %reg!, {%reg...(dorlist)}", cond, p+u, rn, rlist, r=0, w=1); + stm.set_asm("stm%cond%mlstype %reg, {%reg...(dorlist)}^", cond, p+u, rn, rlist, r=1, w=0); + stm.set_asm("stm%cond%mlstype %reg!, {%reg...(dorlist)}^", cond, p+u, rn, rlist, r=1, w=1); + stm.set_decoder(op=0x04, l=0x00); + + // stm.set_cycles(2); + + /*******************************/ + /* Coprocessor instructions */ + /*******************************/ + + /* Coprocessor instructions will NOT be implemented in this model ! */ + +// cdp.set_asm(""); + cdp.set_decoder(op=0x07, subop1=0x00, subop3=0x00); + +// mcr.set_asm(""); + mcr.set_decoder(op=0x07, subop1=0x01, subop3=0x00, l=0x00); + +// mrc.set_asm(""); + mrc.set_decoder(op=0x07, subop1=0x01, subop3=0x00, l=0x01); + +// ldc.set_asm(""); + ldc.set_decoder(op=0x06, l=0x01); + +// stc.set_asm(""); + stc.set_decoder(op=0x06, l=0x00); + + + /************************/ + /* Special instructions */ + /************************/ + + bkpt.set_asm("bkpt %imm", immediate+rm, cond=0xE); + bkpt.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x09, func2=0x03, s=0x00, cond=0x0E); + + swi.set_asm("swi%[cond] %imm", cond, swinumber); + swi.set_asm("swi%[cond] #%imm", cond, swinumber); + swi.set_decoder(op=0x07, subop3=0x01); + + clz.set_asm("clz%[cond] %reg, %reg", cond, rd, rm, one1=0x0F, one3=0x0F); + clz.set_decoder(op=0x00, subop1=0x01, subop2=0x00, func1=0x0B, func2=0x00, s=0x00); + // clz.set_cycles(1); + + mrs.set_asm("mrs%[cond] %reg, %psr", cond, rd, r); + mrs.set_decoder(op=0x00, subop1=0x00, subop2=0x00, func11=0x02, func12=0x00, rm=0x00, fieldmask=0xF); + + /* MSR will not be implemented in this model. */ + +// msr1.set_asm(""); + msr1.set_decoder(op=0x00, subop1=0x00, subop2=0x00, func11=0x02, func12=0x02, zero3=0x00, func2=0x00); + + msr2.set_asm("msr%[cond] APSR_nzcv, #%imm", cond, r=0, fieldmask=8, rotate=2, imm8); + msr2.set_decoder(op=0x01, func11=0x02, func12=0x02, one2=0x0f); + + + /************************/ + /* DSP instructions */ + /************************/ + + /* DSP instructions will not be implemented in this model. */ + +// ldrd.set_asm(""); + ldrd.set_decoder(op=0x00, subop1=0x01, subop2=0x01, ss=0x01, hh=0x00, l=0x00); + + // ldrd.set_cycles(2); + +// strd.set_asm(""); + strd.set_decoder(op=0x00, subop1=0x01, subop2=0x01, ss=0x01, hh=0x01, l=0x00); + + + /************************/ + /* Pseudo instructions */ + /************************/ + + pseudo_instr ("nop"){ + "mov r0, r0"; + } + /*pseudo_instr ("adr %reg, %addrR8b") { + "add %0, r15, %1"; + } + pseudo_instr ("ldr %reg, %exprR8b") { + "ldr %0, [r15, #%1]"; + }*/ + + }; +}; + diff --git a/pdl/arm/arm_isa.cpp b/pdl/arm/arm_isa.cpp new file mode 100644 index 0000000..81e8790 --- /dev/null +++ b/pdl/arm/arm_isa.cpp @@ -0,0 +1,2700 @@ +/** + * @file arm_isa.cpp + * @author Danilo Marcolin Caravana + * Rafael Auler + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Apr 2012 + * + * @brief The ArchC ARMv5e functional model. + * + * @attention Copyright (C) 2002-2012 --- The ArchC Team + * + */ + +#include "arm_isa.H" +#include "arm_isa_init.cpp" +#include "arm_bhv_macros.H" +#include // define types uint32_t, etc + +using namespace arm_parms; + +#define DEFAULT_STACK_SIZE (512 * 1024) +static int processors_started = 0; + +//If you want debug information for this model, uncomment next line +//#define DEBUG_MODEL + +//If you want the processor to operate in system model instead +//of user model, uncomment next line +//#define SYSTEM_MODEL + +//This is a switch to turn unpredictable behavior for some +//instructions to be silently ignored. This is necessary for +//some gcc generated ARM user level code. +#define FORGIVE_UNPREDICTABLE + +// If FORGIVE_UNPREDITABLE is turned on, necessarily turns off +// SYSTEM_MODEL, since the system model cannot work with this flag. +#ifdef FORGIVE_UNPREDITABLE +#undef SYSTEM_MODEL +#endif + +#ifdef DEBUG_MODEL +#include + +static inline int dprintf(const char *format, ...) { + int ret; + va_list args; + va_start(args, format); + ret = vfprintf(ac_err, format, args); + va_end(args); + return ret; +} +#else +inline void dprintf(const char *format, ...) {} +#endif + +//! User defined macros to reference registers +#define LR 14 // link return +#define PC 15 // program counter + +#ifdef SYSTEM_MODEL +#define RB_write bypass_write +#define RB_read bypass_read +#else +#define RB_write RB.write +#define RB_read RB.read +#endif + +#ifdef SLEEP_AWAKE_MODE +/*********************************************************************************/ +/* SLEEP / AWAKE mode control */ +/* INTR_REG may store 1 (AWAKE MODE) or 0 (SLEEP MODE) */ +/* if intr_reg == 0, the simulator will be suspended until it receives a */ +/* interruption 1 */ +/*********************************************************************************/ +#define test_sleep() { if (intr_reg.read() == 0) ac_wait(); } +#else +#define test_sleep() {} +#endif + +void ac_behavior( begin ) { +#ifdef SYSTEM_MODEL + arm_proc_mode.mode = processor_mode::SUPERVISOR_MODE; + arm_proc_mode.thumb = false; + arm_proc_mode.fiq = false; + arm_proc_mode.irq = false; + ac_pc = 0; +#endif + // Initializing flags and model variables + flags.Z = false; + flags.C = false; + flags.N = false; + flags.V = false; + flags.Q = false; + flags.T = false; + execute = false; + dpi_shiftop.entire = 0; + dpi_shiftopcarry = false; + ls_address.entire = 0; + lsm_startaddress.entire = 0; + lsm_endaddress.entire = 0; + OP1.entire = 0; + OP2.entire = 0; + + RB.write(13, AC_RAM_END - 1024 - processors_started++ * DEFAULT_STACK_SIZE); +} + +//!Generic instruction behavior method. +void ac_behavior( instruction ) { + + test_sleep(); + + dprintf("-------------------- PC=%#x -------------------- %lld\n", (uint32_t)ac_pc, ac_instr_counter); + + // Conditionally executes instruction based on COND field, common to all ARM instructions. + execute = false; + + switch(cond) { + case 0: if (flags.Z == true) execute = true; break; + case 1: if (flags.Z == false) execute = true; break; + case 2: if (flags.C == true) execute = true; break; + case 3: if (flags.C == false) execute = true; break; + case 4: if (flags.N == true) execute = true; break; + case 5: if (flags.N == false) execute = true; break; + case 6: if (flags.V == true) execute = true; break; + case 7: if (flags.V == false) execute = true; break; + case 8: if ((flags.C == true)&&(flags.Z == false)) execute = true; break; + case 9: if ((flags.C == false)||(flags.Z == true)) execute = true; break; + case 10: if (flags.N == flags.V) execute = true; break; + case 11: if (flags.N != flags.V) execute = true; break; + case 12: if ((flags.Z == false)&&(flags.N == flags.V)) execute = true; break; + case 13: if ((flags.Z == true)||(flags.N != flags.V)) execute = true; break; + case 14: execute = true; break; + default: execute = false; + } + + // PC increment + ac_pc += 4; + RB_write(PC, ac_pc); + + if(!execute) { + dprintf("cond=0x%X\n", cond); + dprintf("Instruction will not be executed due to condition flags.\n"); + ac_annul(); + } +} + +// Instruction Format behavior methods. + +//!DPI1 - Second operand is register with imm shift +void ac_behavior( Type_DPI1 ) { + + arm_isa::reg_t RM2; + + // Special case: rm = 15 + if (rm == 15) { + // PC is already incremented by four, so only add 4 again (not 8) + RM2.entire = RB_read(rm) + 4; + } + else RM2.entire = RB_read(rm); + + switch(shift) { + case 0: // Logical shift left + if ((shiftamount >= 0) && (shiftamount <= 31)) { + if (shiftamount == 0) { + dpi_shiftop.entire = RM2.entire; + dpi_shiftopcarry = flags.C; + } else { + dpi_shiftop.entire = RM2.entire << shiftamount; + dpi_shiftopcarry = getBit(RM2.entire, 32 - shiftamount); + } + } + break; + case 1: // Logical shift right + if ((shiftamount >= 0) && (shiftamount <= 31)) { + if (shiftamount == 0) { + dpi_shiftop.entire = 0; + dpi_shiftopcarry = getBit(RM2.entire, 31); + } else { + dpi_shiftop.entire = ((uint32_t) RM2.entire) >> shiftamount; + dpi_shiftopcarry = getBit(RM2.entire, shiftamount - 1); + } + } + break; + case 2: // Arithmetic shift right + if ((shiftamount >= 0) && (shiftamount <= 31)) { + if (shiftamount == 0) { + if (!isBitSet(RM2.entire, 31)) { + dpi_shiftop.entire = 0; + dpi_shiftopcarry = getBit(RM2.entire, 31); + } else { + dpi_shiftop.entire = 0xFFFFFFFF; + dpi_shiftopcarry = getBit(RM2.entire, 31); + } + } else { + dpi_shiftop.entire = ((int32_t) RM2.entire) >> shiftamount; + dpi_shiftopcarry = getBit(RM2.entire, shiftamount - 1); + } + } + break; + default: // Rotate right + if ((shiftamount >= 0) && (shiftamount <= 31)) { + if (shiftamount == 0) { //Rotate right with extend + dpi_shiftopcarry = getBit(RM2.entire, 0); + dpi_shiftop.entire = (((uint32_t)RM2.entire) >> 1); + if (flags.C) setBit(dpi_shiftop.entire, 31); + } else { + dpi_shiftop.entire = (RotateRight(shiftamount, RM2)).entire; + dpi_shiftopcarry = getBit(RM2.entire, shiftamount - 1); + } + } + } +} + +//!DPI2 - Second operand is shifted (shift amount given by third register operand) +void ac_behavior( Type_DPI2 ) { + + int rs40; + arm_isa::reg_t RS2, RM2; + + // Special case: r* = 15 + if ((rd == 15)||(rm == 15)||(rn == 15)||(rs == 15)) { + printf("Register 15 cannot be used in this instruction.\n"); + ac_annul(); + } + + RM2.entire = RB_read(rm); + RS2.entire = RB_read(rs); + rs40 = ((uint32_t)RS2.entire) & 0x0000000F; + + switch(shift){ + case 0: // Logical shift left + if (RS2.byte[0] == 0) { + dpi_shiftop.entire = RM2.entire; + dpi_shiftopcarry = flags.C; + } + else if (((uint8_t)RS2.byte[0]) < 32) { + dpi_shiftop.entire = RM2.entire << (uint8_t)RS2.byte[0]; + dpi_shiftopcarry = getBit(RM2.entire, 32 - ((uint8_t)RS2.byte[0])); + } + else if (RS2.byte[0] == 32) { + dpi_shiftop.entire = 0; + dpi_shiftopcarry = getBit(RM2.entire, 0); + } + else { // rs > 32 + dpi_shiftop.entire = 0; + dpi_shiftopcarry = 0; + } + break; + case 1: // Logical shift right + if (RS2.byte[0] == 0) { + dpi_shiftop.entire = RM2.entire; + dpi_shiftopcarry = flags.C; + } + else if (((uint8_t)RS2.byte[0]) < 32) { + dpi_shiftop.entire = ((uint32_t) RM2.entire) >> ((uint8_t)RS2.byte[0]); + dpi_shiftopcarry = getBit(RM2.entire, (uint8_t)RS2.byte[0] - 1); + } + else if (RS2.byte[0] == 32) { + dpi_shiftop.entire = 0; + dpi_shiftopcarry = getBit(RM2.entire, 31); + } + else { // rs > 32 + dpi_shiftop.entire = 0; + dpi_shiftopcarry = 0; + } + break; + case 2: // Arithmetical shift right + if (RS2.byte[0] == 0) { + dpi_shiftop.entire = RM2.entire; + dpi_shiftopcarry = flags.C; + } + else if (((uint8_t)RS2.byte[0]) < 32) { + dpi_shiftop.entire = ((int32_t) RM2.entire) >> ((uint8_t)RS2.byte[0]); + dpi_shiftopcarry = getBit(RM2.entire, ((uint8_t)RS2.byte[0]) - 1); + } else { // rs >= 32 + if (!isBitSet(RM2.entire, 31)) { + dpi_shiftop.entire = 0; + dpi_shiftopcarry = getBit(RM2.entire, 31); + } + else { // rm_31 == 1 + dpi_shiftop.entire = 0xFFFFFFFF; + dpi_shiftopcarry = getBit(RM2.entire, 31); + } + } + break; + default: // Rotate right + if (RS2.byte[0] == 0) { + dpi_shiftop.entire = RM2.entire; + dpi_shiftopcarry = flags.C; + } + else if (rs40 == 0) { + dpi_shiftop.entire = RM2.entire; + dpi_shiftopcarry = getBit(RM2.entire, 31); + } + else { // rs40 > 0 + dpi_shiftop.entire = (RotateRight(rs40, RM2)).entire; + dpi_shiftopcarry = getBit(RM2.entire, rs40 - 1); + } + } +} + +//!DPI3 - Second operand is immediate shifted by another imm +void ac_behavior( Type_DPI3 ){ + int32_t tmp; + tmp = (uint32_t)imm8; + dpi_shiftop.entire = (((uint32_t)tmp) >> (2 * rotate)) | (((uint32_t)tmp) << (32 - (2 * rotate))); + + if (rotate == 0) + dpi_shiftopcarry = flags.C; + else + dpi_shiftopcarry = getBit(dpi_shiftop.entire, 31); +} + +void ac_behavior( Type_BBL ) { + // no special actions necessary +} +void ac_behavior( Type_BBLT ) { + // no special actions necessary +} +void ac_behavior( Type_MBXBLX ) { + // no special actions necessary +} + +//!MULT1 - 32-bit result multiplication +void ac_behavior( Type_MULT1 ) { + // no special actions necessary +} + +//!MULT2 - 64-bit result multiplication +void ac_behavior( Type_MULT2 ) { + // no special actions necessary +} + +//!LSI - Load Store Immediate Offset/Index +void ac_behavior( Type_LSI ) { + + arm_isa::reg_t RN2; + RN2.entire = RB_read(rn); + + ls_address.entire = 0; + + if((p == 1)&&(w == 0)) { // immediate pre-indexed without writeback + // Special case: Rn = PC + if (rn == PC) + ls_address.entire = 4; + + if(u == 1) { + ls_address.entire += RN2.entire + (uint32_t) imm12; + } else { + ls_address.entire += RN2.entire - (uint32_t) imm12; + } + } + + else if((p == 1)&&(w == 1)) { // immediate pre-indexed with writeback + // Special case: Rn = PC + if (rn == PC) { + printf("Unpredictable LSI instruction result (Can't writeback to PC, Rn = PC)\n"); + ac_annul(); + return; + } + // Special case: Rn = Rd + if (rn == rd) { + printf("Unpredictable LSI instruction result (Can't writeback to loaded register, Rn = Rd)\n"); + ac_annul(); + return; + } + + if(u == 1) { + ls_address.entire = RN2.entire + (uint32_t) imm12; + } else { + ls_address.entire = RN2.entire - (uint32_t) imm12; + } + RB_write(rn,ls_address.entire); + } + + else if((p == 0)&&(w == 0)) { // immediate post-indexed (writeback) + // Special case: Rn = PC + if (rn == PC) { + printf("Unpredictable LSI instruction result (Can't writeback to PC, Rn = PC)\n"); + ac_annul(); + return; + } + // Special case Rn = Rd + if (rn == rd) { + printf("Unpredictable LSI instruction result (Can't writeback to loaded register, Rn = Rd)\n"); + ac_annul(); + return; + } + + ls_address.entire = RN2.entire; + if(u == 1) { + //checar se imm12 soma direto + RB_write(rn, ls_address.entire + (uint32_t) imm12); + } else { + RB_write(rn, ls_address.entire - (uint32_t) imm12); + } + } + /* FIXME: Check word alignment (Rd = PC) Address[1:0] = 0b00 */ + +} + +//!LSR - Scaled Register Offset/Index +void ac_behavior( Type_LSR ) { + + arm_isa::reg_t RM2, RN2, index, tmp; + + RM2.entire = RB_read(rm); + RN2.entire = RB_read(rn); + ls_address.entire = 0; + + if ((p == 1)&&(w == 0)) { // offset + // Special case: PC + if(rn == PC) + ls_address.entire = 4; + + if(rm == PC) { + printf("Unpredictable LSR instruction result (Illegal usage of PC, Rm = PC)\n"); + return; + } + + switch(shift){ + case 0: + if(shiftamount == 0) { // Register + index.entire = RM2.entire; + } else { // Scalled logical shift left + index.entire = RM2.entire << shiftamount; + } + break; + case 1: // logical shift right + if(shiftamount == 0) index.entire = 0; + else index.entire = ((uint32_t) RM2.entire) >> shiftamount; + break; + case 2: // arithmetic shift right + if(shiftamount == 0) { + if (isBitSet(RM2.entire, 31)) index.entire = 0xFFFFFFFF; + else index.entire = 0; + } else index.entire = ((int32_t) RM2.entire) >> shiftamount; + break; + default: + if(shiftamount == 0) { // RRX + tmp.entire = 0; + if(flags.C) setBit(tmp.entire, 31); + index.entire = tmp.entire | (((uint32_t) RM2.entire) >> 1); + } else { // rotate right + index.entire = (RotateRight(shiftamount, RM2)).entire; + } + } + + if(u == 1) { + ls_address.entire += (RN2.entire + index.entire); + } else { + ls_address.entire += (RN2.entire - index.entire); + } + } + + else if((p == 1)&&(w == 1)) { // pre-indexed + // Special case: Rn = PC + if (rn == PC) { + printf("Unpredictable LSR instruction result (Can't writeback to PC, Rn = PC)\n"); + ac_annul(); + return; + } + // Special case Rn = Rd + if (rn == rd) { + printf("Unpredictable LSR instruction result (Can't writeback to loaded register, Rn = Rd)\n"); + ac_annul(); + return; + } + // Special case Rm = PC + if (rm == PC) { + printf("Unpredictable LSR instruction result (Illegal usage of PC, Rm = PC)\n"); + ac_annul(); + return; + } + // Special case Rn = Rm + if (rn == rm) { + printf("Unpredictable LSR instruction result (Can't use the same register for Rn and Rm\n"); + ac_annul(); + return; + } + + switch(shift){ + case 0: + if(shiftamount == 0) { // Register + index.entire = RM2.entire; + } else { // Scaled logical shift left + index.entire = RM2.entire << shiftamount; + } + break; + case 1: // logical shift right + if(shiftamount == 0) index.entire = 0; + else index.entire = ((uint32_t) RM2.entire) >> shiftamount; + break; + case 2: // arithmetic shift right + if(shiftamount == 0) { + if (isBitSet(RM2.entire,31)) + index.entire = 0xFFFFFFFF; + else + index.entire = 0; + } else index.entire = ((int32_t) RM2.entire) >> shiftamount; + break; + default: + if(shiftamount == 0) { // RRX + tmp.entire = 0; + if (flags.C) setBit(tmp.entire,31); + index.entire = tmp.entire | (((uint32_t) RM2.entire) >> 1); + } else { // rotate right + index.entire = (RotateRight(shiftamount, RM2)).entire; + } + } + + if(u == 1) { + ls_address.entire = RN2.entire + index.entire; + } else { + ls_address.entire = RN2.entire - index.entire; + } + + RB_write(rn, ls_address.entire); + } + + else if((p == 0)&&(w == 0)) { // post-indexed + // Special case: Rn = PC + if (rn == PC) { + printf("Unpredictable LSR instruction result (Can't writeback to PC, Rn = PC)\n"); + ac_annul(); + return; + } + // Special case Rn = Rd + if (rn == rd) { + printf("Unpredictable LSR instruction result (Can't writeback to loaded register, Rn = Rd)\n"); + ac_annul(); + return; + } + // Special case Rm = PC + if (rm == PC) { + printf("Unpredictable LSR instruction result (Illegal usage of PC, Rm = PC)\n"); + ac_annul(); + return; + } + // Special case Rn = Rm + if (rn == rm) { + printf("Unpredictable LSR instruction result (Can't use the same register for Rn and Rm\n"); + ac_annul(); + return; + } + + ls_address.entire = RN2.entire; + + switch(shift) { + case 0: + if(shiftamount == 0) { // Register + index.entire = RM2.entire; + } else { // Scaled logical shift left + index.entire = RM2.entire << shiftamount; + } + break; + case 1: // logical shift right + if(shiftamount == 0) index.entire = 0; + else index.entire = ((uint32_t) RM2.entire) >> shiftamount; + break; + case 2: // arithmetic shift right + if(shiftamount == 0) { + if (isBitSet(RM2.entire, 31)) + index.entire = 0xFFFFFFFF; + else + index.entire = 0; + } else index.entire = ((int32_t) RM2.entire) >> shiftamount; + break; + default: + if(shiftamount == 0) { // RRX + tmp.entire = 0; + if(flags.C) setBit(tmp.entire, 31); + index.entire = tmp.entire | (((uint32_t) RM2.entire) >> 1); + } else { // rotate right + index.entire = (RotateRight(shiftamount, RM2)).entire; + } + } + + if(u == 1) { + RB_write(rn, RN2.entire + index.entire); + } else { + RB_write(rn, RN2.entire - index.entire); + } + } +} + +//!LSE - Load Store HalfWord +void ac_behavior( Type_LSE ){ + + int32_t off8; + arm_isa::reg_t RM2, RN2; + + // Special cases handling + if((p == 0)&&(w == 1)) { + printf("Unpredictable LSE instruction result"); + ac_annul(); + return; + } + if((ss == 0)&&(hh == 0)) { + printf("Decoding error: this is not a LSE instruction"); + ac_annul(); + return; + } + if((ss == 1)&&(l == 0)) + dprintf("Special DSP\n"); + // FIXME: Test LDRD and STRD second registers in case of writeback + + RN2.entire = RB_read(rn); + + // nos LSE's que usam registrador, o campo addr2 armazena Rm + RM2.entire = RB_read(addr2); + off8 = ((uint32_t)(addr1 << 4) | addr2); + ls_address.entire = 0; + + if(p == 1) { // offset ou pre-indexed + if((i == 1)&&(w == 0)) { // immediate offset + if(rn == PC) + ls_address.entire = 4; + if(u == 1) { + ls_address.entire += (RN2.entire + off8); + } else { + ls_address.entire += (RN2.entire - off8); + } + } + + else if((i == 0)&&(w == 0)) { // register offset + // Special case Rm = PC + if (addr2 == PC) { + printf("Unpredictable LSE instruction result (Illegal usage of PC, Rm = PC)\n"); + ac_annul(); + return; + } + + if(rn == PC) + ls_address.entire = 4; + + if(u == 1) { + ls_address.entire += (RN2.entire + RM2.entire); + } else { + ls_address.entire += (RN2.entire - RM2.entire); + } + } + + else if ((i == 1)&&(w == 1)) { // immediate pre-indexed + // Special case: Rn = PC + if (rn == PC) { + printf("Unpredictable LSE instruction result (Can't writeback to PC, Rn = PC)\n"); + ac_annul(); + return; + } + // Special case Rn = Rd + if (rn == rd) { + printf("Unpredictable LSE instruction result (Can't writeback to loaded register, Rn = Rd)\n"); + ac_annul(); + return; + } + + if(u == 1) { + ls_address.entire = (RN2.entire + off8); + } else { + ls_address.entire = (RN2.entire - off8); + } + + RB_write(rn, ls_address.entire); + } + + else { // i == 0 && w == 1: register pre-indexed + // Special case: Rn = PC + if (rn == PC) { + printf("Unpredictable LSE instruction result (Can't writeback to PC, Rn = PC)\n"); + ac_annul(); + return; + } + // Special case Rn = Rd + if (rn == rd) { + printf("Unpredictable LSE instruction result (Can't writeback to loaded register, Rn = Rd)\n"); + ac_annul(); + return; + } + // Special case Rm = PC + if (addr2 == PC) { + printf("Unpredictable LSE instruction result (Illegal usage of PC, Rm = PC)\n"); + ac_annul(); + return; + } + // Special case Rn = Rm + if (rn == addr2) { + printf("Unpredictable LSE instruction result (Can't use the same register for Rn and Rm\n"); + ac_annul(); + return; + } + + if(u == 1) { + ls_address.entire = (RN2.entire + RM2.entire); + } else { + ls_address.entire = (RN2.entire - RM2.entire); + } + + RB_write(rn, ls_address.entire); + } + + } else { // p == 0: post-indexed + if((i == 1)&&(w == 0)) { // immediate post-indexed + if(rn == PC) { + printf("Unpredictable LSE instruction result"); + ac_annul(); + return; + } + + ls_address.entire = RN2.entire; + if(u == 1) { + RB_write(rn, RN2.entire + off8); + } else { + RB_write(rn, RN2.entire - off8); + } + } + else if((i == 0)&&(w == 0)) { // register post-indexed + // Special case: Rn = PC + if (rn == PC) { + printf("Unpredictable LSE instruction result (Can't writeback to PC, Rn = PC)\n"); + ac_annul(); + return; + } + // Special case Rn = Rd + if (rn == rd) { + printf("Unpredictable LSE instruction result (Can't writeback to loaded register, Rn = Rd)\n"); + ac_annul(); + return; + } + // Special case Rm = PC + if (addr2 == PC) { + printf("Unpredictable LSE instruction result (Illegal usage of PC, Rm = PC)\n"); + ac_annul(); + return; + } + // Special case Rn = Rm + if (rn == addr2) { + printf("Unpredictable LSE instruction result (Can't use the same register for Rn and Rm\n"); + ac_annul(); + return; + } + + ls_address.entire = RN2.entire; + if(u == 1) { + RB_write(rn, RN2.entire + RM2.entire); + } else { + RB_write(rn, RN2.entire - RM2.entire); + } + } + } +} + +//!LSM - Load Store Multiple +void ac_behavior( Type_LSM ){ + + arm_isa::reg_t RN2; + int setbits; + + // Put registers list in a variable capable of addressing individual bits + arm_isa::reg_t registerList; + registerList.entire = (uint32_t) rlist; + + // Special case - empty list + if (registerList.entire == 0) { + printf("Unpredictable LSM instruction result (No register specified)\n"); + ac_annul(); + return; + } + + RN2.entire = RB_read(rn); + setbits = LSM_CountSetBits(registerList); + + // Special case Rn in Rlist + if((w == 1)&&(isBitSet(rlist,rn))) { + lsm_oldrn.entire = RB_read(rn); + } + + if((p == 0)&&(u == 1)) { // increment after + lsm_startaddress.entire = RN2.entire; + lsm_endaddress.entire = RN2.entire + (setbits * 4) - 4; + if(w == 1) RN2.entire += (setbits * 4); + } + else if((p == 1)&&(u == 1)) { // increment before + lsm_startaddress.entire = RN2.entire + 4; + lsm_endaddress.entire = RN2.entire + (setbits * 4); + if(w == 1) RN2.entire += (setbits * 4); + } + else if((p == 0)&&(u == 0)) { // decrement after + lsm_startaddress.entire = RN2.entire - (setbits * 4) + 4; + lsm_endaddress.entire = RN2.entire; + if(w == 1) RN2.entire -= (setbits * 4); + } + else { // decrement before + lsm_startaddress.entire = RN2.entire - (setbits * 4); + lsm_endaddress.entire = RN2.entire - 4; + if(w == 1) RN2.entire -= (setbits * 4); + } + + RB_write(rn,RN2.entire); +} + +void ac_behavior( Type_CDP ){ + // no special actions necessary +} +void ac_behavior( Type_CRT ){ + // no special actions necessary +} +void ac_behavior( Type_CLS ){ + // no special actions necessary +} +void ac_behavior( Type_MBKPT ){ + // no special actions necessary +} +void ac_behavior( Type_MSWI ){ + // no special actions necessary +} +void ac_behavior( Type_MCLZ ){ + // no special actions necessary +} +void ac_behavior( Type_MMSR1 ){ + // no special actions necessary +} +void ac_behavior( Type_MMSR2 ){ + // no special actions necessary +} + +void ac_behavior( Type_DSPSM ){ + + arm_isa::reg_t RM2, RS2; + + RM2.entire = RB_read(rm); + RS2.entire = RB_read(rs); + + // Special cases + if((drd == PC)||(drn == PC)||(rm == PC)||(rs == PC)) { + printf("Unpredictable SMLA instruction result\n"); + return; + } + + if(xx == 0) + OP1.entire = SignExtend(RM2.entire, 16); + else + OP1.entire = SignExtend((RM2.entire >> 16), 16); + + if(yy == 0) + OP2.entire = SignExtend(RS2.entire, 16); + else + OP2.entire = SignExtend((RS2.entire >> 16), 16); +} + + +//! Behavior Methods + +//------------------------------------------------------ +void arm_isa::ADC(int rd, int rn, bool s) { + + arm_isa::reg_t RD2, RN2; + arm_isa::r64bit_t soma; + + dprintf("Instruction: ADC\n"); + RN2.entire = RB_read(rn); + if(rn == PC) RN2.entire += 4; + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n Carry=%d\n", RN2.entire,dpi_shiftop.entire,flags.C); + soma.hilo = (uint64_t)(uint32_t)RN2.entire + (uint64_t)(uint32_t)dpi_shiftop.entire; + if (flags.C) soma.hilo++; + RD2.entire = soma.reg[0]; + RB_write(rd, RD2.entire); + if ((s == 1)&&(rd == PC)) { +#ifndef FORGIVE_UNPREDICTABLE + printf("Unpredictable ADC instruction result\n"); + return; +#endif + } else { + if (s == 1) { + flags.N = getBit(RD2.entire,31); + flags.Z = ((RD2.entire == 0) ? true : false); + flags.C = ((soma.reg[1] != 0) ? true : false); + flags.V = (((getBit(RN2.entire,31) && getBit(dpi_shiftop.entire,31) && (!getBit(RD2.entire,31))) || + ((!getBit(RN2.entire,31)) && (!getBit(dpi_shiftop.entire,31)) && getBit(RD2.entire,31))) ? true : false); + } + } + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n", flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::ADD(int rd, int rn, bool s) { + + arm_isa::reg_t RD2, RN2; + arm_isa::r64bit_t soma; + + dprintf("Instruction: ADD\n"); + RN2.entire = RB_read(rn); + if(rn == PC) RN2.entire += 4; + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n", RN2.entire,dpi_shiftop.entire); + soma.hilo = (uint64_t)(uint32_t)RN2.entire + (uint64_t)(uint32_t)dpi_shiftop.entire; + RD2.entire = soma.reg[0]; + RB_write(rd, RD2.entire); + if ((s == 1)&&(rd == PC)) { +#ifndef FORGIVE_UNPREDICTABLE + if (arm_proc_mode.mode == arm_isa::processor_mode::USER_MODE || + arm_proc_mode.mode == arm_isa::processor_mode::SYSTEM_MODE) { + printf("Unpredictable ADD instruction result\n"); + return; + } + SPSRtoCPSR(); +#endif + } else { + if (s == 1) { + flags.N = getBit(RD2.entire,31); + flags.Z = ((RD2.entire == 0) ? true : false); + flags.C = ((soma.reg[1] != 0) ? true : false); + flags.V = (((getBit(RN2.entire,31) && getBit(dpi_shiftop.entire,31) && (!getBit(RD2.entire,31))) || + ((!getBit(RN2.entire,31)) && (!getBit(dpi_shiftop.entire,31)) && getBit(RD2.entire,31))) ? true : false); + } + } + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n", flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::AND(int rd, int rn, bool s) { + + arm_isa::reg_t RD2, RN2; + + dprintf("Instruction: AND\n"); + RN2.entire = RB_read(rn); + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n", RN2.entire,dpi_shiftop.entire); + RD2.entire = RN2.entire & dpi_shiftop.entire; + RB_write(rd, RD2.entire); + + if ((s == 1)&&(rd == PC)) { +#ifndef FORGIVE_UNPREDICTABLE + if (arm_proc_mode.mode == arm_isa::processor_mode::USER_MODE || + arm_proc_mode.mode == arm_isa::processor_mode::SYSTEM_MODE) { + printf("Unpredictable AND instruction result\n"); + return; + } + SPSRtoCPSR(); +#endif + } else { + if (s == 1) { + flags.N = getBit(RD2.entire, 31); + flags.Z = ((RD2.entire == 0) ? true : false); + flags.C = dpi_shiftopcarry; + // nothing happens with flags.V + } + } + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n", flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::B(int h, int offset) { + + uint32_t mem_pos, s_extend; + + // Note that PC is already incremented by 4, i.e., pointing to the next instruction + + if(h == 1) + { // h? it is really "l" + dprintf("Instruction: BL\n"); + RB_write(LR, RB_read(PC)); + dprintf("Branch return address: 0x%lX\n", RB_read(LR)); + } else { + dprintf("Instruction: B\n"); + } + + s_extend = arm_isa::SignExtend((int32_t)(offset << 2), 26); + mem_pos = (uint32_t)RB_read(PC) + 4 + s_extend; + dprintf("Calculated branch destination: 0x%X\n", mem_pos); + RB_write(PC, mem_pos); + + //fprintf(stderr, "0x%X\n", (unsigned int)mem_pos); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::BX(int rm) { + + dprintf("Instruction: BX\n"); + + if(isBitSet(rm,0)) { + dprintf("Change to thumb not implemented in this model. PC=%X\n", ac_pc.read()); +// return; + } + + flags.T = isBitSet(rm, 0); + ac_pc = RB_read(rm) & 0xFFFFFFFE; + + //dprintf("Pc = 0x%X",ac_pc); +} + +//------------------------------------------------------ +void arm_isa::BIC(int rd, int rn, bool s) { + + arm_isa::reg_t RD2, RN2; + + dprintf("Instruction: BIC\n"); + RN2.entire = RB_read(rn); + RD2.entire = RN2.entire & ~dpi_shiftop.entire; + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n", RN2.entire,dpi_shiftop.entire); + RB_write(rd,RD2.entire); + + if ((s == 1)&&(rd == PC)) { +#ifndef FORGIVE_UNPREDICTABLE + if (arm_proc_mode.mode == arm_isa::processor_mode::USER_MODE || + arm_proc_mode.mode == arm_isa::processor_mode::SYSTEM_MODE) { + printf("Unpredictable BIC instruction result\n"); + return; + } + SPSRtoCPSR(); +#endif + } else { + if (s == 1) { + flags.N = getBit(RD2.entire,31); + flags.Z = ((RD2.entire == 0) ? true : false); + flags.C = dpi_shiftopcarry; + // nothing happens with flags.V + } + } + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n", flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::CDP(){ + dprintf("Instruction: CDP\n"); + fprintf(stderr,"Warning: CDP is not implemented in this model.\n"); +} + +//------------------------------------------------------ +void arm_isa::CLZ(int rd, int rm) { + + arm_isa::reg_t RD2, RM2; + int i; + + dprintf("Instruction: CLZ\n"); + + // Special cases +#ifndef FORGIVE_UNPREDICTABLE + if((rd == PC)||(rm == PC)) { + if (arm_proc_mode.mode == arm_isa::processor_mode::USER_MODE || + arm_proc_mode.mode == arm_isa::processor_mode::SYSTEM_MODE) { + printf("Unpredictable CLZ instruction result\n"); + return; + } + SPSRtoCPSR(); + } +#endif + + RM2.entire = RB_read(rm); + + if(RM2.entire == 0) RD2.entire = 32; + else { + i = 31; + while((i>=0)&&(!isBitSet(RM2.entire,i))) i--; + RD2.entire = 31 - i; + } + + RB_write(rd, RD2.entire); + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::CMN(int rn) { + + arm_isa::reg_t RN2, alu_out; + arm_isa::r64bit_t soma; + + dprintf("Instruction: CMN\n"); + RN2.entire = RB_read(rn); + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n", RN2.entire,dpi_shiftop.entire); + soma.hilo = (uint64_t)(uint32_t)RN2.entire + (uint64_t)(uint32_t)dpi_shiftop.entire; + alu_out.entire = soma.reg[0]; + + flags.N = getBit(alu_out.entire,31); + flags.Z = ((alu_out.entire == 0) ? true : false); + flags.C = ((soma.reg[1] != 0) ? true : false); + flags.V = (((getBit(RN2.entire,31) && getBit(dpi_shiftop.entire,31) && (!getBit(alu_out.entire,31))) || + ((!getBit(RN2.entire,31)) && (!getBit(dpi_shiftop.entire,31)) && getBit(alu_out.entire,31))) ? true : false); + + dprintf("Results: 0x%lX\n * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n", alu_out.entire,flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::CMP(int rn) { + + arm_isa::reg_t RN2, alu_out, neg_shiftop; + arm_isa::r64bit_t result; + + dprintf("Instruction: CMP\n"); + RN2.entire = RB_read(rn); + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n", RN2.entire,dpi_shiftop.entire); + neg_shiftop.entire = - dpi_shiftop.entire; + result.hilo = (uint64_t)(uint32_t)RN2.entire + (uint64_t)(uint32_t)neg_shiftop.entire; + alu_out.entire = result.reg[0]; + + flags.N = getBit(alu_out.entire,31); + flags.Z = ((alu_out.entire == 0) ? true : false); + flags.C = !(((uint32_t) dpi_shiftop.entire > (uint32_t) RN2.entire) ? true : false); + flags.V = (((getBit(RN2.entire,31) && getBit(neg_shiftop.entire,31) && (!getBit(alu_out.entire,31))) || + ((!getBit(RN2.entire,31)) && (!getBit(neg_shiftop.entire,31)) && getBit(alu_out.entire,31))) ? true : false); + + dprintf("Results: 0x%lX\n * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n", alu_out.entire,flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::EOR(int rd, int rn, bool s) { + + arm_isa::reg_t RD2, RN2; + + dprintf("Instruction: EOR\n"); + RN2.entire = RB_read(rn); + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n", RN2.entire,dpi_shiftop.entire); + RD2.entire = RN2.entire ^ dpi_shiftop.entire; + RB_write(rd, RD2.entire); + + if ((s == 1)&&(rd == PC)) { +#ifndef FORGIVE_UNPREDICTABLE + if (arm_proc_mode.mode == arm_isa::processor_mode::USER_MODE || + arm_proc_mode.mode == arm_isa::processor_mode::SYSTEM_MODE) { + printf("Unpredictable EOR instruction result\n"); + return; + } + SPSRtoCPSR(); +#endif + } else { + if (s == 1) { + flags.N = getBit(RD2.entire, 31); + flags.Z = ((RD2.entire == 0) ? true : false); + flags.C = dpi_shiftopcarry; + // nothing happens with flags.V + } + } + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::LDC(){ + dprintf("Instruction: LDC\n"); + fprintf(stderr,"Warning: LDC instruction is not implemented in this model.\n"); +} + +//------------------------------------------------------ +void arm_isa::LDM(int rlist, bool r) { + + // todo special cases + + int i; + int32_t value; + + if (r == 0) { // LDM(1) + dprintf("Instruction: LDM\n"); + ls_address = lsm_startaddress; + dprintf("Initial address: 0x%lX\n",ls_address.entire); + for(i=0;i<15;i++){ + if(isBitSet(rlist,i)) { + RB_write(i,DATA_PORT->read(ls_address.entire)); + ls_address.entire += 4; + dprintf(" * Loaded register: 0x%X; Value: 0x%X; Next address: 0x%lX\n", i,RB_read(i),ls_address.entire-4); + } + } + + if((isBitSet(rlist,PC))) { // LDM(1) + value = DATA_PORT->read(ls_address.entire); + RB_write(PC,value & 0xFFFFFFFE); + ls_address.entire += 4; + dprintf(" * Loaded register: PC; Next address: 0x%lX\n", ls_address.entire); + } + } else { + // LDM(2) similar to LDM(1), except for the above "if" +#ifndef FORGIVE_UNPREDICTABLE + if (!in_a_privileged_mode()) { + fprintf (stderr, "Unpredictable behavior for LDM2/LDM3\n"); + abort(); + } +#endif + dprintf("Instruction: LDM\n"); + ls_address = lsm_startaddress; + dprintf("Initial address: 0x%lX\n",ls_address.entire); + for(i=0;i<15;i++){ + if(isBitSet(rlist,i)) { + RB.write(i,DATA_PORT->read(ls_address.entire)); + ls_address.entire += 4; + dprintf(" * Loaded register: 0x%X; Value: 0x%X; Next address: 0x%lX\n", i,RB_read(i),ls_address.entire); + } + } + if((isBitSet(rlist,PC))) { // LDM(3) + value = DATA_PORT->read(ls_address.entire); + RB.write(PC,value & 0xFFFFFFFE); + ls_address.entire += 4; + dprintf(" * Loaded register: PC; Next address: 0x%lX\n", ls_address.entire); +#ifndef FORGIVE_UNPREDICTABLE + SPSRtoCPSR(); +#endif + } + } + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::LDR(int rd, int rn) { + + int32_t value; + arm_isa::reg_t tmp; + int addr10; + + dprintf("Instruction: LDR\n"); + addr10 = (uint32_t) ls_address.entire & 0x00000003; + ls_address.entire &= 0xFFFFFFFC; + + // Special cases + // TODO: Verify coprocessor cases (alignment) + dprintf("Reading memory position 0x%08X\n", ls_address.entire); + + switch(addr10) { + case 0: + value = DATA_PORT->read(ls_address.entire); + break; + case 1: + tmp.entire = DATA_PORT->read(ls_address.entire); + value = (arm_isa::RotateRight(8,tmp)).entire; + break; + case 2: + tmp.entire = DATA_PORT->read(ls_address.entire); + value = (arm_isa::RotateRight(16,tmp)).entire; + break; + default: + tmp.entire = DATA_PORT->read(ls_address.entire); + value = (arm_isa::RotateRight(24,tmp)).entire; + } + + if(rd == PC) { + RB_write(PC,(value & 0xFFFFFFFE)); + flags.T = isBitSet(value,0); + dprintf(" * PC <= 0x%08X\n", value & 0xFFFFFFFE); + } + else + { + RB_write(rd,value); + dprintf(" * R%d <= 0x%08X\n", rd, value); + } + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::LDRB(int rd, int rn) { + uint8_t value; + + dprintf("Instruction: LDRB\n"); + + // Special cases + dprintf("Reading memory position 0x%08X\n", ls_address.entire); + value = (uint8_t) DATA_PORT->read_byte(ls_address.entire); + + dprintf("Byte: 0x%X\n", value); + RB_write(rd, ((uint32_t)value)); + + dprintf(" * R%d <= 0x%02X\n", rd, value); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::LDRBT(int rd, int rn) { + + uint8_t value; + + dprintf("Instruction: LDRBT\n"); + + // Special cases + dprintf("Reading memory position 0x%08X\n", ls_address.entire); + value = (uint8_t) DATA_PORT->read_byte(ls_address.entire); + + dprintf("Byte: 0x%X\n", (uint32_t) value); + RB_write(rd, (uint32_t) value); + + dprintf(" * R%d <= 0x%02X\n", rd, value); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::LDRD(int rd, int rn) { + uint32_t value1, value2; + + dprintf("Instruction: LDRD\n"); + dprintf("Reading memory position 0x%08X\n", ls_address.entire); + value1 = DATA_PORT->read_byte(ls_address.entire); + value2 = DATA_PORT->read_byte(ls_address.entire+4); + + // Special cases + // Registrador destino deve ser par + if(isBitSet(rd,0)){ + printf("Undefined LDRD instruction result (Rd must be even)\n"); + return; + } + // Verificar alinhamento do doubleword + if((rd == LR)||(ls_address.entire & 0x00000007)){ + printf("Unpredictable LDRD instruction result (Address is not doubleword aligned) @ 0x%08X\n", RB_read(PC)-4); + return; + } + + //FIXME: Verify if writeback receives +4 from address + RB_write(rd, value1); + RB_write(rd+1, value2); + + dprintf(" * R%d <= 0x%08X\n * R%d <= 0x%08X\n (little) value = 0x%08X%08X\n (big) value = 0x%08X08X\n", rd, value1, rd+1, value2, value2, value1, value1, value2); + + ac_pc = RB_read(PC); +} +//------------------------------------------------------ +void arm_isa::LDRH(int rd, int rn) { + uint32_t value; + + dprintf("Instruction: LDRH\n"); + dprintf("Reading memory position 0x%08X\n", ls_address.entire); + // Special cases + // verify coprocessor alignment + // verify halfword alignment + if(isBitSet(ls_address.entire,0)){ + printf("Unpredictable LDRH instruction result (Address is not Halfword Aligned)\n"); + return; + } + value = DATA_PORT->read_half(ls_address.entire); + + RB_write(rd, value); + + dprintf(" * R%d <= 0x%04X\n", rd, value); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::LDRSB(int rd, int rn) { + + uint32_t data; + + dprintf("Instruction: LDRSB\n"); + + // Special cases + dprintf("Reading memory position 0x%08X\n", ls_address.entire); + data = DATA_PORT->read_byte(ls_address.entire); + data = arm_isa::SignExtend(data, 8); + + RB_write(rd, data); + + dprintf(" * R%d <= 0x%08X\n", rd, data); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::LDRSH(int rd, int rn){ + + uint32_t data; + + dprintf("Instruction: LDRSH\n"); + dprintf("Reading memory position 0x%08X\n", ls_address.entire); + // Special cases + // verificar alinhamento do halfword + if(isBitSet(ls_address.entire, 0)) { + printf("Unpredictable LDRSH instruction result (Address is not halfword aligned)\n"); + return; + } + // Verify coprocessor alignment + + data = DATA_PORT->read_half(ls_address.entire); + + data = arm_isa::SignExtend(data,16); + RB_write(rd, data); + + dprintf(" * R%d <= 0x%08X\n", rd, data); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::LDRT(int rd, int rn) { + + int addr10; + arm_isa::reg_t tmp; + uint32_t value; + + dprintf("Instruction: LDRT\n"); + + addr10 = (int)ls_address.entire & 0x00000003; + ls_address.entire &= 0xFFFFFFFC; + dprintf("Reading memory position 0x%08X\n", ls_address.entire); + + // Special cases + // Verify coprocessor alignment + + switch(addr10) { + case 0: + value = DATA_PORT->read(ls_address.entire); + RB_write(rd, value); + break; + case 1: + tmp.entire = DATA_PORT->read(ls_address.entire); + value = arm_isa::RotateRight(8,tmp).entire; + RB_write(rd, value); + break; + case 2: + tmp.entire = DATA_PORT->read(ls_address.entire); + value = arm_isa::RotateRight(16,tmp).entire; + RB_write(rd, value); + break; + default: + tmp.entire = DATA_PORT->read(ls_address.entire); + value = arm_isa::RotateRight(24, tmp).entire; + RB_write(rd, value); + } + + dprintf(" * R%d <= 0x%08X\n", rd, value); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::MCR(){ + dprintf("Instruction: MCR\n"); + fprintf(stderr, "Warning: MCR instruction is not implemented in this model.\n"); +} + +//------------------------------------------------------ +void arm_isa::MLA(int rd, int rn, int rm, int rs, bool s) { + + arm_isa::reg_t RD2, RN2, RM2, RS2; + RN2.entire = RB_read(rn); + RM2.entire = RB_read(rm); + RS2.entire = RB_read(rs); + + dprintf("Instruction: MLA\n"); + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n C = 0x%lX\n", RM2.entire, RS2.entire, RN2.entire); + + // Special cases + if((rd == PC)||(rm == PC)||(rs == PC)||(rn == PC)||(rd == rm)) { + fprintf(stderr, "Unpredictable MLA instruction result\n"); + return; + } + + RD2.entire = RM2.entire * RS2.entire + RN2.entire; + if(s == 1) { + flags.N = getBit(RD2.entire,31); + flags.Z = ((RD2.entire == 0) ? true : false); + // nothing happens with flags.C and flags.V + } + RB_write(rd,RD2.entire); + + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::MOV(int rd, bool s) { + + dprintf("Instruction: MOV\n"); + RB_write(rd, dpi_shiftop.entire); + + if ((s == 1)&&(rd == PC)) { +#ifndef FORGIVE_UNPREDICTABLE + if (arm_proc_mode.mode == arm_isa::processor_mode::USER_MODE || + arm_proc_mode.mode == arm_isa::processor_mode::SYSTEM_MODE) { + printf("Unpredictable MOV instruction result\n"); + return; + } + SPSRtoCPSR(); +#endif + } + if (s == 1) { + flags.N = getBit(dpi_shiftop.entire, 31); + flags.Z = ((dpi_shiftop.entire == 0) ? true : false); + flags.C = dpi_shiftopcarry; + // nothing happens with flags.V + } + + dprintf(" * R%d <= 0x%08X (%d)\n", rd, dpi_shiftop.entire, dpi_shiftop.entire); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::MRC(){ + dprintf("Instruction: MRC\n"); + fprintf(stderr, "Warning: MRC instruction is not implemented in this model.\n"); +} + +//------------------------------------------------------ +void arm_isa::MRS(int rd, bool r, int zero3, int subop2, int func2, int subop1, int rm, int field) { + + unsigned res; + + dprintf("Instruction: MRS\n"); + + // Special cases + if((rd == PC)||((zero3 != 0)&&(subop2 != 0)&&(func2 != 0)&&(subop1 != 0)&&(rm != 0))||(field != 15)) { + printf("Unpredictable MRS instruction result\n"); + dprintf("**! Unpredictable MRS instruction result\n"); + return; + } + + if (r == 1) { + if (!in_a_privileged_mode()) { + printf("Unpredictable MRS instruction result\n"); + dprintf("**! Unpredictable MRS instruction result\n"); + return; + } + res = readSPSR(); + dprintf("Read SPSR.\n"); + } else { + res = readCPSR(); + dprintf("Read CPSR.\n"); + } + + RB_write(rd,res); + + dprintf(" * R%d <= 0x%08X\n", rd, res); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::MUL(int rd, int rm, int rs, bool s) { + + arm_isa::reg_t RD2, RM2, RS2; + RM2.entire = RB_read(rm); + RS2.entire = RB_read(rs); + + dprintf("Instruction: MUL\n"); + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n", RM2.entire, RS2.entire); + + // Special cases + if((rd == PC)||(rm == PC)||(rs == PC)||(rd == rm)) { + fprintf(stderr, "Unpredictable MUL instruction result\n"); +// return; + } + + RD2.entire = RM2.entire * RS2.entire; + if(s == 1) { + flags.N = getBit(RD2.entire, 31); + flags.Z = ((RD2.entire == 0) ? true : false); + // nothing happens with flags.C and flags.V + } + RB_write(rd, RD2.entire); + + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::MVN(int rd, bool s) { + + dprintf("Instruction: MVN\n"); + RB_write(rd,~dpi_shiftop.entire); + + if ((s == 1)&&(rd == PC)) { +#ifndef FORGIVE_UNPREDICTABLE + if (arm_proc_mode.mode == arm_isa::processor_mode::USER_MODE || + arm_proc_mode.mode == arm_isa::processor_mode::SYSTEM_MODE) { + printf("Unpredictable MVN instruction result\n"); + return; + } + SPSRtoCPSR(); +#endif + } else { + if (s == 1) { + flags.N = getBit(~dpi_shiftop.entire,31); + flags.Z = ((~dpi_shiftop.entire == 0) ? true : false); + flags.C = dpi_shiftopcarry; + // nothing happens with flags.V + } + } + + dprintf(" * R%d <= 0x%08X (%d)\n", rd, ~dpi_shiftop.entire, ~dpi_shiftop.entire); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::ORR(int rd, int rn, bool s) { + + arm_isa::reg_t RD2, RN2; + + dprintf("Instruction: ORR\n"); + RN2.entire = RB_read(rn); + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n", RN2.entire,dpi_shiftop.entire); + RD2.entire = RN2.entire | dpi_shiftop.entire; + RB_write(rd,RD2.entire); + + if ((s == 1)&&(rd == PC)) { +#ifndef FORGIVE_UNPREDICTABLE + if (arm_proc_mode.mode == arm_isa::processor_mode::USER_MODE || + arm_proc_mode.mode == arm_isa::processor_mode::SYSTEM_MODE) { + printf("Unpredictable ORR instruction result\n"); + return; + } + SPSRtoCPSR(); +#endif + } else { + if (s == 1) { + flags.N = getBit(RD2.entire,31); + flags.Z = ((RD2.entire == 0) ? true : false); + flags.C = dpi_shiftopcarry; + // nothing happens with flags.V + } + } + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::RSB(int rd, int rn, bool s) { + + arm_isa::reg_t RD2, RN2, neg_RN2; + arm_isa::r64bit_t result; + + dprintf("Instruction: RSB\n"); + RN2.entire = RB_read(rn); + if(rn == PC) RN2.entire += 4; + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n", RN2.entire,dpi_shiftop.entire); + neg_RN2.entire = - RN2.entire; + result.hilo = (uint64_t)(uint32_t)dpi_shiftop.entire + (uint64_t)(uint32_t)neg_RN2.entire; + RD2.entire = result.reg[0]; + RB_write(rd, RD2.entire); + if ((s == 1) && (rd == PC)) { +#ifndef FORGIVE_UNPREDICTABLE + if (arm_proc_mode.mode == arm_isa::processor_mode::USER_MODE || + arm_proc_mode.mode == arm_isa::processor_mode::SYSTEM_MODE) { + printf("Unpredictable RSB instruction result\n"); + return; + } + SPSRtoCPSR(); +#endif + } else { + if (s == 1) { + flags.N = getBit(RD2.entire,31); + flags.Z = ((RD2.entire == 0) ? true : false); + flags.C = !(((uint32_t) RN2.entire > (uint32_t) dpi_shiftop.entire) ? true : false); + flags.V = (((getBit(neg_RN2.entire,31) && getBit(dpi_shiftop.entire,31) && (!getBit(RD2.entire,31))) || + ((!getBit(neg_RN2.entire,31)) && (!getBit(dpi_shiftop.entire,31)) && getBit(RD2.entire,31))) ? true : false); + } + } + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::RSC(int rd, int rn, bool s) { + + arm_isa::reg_t RD2, RN2, neg_RN2; + arm_isa::r64bit_t result; + + dprintf("Instruction: RSC\n"); + RN2.entire = RB_read(rn); + if(rn == PC) RN2.entire += 4; + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n Carry = %d\n", RN2.entire,dpi_shiftop.entire, flags.C); + if (!flags.C) { RN2.entire++; } + neg_RN2.entire = - RN2.entire; + result.hilo = (uint64_t)(uint32_t)dpi_shiftop.entire + (uint64_t)(uint32_t)neg_RN2.entire; + RD2.entire = result.reg[0]; + + RB_write(rd, RD2.entire); + if ((s == 1)&&(rd == PC)) { +#ifndef FORGIVE_UNPREDICTABLE + if (arm_proc_mode.mode == arm_isa::processor_mode::USER_MODE || + arm_proc_mode.mode == arm_isa::processor_mode::SYSTEM_MODE) { + printf("Unpredictable RSC instruction result\n"); + return; + } + SPSRtoCPSR(); +#endif + } else { + if (s == 1) { + flags.N = getBit(RD2.entire,31); + flags.Z = ((RD2.entire == 0) ? true : false); + if ((!flags.C)&&(RN2.entire == 0)) + flags.C = false; + else + flags.C = !(((uint32_t) RN2.entire > (uint32_t) dpi_shiftop.entire) ? true : false); + flags.V = (((getBit(neg_RN2.entire,31) && getBit(dpi_shiftop.entire,31) && (!getBit(RD2.entire,31))) || + ((!getBit(neg_RN2.entire,31)) && (!getBit(dpi_shiftop.entire,31)) && getBit(RD2.entire,31))) ? true : false); + } + } + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::SBC(int rd, int rn, bool s) { + + arm_isa::reg_t RD2, RN2, neg_shiftop; + arm_isa::r64bit_t result; + + dprintf("Instruction: SBC\n"); + RN2.entire = RB_read(rn); + if(rn == PC) RN2.entire += 4; + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n Carry = %d\n", RN2.entire,dpi_shiftop.entire, flags.C); + if (!flags.C) dpi_shiftop.entire++; + neg_shiftop.entire = - dpi_shiftop.entire; + result.hilo = (uint64_t)(uint32_t)RN2.entire + (uint64_t)(uint32_t)neg_shiftop.entire; + RD2.entire = result.reg[0]; + RB_write(rd, RD2.entire); + if ((s == 1)&&(rd == PC)) { +#ifndef FORGIVE_UNPREDICTABLE + if (arm_proc_mode.mode == arm_isa::processor_mode::USER_MODE || + arm_proc_mode.mode == arm_isa::processor_mode::SYSTEM_MODE) { + printf("Unpredictable SBC instruction result\n"); + return; + } + SPSRtoCPSR(); +#endif + } else { + if (s == 1) { + flags.N = getBit(RD2.entire,31); + flags.Z = ((RD2.entire == 0) ? true : false); + if ((!flags.C)&&(dpi_shiftop.entire==0)) + flags.C = false; + else + flags.C = !(((uint32_t) dpi_shiftop.entire > (uint32_t) RN2.entire) ? true : false); + flags.V = (((getBit(RN2.entire,31) && getBit(neg_shiftop.entire,31) && (!getBit(RD2.entire,31))) || + ((!getBit(RN2.entire,31)) && (!getBit(neg_shiftop.entire,31)) && getBit(RD2.entire,31))) ? true : false); + } + } + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::SMLAL(int rdhi, int rdlo, int rm, int rs, bool s) { + + arm_isa::r64bit_t result, acc; + arm_isa::reg_t RM2, RS2; + + RM2.entire = RB_read(rm); + RS2.entire = RB_read(rs); + acc.reg[0] = RB_read(rdlo); + acc.reg[1] = RB_read(rdhi); + + dprintf("Instruction: SMLAL\n"); + dprintf("Operands:\n rm=0x%X, contains 0x%lX\n rs=0x%X, contains 0x%lX\n Add multiply result to %lld\nDestination(Hi): Rdhi=0x%X, Rdlo=0x%X\n", rm,RM2.entire,rs,RS2.entire,acc.hilo,rdhi,rdlo); + + // Special cases + if((rdhi == PC)||(rdlo == PC)||(rm == PC)||(rs == PC)||(rdhi == rdlo)||(rdhi == rm)||(rdlo == rm)) { + printf("Unpredictable SMLAL instruction result\n"); + return; + } + + result.hilo = (int64_t)RM2.entire * (int64_t)RS2.entire + acc.hilo; + RB_write(rdhi,result.reg[1]); + RB_write(rdlo,result.reg[0]); + if(s == 1){ + flags.N = getBit(result.reg[1],31); + flags.Z = ((result.hilo == 0) ? true : false); + // nothing happens with flags.C and flags.V + } + dprintf(" * R%d(high) R%d(low) <= 0x%08X%08X (%d)\n", rdhi, rdlo, result.reg[1], result.reg[0], result.reg[0]); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::SMULL(int rdhi, int rdlo, int rm, int rs, bool s) { + + arm_isa::r64bit_t result; + arm_isa::reg_t RM2, RS2; + + RM2.entire = RB_read(rm); + RS2.entire = RB_read(rs); + + dprintf("Instruction: SMULL\n"); + dprintf("Operands:\n rm=0x%X, contains 0x%lX\n rs=0x%X, contains 0x%lX\n Destination(Hi): Rdhi=0x%X, Rdlo=0x%X\n", rm,RM2.entire,rs,RS2.entire,rdhi,rdlo); + + // Special cases + if((rdhi == PC)||(rdlo == PC)||(rm == PC)||(rs == PC)||(rdhi == rdlo)||(rdhi == rm)||(rdlo == rm)) { + printf("Unpredictable SMULL instruction result\n"); + return; + } + + result.hilo = (int64_t)RM2.entire * (int64_t)RS2.entire; + RB_write(rdhi,result.reg[1]); + RB_write(rdlo,result.reg[0]); + if(s == 1){ + flags.N = getBit(result.reg[1],31); + flags.Z = ((result.hilo == 0) ? true : false); + // nothing happens with flags.C and flags.V + } + dprintf(" * R%d(high) R%d(low) <= 0x%08X%08X (%d)\n", rdhi, rdlo, result.reg[1], result.reg[0], result.reg[0]); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::STC(){ + dprintf("Instruction: STC\n"); + fprintf(stderr,"Warning: STC instruction is not implemented in this model.\n"); +} + +//------------------------------------------------------ +void arm_isa::STM(int rn, int rlist, unsigned r) { + + // todo special cases + + int i; + + if (r == 0) { // STM(1) + dprintf("Instruction: STM\n"); + ls_address = lsm_startaddress; + for(i=0;i<16;i++){ + if(isBitSet(rlist,i)) { + // rn is in rlist. e.g. push {sp,...} + if (i == rn) + DATA_PORT->write(ls_address.entire,lsm_oldrn.entire); + else + DATA_PORT->write(ls_address.entire,RB_read(i)); + + ls_address.entire += 4; + dprintf(" * Stored register: 0x%X; value: 0x%X; address: 0x%lX\n",i,RB_read(i),ls_address.entire-4); + } + } + } else { // STM(2) +#ifndef FORGIVE_UNPREDICTABLE + if (!in_a_privileged_mode()) { + fprintf(stderr, "STM(2) unpredictable in user mode"); + abort(); + } +#endif + dprintf("Instruction: STM(2)\n"); + ls_address = lsm_startaddress; + for(i=0;i<16;i++){ + if(isBitSet(rlist,i)) { + DATA_PORT->write(ls_address.entire,RB .read(i)); + ls_address.entire += 4; + dprintf(" * Stored register: 0x%X; value: 0x%X; address: 0x%lX\n",i,RB_read(i),ls_address.entire-4); + } + } + } + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::STR(int rd, int rn) { + + dprintf("Instruction: STR\n"); + + // Special cases + // verify coprocessor alignment + + DATA_PORT->write(ls_address.entire, RB_read(rd)); + + dprintf(" * MEM[0x%08X] <= 0x%08X\n", ls_address.entire, RB_read(rd)); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::STRB(int rd, int rn) { + + arm_isa::reg_t RD2; + + dprintf("Instruction: STRB\n"); + + // Special cases + + RD2.entire = RB_read(rd); + DATA_PORT->write_byte(ls_address.entire, RD2.byte[0]); + + dprintf(" * MEM[0x%08X] <= 0x%02X\n", ls_address.entire, RD2.byte[0]); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::STRBT(int rd, int rn) { + + arm_isa::reg_t RD2; + + dprintf("Instruction: STRBT\n"); + + // Special cases + + RD2.entire = RB_read(rd); + DATA_PORT->write_byte(ls_address.entire, RD2.byte[0]); + + dprintf(" * MEM[0x%08X] <= 0x%02X\n", ls_address.entire, RD2.byte[0]); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::STRD(int rd, int rn) { + + dprintf("Instruction: STRD\n"); + + // Special cases + // Destination register must be even + if(isBitSet(rd,0)){ + printf("Undefined STRD instruction result (Rd must be even)\n"); + return; + } + // Check doubleword alignment + if((rd == LR)||(ls_address.entire & 0x00000007)){ + printf("Unpredictable STRD instruction result (Address is not doubleword aligned)\n"); + return; + } + + //FIXME: Check if writeback receives +4 from second address + DATA_PORT->write(ls_address.entire,RB_read(rd)); + DATA_PORT->write(ls_address.entire+4,RB_read(rd+1)); + + dprintf(" * MEM[0x%08X], *DATA_PORT[0x%08X] <= 0x%08X %08X\n", ls_address.entire, ls_address.entire+4, RB_read(rd+1), RB_read(rd)); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::STRH(int rd, int rn) { + + int16_t data; + + dprintf("Instruction: STRH\n"); + + // Special cases + // verify coprocessor alignment + // verify halfword alignment + if(isBitSet(ls_address.entire,0)){ + printf("Unpredictable STRH instruction result (Address is not halfword aligned)\n"); + return; + } + + data = (int16_t) (RB_read(rd) & 0x0000FFFF); + DATA_PORT->write_half(ls_address.entire, data); + + dprintf(" * MEM[0x%08X] <= 0x%04X\n", ls_address.entire, data); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::STRT(int rd, int rn) { + + dprintf("Instruction: STRT\n"); + + // Special cases + // verificar caso do coprocessador (alinhamento) + + DATA_PORT->write(ls_address.entire, RB_read(rd)); + + dprintf(" * MEM[0x%08X] <= 0x%08X\n", ls_address.entire, RB_read(rd)); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::SUB(int rd, int rn, bool s) { + + arm_isa::reg_t RD2, RN2, neg_shiftop; + arm_isa::r64bit_t result; + + dprintf("Instruction: SUB\n"); + RN2.entire = RB_read(rn); + if(rn == PC) RN2.entire += 4; + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n", RN2.entire,dpi_shiftop.entire); + neg_shiftop.entire = - dpi_shiftop.entire; + result.hilo = (uint64_t)(uint32_t)RN2.entire + (uint64_t)(uint32_t)neg_shiftop.entire; + RD2.entire = result.reg[0]; + RB_write(rd, RD2.entire); + if ((s == 1)&&(rd == PC)) { +#ifndef FORGIVE_UNPREDICTABLE + if (arm_proc_mode.mode == arm_isa::processor_mode::USER_MODE || + arm_proc_mode.mode == arm_isa::processor_mode::SYSTEM_MODE) { + printf("Unpredictable SUB instruction result\n"); + return; + } + SPSRtoCPSR(); +#endif + } else { + if (s == 1) { + flags.N = getBit(RD2.entire,31); + flags.Z = ((RD2.entire == 0) ? true : false); + flags.C = !(((uint32_t) dpi_shiftop.entire > (uint32_t) RN2.entire) ? true : false); + flags.V = (((getBit(RN2.entire,31) && getBit(neg_shiftop.entire,31) && (!getBit(RD2.entire,31))) || + ((!getBit(RN2.entire,31)) && (!getBit(neg_shiftop.entire,31)) && getBit(RD2.entire,31))) ? true : false); + } + } + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); + +} + +//------------------------------------------------------ +void arm_isa::SWP(int rd, int rn, int rm) { + + arm_isa::reg_t RN2, RM2, rtmp; + int32_t tmp; + int rn10; + + dprintf("Instruction: SWP\n"); + + // Special cases + // verify coprocessor alignment + if((rd == PC)||(rm == PC)||(rn == PC)||(rm == rn)||(rn == rd)){ + printf("Unpredictable SWP instruction result\n"); + return; + } + + RN2.entire = RB_read(rn); + RM2.entire = RB_read(rm); + rn10 = RN2.entire & 0x00000003; + + switch(rn10) { + case 0: + tmp = DATA_PORT->read(RN2.entire); + break; + case 1: + rtmp.entire = DATA_PORT->read(RN2.entire); + tmp = (arm_isa::RotateRight(8,rtmp)).entire; + break; + case 2: + rtmp.entire = DATA_PORT->read(RN2.entire); + tmp = (arm_isa::RotateRight(16,rtmp)).entire; + break; + default: + rtmp.entire = DATA_PORT->read(RN2.entire); + tmp = (arm_isa::RotateRight(24,rtmp)).entire; + } + + DATA_PORT->write(RN2.entire,RM2.entire); + RB_write(rd,tmp); + + dprintf(" * MEM[0x%08X] <= 0x%08X (%d)\n", RN2.entire, RM2.entire, RM2.entire); + dprintf(" * R%d <= 0x%08X (%d)\n", rd, tmp, tmp); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::SWPB(int rd, int rn, int rm) { + + uint32_t tmp; + arm_isa::reg_t RM2, RN2; + + dprintf("Instruction: SWPB\n"); + + // Special cases + if((rd == PC)||(rm == PC)||(rn == PC)||(rm == rn)||(rn == rd)){ + printf("Unpredictable SWPB instruction result\n"); + return; + } + + RM2.entire = RB_read(rm); + RN2.entire = RB_read(rn); + + tmp = (uint32_t) DATA_PORT->read_byte(RN2.entire); + DATA_PORT->write_byte(RN2.entire,RM2.byte[0]); + RB_write(rd,tmp); + + dprintf(" * MEM[0x%08X] <= 0x%02X (%d)\n", RN2.entire, RM2.byte[0], RM2.byte[0]); + dprintf(" * R%d <= 0x%02X (%d)\n", rd, tmp, tmp); + + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::TEQ(int rn) { + + arm_isa::reg_t RN2, alu_out; + + dprintf("Instruction: TEQ\n"); + RN2.entire = RB_read(rn); + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n", RN2.entire,dpi_shiftop.entire); + alu_out.entire = RN2.entire ^ dpi_shiftop.entire; + + flags.N = getBit(alu_out.entire,31); + flags.Z = ((alu_out.entire == 0) ? true : false); + flags.C = dpi_shiftopcarry; + // nothing happens with flags.V + + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::TST(int rn) { + + arm_isa::reg_t RN2, alu_out; + + dprintf("Instruction: TST\n"); + RN2.entire = RB_read(rn); + dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n", RN2.entire,dpi_shiftop.entire); + alu_out.entire = RN2.entire & dpi_shiftop.entire; + + flags.N = getBit(alu_out.entire, 31); + flags.Z = ((alu_out.entire == 0) ? true : false); + flags.C = dpi_shiftopcarry; + // nothing happens with flags.V + + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::UMLAL(int rdhi, int rdlo, int rm, int rs, bool s) { + + arm_isa::r64bit_t result, acc; + arm_isa::reg_t RM2, RS2; + + RM2.entire = RB_read(rm); + RS2.entire = RB_read(rs); + acc.reg[0] = RB_read(rdlo); + acc.reg[1] = RB_read(rdhi); + + dprintf("Instruction: UMLAL\n"); + dprintf("Operands:\n rm=0x%X, contains 0x%lX\n rs=0x%X, contains 0x%lX\n Add multiply result to %lld\nDestination(Hi): Rdhi=0x%X, Rdlo=0x%X\n", rm,RM2.entire,rs,RS2.entire,acc.hilo,rdhi,rdlo); + + // Special cases + if((rdhi == PC)||(rdlo == PC)||(rm == PC)||(rs == PC)||(rdhi == rdlo)||(rdhi == rm)||(rdlo == rm)) { + printf("Unpredictable UMLAL instruction result\n"); + return; + } + + result.hilo = (uint64_t)(uint32_t)RM2.entire * (uint64_t)(uint32_t)RS2.entire + + (uint64_t)acc.hilo; + RB_write(rdhi,result.reg[1]); + RB_write(rdlo,result.reg[0]); + if(s == 1){ + flags.N = getBit(result.reg[1],31); + flags.Z = ((result.hilo == 0) ? true : false); + // nothing happens with flags.C and flags.V + } + + dprintf(" * R%d(high) R%d(low) <= 0x%08X%08X (%d)\n", rdhi, rdlo, result.reg[1], result.reg[0], result.reg[0]); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::UMULL(int rdhi, int rdlo, int rm, int rs, bool s) { + + + arm_isa::r64bit_t result; + arm_isa::reg_t RM2, RS2; + + RM2.entire = RB_read(rm); + RS2.entire = RB_read(rs); + + dprintf("Instruction: UMULL\n"); + dprintf("Operands:\n rm=0x%X, contains 0x%lX\n rs=0x%X, contains 0x%lX\n Destination(Hi): Rdhi=0x%X, Rdlo=0x%X\n", rm,RM2.entire,rs,RS2.entire,rdhi,rdlo); + + // Special cases + if((rdhi == PC)||(rdlo == PC)||(rm == PC)||(rs == PC)||(rdhi == rdlo)||(rdhi == rm)||(rdlo == rm)) { + printf("Unpredictable UMULL instruction result\n"); + return; + } + + result.hilo = (uint64_t)(uint32_t)RM2.entire * (uint64_t)(uint32_t)RS2.entire; + RB_write(rdhi,result.reg[1]); + RB_write(rdlo,result.reg[0]); + if(s == 1){ + flags.N = getBit(result.reg[1],31); + flags.Z = ((result.hilo == 0) ? true : false); + // nothing happens with flags.C and flags.V + } + dprintf(" * R%d(high) R%d(low) <= 0x%08X%08X (%d)\n", rdhi, rdlo, result.reg[1], result.reg[0], result.reg[0]); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n",flags.N,flags.Z,flags.C,flags.V); + ac_pc = RB_read(PC); +} + +//------------------------------------------------------ +void arm_isa::DSMLA(int rd, int rn) { + + arm_isa::reg_t RD2, RN2; + + RN2.entire = RB_read(rn); + + dprintf("Instruction: SMLA\n"); + dprintf("Operands:\n rn=0x%X, contains 0x%lX\n first operand contains 0x%lX\n second operand contains 0x%lX\n rd=0x%X, contains 0x%lX\n", rn, RN2.entire, OP1.entire, OP2.entire, rd, RD2.entire); + + RD2.entire = (OP1.entire * OP2.entire) + RN2.entire; + + RB_write(rd, RD2.entire); + + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + + // SET Q FLAG +} + +//------------------------------------------------------ +void arm_isa::DSMUL(int rd) { + + arm_isa::reg_t RD2; + + dprintf("Instruction: SMUL\n"); + dprintf("Operands:\n first operand contains 0x%lX\n second operand contains 0x%lX\n rd=0x%X, contains 0x%lX\n", OP1.entire, OP2.entire, rd, RD2.entire); + + RD2.entire = OP1.entire * OP2.entire; + + RB_write(rd, RD2.entire); + + dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire); + + // SET Q FLAG +} + +//------------------------------------------------------ + + +//!Instruction and1 behavior method. +void ac_behavior( and1 ){ AND(rd, rn, s);} + +//!Instruction eor1 behavior method. +void ac_behavior( eor1 ){ EOR(rd, rn, s);} + +//!Instruction sub1 behavior method. +void ac_behavior( sub1 ){ SUB(rd, rn, s);} + +//!Instruction rsb1 behavior method. +void ac_behavior( rsb1 ){ RSB(rd, rn, s);} + +//!Instruction add1 behavior method. +void ac_behavior( add1 ){ ADD(rd, rn, s);} + +//!Instruction adc1 behavior method. +void ac_behavior( adc1 ){ ADC(rd, rn, s);} + +//!Instruction sbc1 behavior method. +void ac_behavior( sbc1 ){ SBC(rd, rn, s);} + +//!Instruction rsc1 behavior method. +void ac_behavior( rsc1 ){ RSC(rd, rn, s);} + +//!Instruction tst1 behavior method. +void ac_behavior( tst1 ){ TST(rn);} + +//!Instruction teq1 behavior method. +void ac_behavior( teq1 ){ TEQ(rn);} + +//!Instruction cmp1 behavior method. +void ac_behavior( cmp1 ){ CMP(rn);} + +//!Instruction cmn1 behavior method. +void ac_behavior( cmn1 ){ CMN(rn);} + +//!Instruction orr1 behavior method. +void ac_behavior( orr1 ){ ORR(rd, rn, s);} + +//!Instruction mov1 behavior method. +void ac_behavior( mov1 ){ MOV(rd, s);} + +//!Instruction bic1 behavior method. +void ac_behavior( bic1 ){ BIC(rd, rn, s);} + +//!Instruction mvn1 behavior method. +void ac_behavior( mvn1 ){ MVN(rd, s);} + +//!Instruction and2 behavior method. +void ac_behavior( and2 ){ AND(rd, rn, s);} + +//!Instruction eor2 behavior method. +void ac_behavior( eor2 ){ EOR(rd, rn, s);} + +//!Instruction sub2 behavior method. +void ac_behavior( sub2 ){ SUB(rd, rn, s);} + +//!Instruction rsb2 behavior method. +void ac_behavior( rsb2 ){ RSB(rd, rn, s);} + +//!Instruction add2 behavior method. +void ac_behavior( add2 ){ ADD(rd, rn, s);} + +//!Instruction adc2 behavior method. +void ac_behavior( adc2 ){ ADC(rd, rn, s);} + +//!Instruction sbc2 behavior method. +void ac_behavior( sbc2 ){ SBC(rd, rn, s);} + +//!Instruction rsc2 behavior method. +void ac_behavior( rsc2 ){ RSC(rd, rn, s);} + +//!Instruction tst2 behavior method. +void ac_behavior( tst2 ){ TST(rn);} + +//!Instruction teq2 behavior method. +void ac_behavior( teq2 ){ TEQ(rn);} + +//!Instruction cmp2 behavior method. +void ac_behavior( cmp2 ){ CMP(rn);} + +//!Instruction cmn2 behavior method. +void ac_behavior( cmn2 ){ CMN(rn);} + +//!Instruction orr2 behavior method. +void ac_behavior( orr2 ){ ORR(rd, rn, s);} + +//!Instruction mov2 behavior method. +void ac_behavior( mov2 ){ MOV(rd, s);} + +//!Instruction bic2 behavior method. +void ac_behavior( bic2 ){ BIC(rd, rn, s);} + +//!Instruction mvn2 behavior method. +void ac_behavior( mvn2 ){ MVN(rd, s);} + +//!Instruction and3 behavior method. +void ac_behavior( and3 ){ AND(rd, rn, s);} + +//!Instruction eor3 behavior method. +void ac_behavior( eor3 ){ EOR(rd, rn, s);} + +//!Instruction sub3 behavior method. +void ac_behavior( sub3 ){ SUB(rd, rn, s);} + +//!Instruction rsb3 behavior method. +void ac_behavior( rsb3 ){ RSB(rd, rn, s);} + +//!Instruction add3 behavior method. +void ac_behavior( add3 ){ ADD(rd, rn, s);} + +//!Instruction adc3 behavior method. +void ac_behavior( adc3 ){ ADC(rd, rn, s);} + +//!Instruction sbc3 behavior method. +void ac_behavior( sbc3 ){ SBC(rd, rn, s);} + +//!Instruction rsc3 behavior method. +void ac_behavior( rsc3 ){ RSC(rd, rn, s);} + +//!Instruction tst3 behavior method. +void ac_behavior( tst3 ){ TST(rn);} + +//!Instruction teq3 behavior method. +void ac_behavior( teq3 ){ TEQ(rn);} + +//!Instruction cmp3 behavior method. +void ac_behavior( cmp3 ){ CMP(rn);} + +//!Instruction cmn3 behavior method. +void ac_behavior( cmn3 ){ CMN(rn);} + +//!Instruction orr3 behavior method. +void ac_behavior( orr3 ){ ORR(rd, rn, s);} + +//!Instruction mov3 behavior method. +void ac_behavior( mov3 ){ MOV(rd, s);} + +//!Instruction bic3 behavior method. +void ac_behavior( bic3 ){ BIC(rd, rn, s);} + +//!Instruction mvn3 behavior method. +void ac_behavior( mvn3 ){ MVN(rd, s);} + +//!Instruction b behavior method. +void ac_behavior( b ){ B(h, offset);} + +//!Instruction blx1 behavior method. +void ac_behavior( blx1 ){ + fprintf(stderr,"Warning: BLX instruction is not implemented in this model. PC=%X\n", ac_pc.read()); +} + +//!Instruction bx behavior method. +void ac_behavior( bx ){ BX(rm); } + +//!Instruction blx2 behavior method. +void ac_behavior( blx2 ){ + arm_isa::reg_t dest; + dest.entire = RB_read(rm); + dprintf("Instruction: BLX2\n"); + dprintf("Branch to contents of reg: 0x%X\n", rm); + dprintf("Contents of register: 0x%lX\n", dest.entire); + // Note that PC is already incremented by 4, i.e., pointing to the next instruction + if(isBitSet(dest.entire,0)) { + fprintf(stderr,"Change to thumb not implemented in this model. PC=%X\n", ac_pc.read()); + exit(EXIT_FAILURE); + } + + RB_write(LR, RB_read(PC)); + dprintf("Branch return address: 0x%lX\n", RB_read(LR)); + + flags.T = isBitSet(rm, 0); + RB_write(PC, dest.entire & 0xFFFFFFFE); + ac_pc = RB_read(PC); + + dprintf("Calculated branch destination: 0x%lX\n", RB_read(PC)); +} + +//!Instruction swp behavior method. +void ac_behavior( swp ){ SWP(rd, rn, rm); } + +//!Instruction swpb behavior method. +void ac_behavior( swpb ){ SWPB(rd, rn, rm); } + +//!Instruction mla behavior method. +void ac_behavior( mla ){ MLA(rn, rd, rm, rs, s);} +// OBS: inversao dos parametros proposital ("fields with the same name...") + +//!Instruction mul behavior method. +void ac_behavior( mul ){ MUL(rn, rm, rs, s);} +// OBS: inversao dos parametros proposital ("fields with the same name...") + +//!Instruction smlal behavior method. +void ac_behavior( smlal ){ SMLAL(rdhi, rdlo, rm, rs, s);} + +//!Instruction smull behavior method. +void ac_behavior( smull ){ SMULL(rdhi, rdlo, rm, rs, s);} + +//!Instruction umlal behavior method. +void ac_behavior( umlal ){ UMLAL(rdhi, rdlo, rm, rs, s);} + +//!Instruction umull behavior method. +void ac_behavior( umull ){ UMULL(rdhi, rdlo, rm, rs, s);} + +//!Instruction ldr1 behavior method. +void ac_behavior( ldr1 ){ LDR(rd, rn); } + +//!Instruction ldrt1 behavior method. +void ac_behavior( ldrt1 ){ LDRT(rd, rn); } + +//!Instruction ldrb1 behavior method. +void ac_behavior( ldrb1 ){ LDRB(rd, rn); } + +//!Instruction ldrbt1 behavior method. +void ac_behavior( ldrbt1 ){ LDRBT(rd, rn); } + +//!Instruction str1 behavior method. +void ac_behavior( str1 ){ STR(rd, rn); } + +//!Instruction strt1 behavior method. +void ac_behavior( strt1 ){ STRT(rd, rn); } + +//!Instruction strb1 behavior method. +void ac_behavior( strb1 ){ STRB(rd, rn); } + +//!Instruction strbt1 behavior method. +void ac_behavior( strbt1 ){ STRBT(rd, rn); } + +//!Instruction ldr2 behavior method. +void ac_behavior( ldr2 ){ LDR(rd, rn); } + +//!Instruction ldrt2 behavior method. +void ac_behavior( ldrt2 ){ LDRT(rd, rn); } + +//!Instruction ldrb2 behavior method. +void ac_behavior( ldrb2 ){ LDRB(rd, rn); } + +//!Instruction ldrbt2 behavior method. +void ac_behavior( ldrbt2 ){ LDRBT(rd, rn); } + +//!Instruction str2 behavior method. +void ac_behavior( str2 ){ STR(rd, rn); } + +//!Instruction strt2 behavior method. +void ac_behavior( strt2 ){ STRT(rd, rn); } + +//!Instruction strb2 behavior method. +void ac_behavior( strb2 ){ STRB(rd, rn); } + +//!Instruction strbt2 behavior method. +void ac_behavior( strbt2 ){ STRBT(rd, rn); } + +//!Instruction ldrh behavior method. +void ac_behavior( ldrh ){ LDRH(rd, rn); } + +//!Instruction ldrsb behavior method. +void ac_behavior( ldrsb ){ LDRSB(rd, rn); } + +//!Instruction ldrsh behavior method. +void ac_behavior( ldrsh ){ LDRSH(rd, rn); } + +//!Instruction strh behavior method. +void ac_behavior( strh ){ STRH(rd, rn); } + +//!Instruction ldm behavior method. +void ac_behavior( ldm ){ LDM(rlist,r); } + +//!Instruction stm behavior method. +void ac_behavior( stm ){ STM(rn, rlist, r); } + +//!Instruction cdp behavior method. +void ac_behavior( cdp ){ CDP();} + +//!Instruction mcr behavior method. +void ac_behavior( mcr ){ MCR();} + +//!Instruction mrc behavior method. +void ac_behavior( mrc ){ MRC();} + +//!Instruction ldc behavior method. +void ac_behavior( ldc ){ LDC();} + +//!Instruction stc behavior method. +void ac_behavior( stc ){ STC();} + +//!Instruction bkpt behavior method. +void ac_behavior( bkpt ){ + fprintf(stderr,"Warning: BKPT instruction is not implemented in this model. PC=%X\n", ac_pc.read()); +} + +//!Instruction swi behavior method. +void ac_behavior( swi ){ +#ifdef SYSTEM_MODEL + service_interrupt(EXCEPTION_SWI); +#else + dprintf("Instruction: SWI\n"); + if (swinumber == 0) { + // New ABI (EABI), expected syscall number is in r7 + unsigned sysnum = RB_read(7) + 0x900000; + dprintf("EABI Syscall number: 0x%X\t(%d)\n", RB_read(7), RB_read(7)); + if (syscall.process_syscall(sysnum) == -1) { + fprintf(stderr, "Warning: A syscall not implemented in this model was called.\n\tCaller address: 0x%X\n\tSyscall number: 0x%X\t%d\n", (unsigned int)ac_pc, sysnum, sysnum); + } + // Old ABI (syscall encoded in instruction) + } else { + dprintf("Syscall number: 0x%X\t%d\n", swinumber, swinumber); + if (syscall.process_syscall(swinumber) == -1) { + fprintf(stderr, "Warning: A syscall not implemented in this model was called.\n\tCaller address: 0x%X\n\tSWI number: 0x%X\t(%d)\n", (unsigned int)ac_pc, swinumber, swinumber); + } + } +#endif +} + +//!Instruction clz behavior method. +void ac_behavior( clz ){ CLZ(rd, rm);} + +//!Instruction mrs behavior method. +void ac_behavior( mrs ){ MRS(rd,r,zero3,subop2,func2,subop1,rm,fieldmask);} + +//!Instruction msr1 behavior method. +void ac_behavior( msr1 ){ + unsigned in = RB_read(rm); + unsigned res; + + dprintf("Instruction: MSR\n"); + // Write to CPSR + if (r == 0) { + res = readCPSR(); + if (in_a_privileged_mode()) { + if (fieldmask & 1) { + res &= ~0xFF; + res |= (in & 0xFF); + } + if (fieldmask & (1 << 1)) { + res &= ~0xFF00; + res |= (in & 0xFF00); + } + if (fieldmask & (1 << 2)) { + res &= ~0xFF0000; + res |= (in & 0xFF0000); + } + } + if (fieldmask & (1 << 3)) { + res &= ~0xFF000000; + res |= (in & 0xFF000000); + } + writeCPSR(res); + dprintf(" * CPSR <= 0x%08X\n", res); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n FIQ disable" + "=0x%X, IRQ disable=0x%X, Thumb=0x%X\n",flags.N,flags.Z, + flags.C,flags.V, arm_proc_mode.fiq, arm_proc_mode.irq, + arm_proc_mode.thumb); + dprintf(" * Processor mode <= %s MODE\n", cur_mode_str()); + } else { // r == 1, write to SPSR + res = readSPSR(); + if (fieldmask & 1) { + res &= ~0xFF; + res |= (in & 0xFF); + } + if (fieldmask & (1 << 1)) { + res &= ~0xFF00; + res |= (in & 0xFF00); + } + if (fieldmask & (1 << 2)) { + res &= ~0xFF0000; + res |= (in & 0xFF0000); + } + if (fieldmask & (1 << 3)) { + res &= ~0xFF000000; + res |= (in & 0xFF000000); + } + writeSPSR(res); + dprintf(" * SPSR <= 0x%08X\n", res); + } +} + +//!Instruction msr2 behavior method. +void ac_behavior( msr2 ){ + arm_isa::reg_t temp; + temp.entire = imm8; + unsigned in = RotateRight(rotate*2, temp).entire; + unsigned res; + dprintf("Instruction: MSR\n"); + // Write to CPSR + if (r == 0) { + res = readCPSR(); + if (in_a_privileged_mode()) { + if (fieldmask & 1) { + res &= ~0xFF; + res |= (in & 0xFF); + } + if (fieldmask & (1 << 1)) { + res &= ~0xFF00; + res |= (in & 0xFF00); + } + if (fieldmask & (1 << 2)) { + res &= ~0xFF0000; + res |= (in & 0xFF0000); + } + } + if (fieldmask & (1 << 3)) { + res &= ~0xFF000000; + res |= (in & 0xFF000000); + } + writeCPSR(res); + dprintf(" * CPSR <= 0x%08X\n", res); + dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n FIQ disable" + "=0x%X, IRQ disable=0x%X, Thumb=0x%X\n",flags.N,flags.Z, + flags.C,flags.V, arm_proc_mode.fiq, arm_proc_mode.irq, + arm_proc_mode.thumb); + dprintf(" * Processor mode <= %s MODE\n", cur_mode_str()); + } else { // r == 1, write to SPSR + res = readSPSR(); + if (fieldmask & 1) { + res &= ~0xFF; + res |= (in & 0xFF); + } + if (fieldmask & (1 << 1)) { + res &= ~0xFF00; + res |= (in & 0xFF00); + } + if (fieldmask & (1 << 2)) { + res &= ~0xFF0000; + res |= (in & 0xFF0000); + } + if (fieldmask & (1 << 3)) { + res &= ~0xFF000000; + res |= (in & 0xFF000000); + } + writeSPSR(res); + dprintf(" * SPSR <= 0x%08X\n", res); + } +} + +//!Instruction ldrd2 behavior method. +void ac_behavior( ldrd ){ LDRD(rd, rn); } + +//!Instruction ldrd2 behavior method. +void ac_behavior( strd ){ STRD(rd, rn); } + +//!Instruction dsmla behavior method. +void ac_behavior( dsmla ){ DSMLA(drd, drn); } + +//!Instruction dsmlal behavior method. +void ac_behavior( dsmlal ){ + fprintf(stderr,"Warning: SMLAL instruction is not implemented in this model. PC=%X\n", ac_pc.read()); +} + +//!Instruction dsmul behavior method. +void ac_behavior( dsmul ){ DSMUL(drd); } + +//!Instruction dsmlaw behavior method. +void ac_behavior( dsmlaw ){ + fprintf(stderr,"Warning: SMLAW instruction is not implemented in this model. PC=%X\n", ac_pc.read()); +} + +//!Instruction dsmulw behavior method. +void ac_behavior( dsmulw ){ + fprintf(stderr,"Warning: SMULW instruction is not implemented in this model. PC=%X\n", ac_pc.read()); +} + +void ac_behavior( end ) { } diff --git a/pdl/arm/arm_isa_helper.H b/pdl/arm/arm_isa_helper.H new file mode 100644 index 0000000..3d05f16 --- /dev/null +++ b/pdl/arm/arm_isa_helper.H @@ -0,0 +1,603 @@ +/** + * @file arm_isa_helper.H + * @author Rafael Auler + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Apr 2012 + * + * @brief This is a helper header file included directly + * in the generated arm_isa.H file. Here we put + * data structures and functions used throughout + * the arm_isa.cpp (arm instruction behaviors). + * + * @attention Copyright (C) 2002-2012 --- The ArchC Team + * + */ + +// Abstracts away the different ARM processor modes +class processor_mode { +public: + static const unsigned int USER_MODE = 0x10; // 0b10000; + static const unsigned int FIQ_MODE = 0x11; // 0b10001; + static const unsigned int IRQ_MODE = 0x12; // 0b10010; + static const unsigned int SUPERVISOR_MODE = 0x13; // 0b10011; + static const unsigned int ABORT_MODE = 0x17; // 0b10111; + static const unsigned int UNDEFINED_MODE = 0x1B; // 0b11011; + static const unsigned int SYSTEM_MODE = 0x1F; // 0b11111; + static const unsigned int MODE_MASK = 0x1F; // 0b11111; + + bool fiq, irq, thumb; + unsigned int mode; + + // Initializes with: + // FIQ enabled (CPSR FIQ disable bit set = false) + // IRQ enabled + // Thumb disabled + // User mode + processor_mode() : fiq(false), irq(false), thumb(false), mode (USER_MODE) {} +}; + +enum exception_type { + EXCEPTION_RESET, EXCEPTION_UNDEFINED_INSTR, EXCEPTION_SWI, + EXCEPTION_PREFETCH_ABORT, EXCEPTION_DATA_ABORT, EXCEPTION_IRQ, + EXCEPTION_FIQ +}; + +processor_mode arm_proc_mode; + +// Useful abstract data types defining ARM flags and register access +typedef struct flag_s { + bool N; // Negative + bool Z; // Zero + bool C; // Carry + bool V; // Overflow + bool Q; // DSP + bool T; // Thumb +} flag_t; + +typedef union { + int8_t byte[4]; + int32_t entire; +} reg_t; + +typedef union { + int32_t reg[2]; + int64_t hilo; +} r64bit_t; + +// Global instances used throughout the model. +flag_t flags; +bool execute; + +reg_t dpi_shiftop; +bool dpi_shiftopcarry; + +reg_t ls_address; +reg_t lsm_startaddress; +reg_t lsm_endaddress; + +reg_t OP1; +reg_t OP2; + +// When rn is in rlist. e.g: push {sp, ...} +reg_t lsm_oldrn; + + +// Functions used to determine which register to access +// in case of using other processor modes +void bypass_write(unsigned address, unsigned datum) { + if (arm_proc_mode.mode == processor_mode::USER_MODE || + arm_proc_mode.mode == processor_mode::SYSTEM_MODE) { + RB.write(address, datum); + return; + } + switch (arm_proc_mode.mode) { + case processor_mode::FIQ_MODE: + switch (address) { + case 14: + R14_fiq = datum; + break; + case 13: + R13_fiq = datum; + break; + case 12: + R12_fiq = datum; + break; + case 11: + R11_fiq = datum; + break; + case 10: + R10_fiq = datum; + break; + case 9: + R9_fiq = datum; + break; + case 8: + R8_fiq = datum; + break; + default: + RB .write(address, datum); + break; + } + break; + case processor_mode::IRQ_MODE: + if (address == 14) + R14_irq = datum; + else if (address == 13) + R13_irq = datum; + else + RB .write(address, datum); + break; + case processor_mode::SUPERVISOR_MODE: + if (address == 14) + R14_svc = datum; + else if (address == 13) + R13_svc = datum; + else + RB .write(address, datum); + break; + case processor_mode::ABORT_MODE: + if (address == 14) + R14_abt = datum; + else if (address == 13) + R13_abt = datum; + else + RB .write(address, datum); + break; + case processor_mode::UNDEFINED_MODE: + if (address == 14) + R14_und = datum; + else if (address == 13) + R13_und = datum; + else + RB .write(address, datum); + break; + } +} + +unsigned bypass_read(unsigned address) { + if (arm_proc_mode.mode == processor_mode::USER_MODE || + arm_proc_mode.mode == processor_mode::SYSTEM_MODE) + return RB .read(address); + switch (arm_proc_mode.mode) { + case processor_mode::FIQ_MODE: + switch (address) { + case 14: + return R14_fiq; + break; + case 13: + return R13_fiq; + break; + case 12: + return R12_fiq; + break; + case 11: + return R11_fiq; + break; + case 10: + return R10_fiq; + break; + case 9: + return R9_fiq; + break; + case 8: + return R8_fiq; + break; + default: + return RB.read(address); + break; + } + break; + case processor_mode::IRQ_MODE: + if (address == 14) + return R14_irq; + else if (address == 13) + return R13_irq; + else + return RB.read(address); + break; + case processor_mode::SUPERVISOR_MODE: + if (address == 14) + return R14_svc; + else if (address == 13) + return R13_svc; + else + return RB.read(address); + break; + case processor_mode::ABORT_MODE: + if (address == 14) + return R14_abt; + else if (address == 13) + return R13_abt; + else + return RB.read(address); + break; + case processor_mode::UNDEFINED_MODE: + if (address == 14) + return R14_und; + else if (address == 13) + return R13_und; + else + return RB.read(address); + break; + } + return ~((unsigned)0); +} + +//! User defined macros to access a single bit +#define isBitSet(variable, position) (((variable & (1 << (position))) != 0) ? true : false) +#define getBit(variable, position) (((variable & (1 << (position))) != 0) ? true : false) +#define setBit(variable, position) variable = variable | (1 << (position)) +#define clearBit(variable, position) variable = variable & (~(1 << (position))) + +//! Useful functions to easily describe arm instructions behavior +static inline reg_t ArithmeticShiftRight(int shiftamount, reg_t reg) { + reg_t tmp = reg; + tmp.entire = ((int32_t)tmp.entire) >> shiftamount; + return tmp; +} + +static inline reg_t RotateRight(int shiftamount, reg_t reg) { + reg_t ret; + ret.entire = (((uint32_t)reg.entire) >> shiftamount) | (((uint32_t)reg.entire) << (32 - shiftamount)); + return ret; +} + +static inline int32_t SignExtend(int32_t word, int word_length) { + const int32_t m = 1U << (word_length - 1); + int32_t x = (word) & ((1ULL << word_length) - 1); + return ((x ^ m) - m); +} + +static inline int LSM_CountSetBits(reg_t registerList) { + int i, count; + + count = 0; + for (i=0; i<16; i++) { // Verify limits for big/little endian + if (isBitSet(registerList.entire,i)) count++; + } + return count; +} + +inline reg_t CPSRBuild() { + reg_t CPSR; + + CPSR.entire = arm_proc_mode.mode; + if (arm_proc_mode.fiq) + setBit(CPSR.entire,6); // FIQ disable + if (arm_proc_mode.irq) + setBit(CPSR.entire,7); // IRQ disable + if (arm_proc_mode.thumb) + setBit(CPSR.entire,5); // Thumb + if (flags.N) setBit(CPSR.entire,31); // N flag + else clearBit(CPSR.entire,31); + if (flags.Z) setBit(CPSR.entire,30); // Z flag + else clearBit(CPSR.entire,30); + if (flags.C) setBit(CPSR.entire,29); // C flag + else clearBit(CPSR.entire,29); + if (flags.V) setBit(CPSR.entire,28); // V flag + else clearBit(CPSR.entire,28); + if (flags.Q) setBit(CPSR.entire,27); // Q flag + else clearBit(CPSR.entire,27); + if (flags.T) setBit(CPSR.entire, 5); // T flag + + return CPSR; +} + +uint32_t readCPSR() { + return (uint32_t) CPSRBuild().entire; +} + +void writeCPSR(unsigned value) { + reg_t CPSR; + + CPSR.entire = value; + flags.N = (getBit(CPSR.entire,31))? true : false; + flags.Z = (getBit(CPSR.entire,30))? true : false; + flags.C = (getBit(CPSR.entire,29))? true : false; + flags.V = (getBit(CPSR.entire,28))? true : false; + flags.Q = (getBit(CPSR.entire,27))? true : false; + flags.T = (getBit(CPSR.entire,5))? true : false; + arm_proc_mode.fiq = getBit(CPSR.entire,6)? true : false; + arm_proc_mode.irq = getBit(CPSR.entire,7)? true : false; + arm_proc_mode.mode = value & processor_mode::MODE_MASK; +} + +// This function implements the transfer of the SPSR of the current processor +// mode to the CPSR, usually executed when exiting from an exception handler. +void SPSRtoCPSR() { + switch (arm_proc_mode.mode) { + case processor_mode::FIQ_MODE: + writeCPSR(SPSR_fiq); + break; + case processor_mode::IRQ_MODE: + writeCPSR(SPSR_irq); + break; + case processor_mode::SUPERVISOR_MODE: + writeCPSR(SPSR_svc); + break; + case processor_mode::ABORT_MODE: + writeCPSR(SPSR_abt); + break; + case processor_mode::UNDEFINED_MODE: + writeCPSR(SPSR_und); + break; + default: + printf("Invalid processor mode.\n"); + return; + } +} + +void writeSPSR(unsigned value) { + switch (arm_proc_mode.mode) { + case processor_mode::FIQ_MODE: + SPSR_fiq = value; + break; + case processor_mode::IRQ_MODE: + SPSR_irq = value; + break; + case processor_mode::SUPERVISOR_MODE: + SPSR_svc = value; + break; + case processor_mode::ABORT_MODE: + SPSR_abt = value; + break; + case processor_mode::UNDEFINED_MODE: + SPSR_und = value; + break; + } +} + +unsigned readSPSR() { + switch (arm_proc_mode.mode) { + case processor_mode::FIQ_MODE: + return SPSR_fiq; + case processor_mode::IRQ_MODE: + return SPSR_irq; + case processor_mode::SUPERVISOR_MODE: + return SPSR_svc; + case processor_mode::ABORT_MODE: + return SPSR_abt; + case processor_mode::UNDEFINED_MODE: + return SPSR_und; + } + return 0; +} + +bool in_a_privileged_mode() { + switch (arm_proc_mode.mode) { + case processor_mode::SYSTEM_MODE: + case processor_mode::FIQ_MODE: + case processor_mode::IRQ_MODE: + case processor_mode::SUPERVISOR_MODE: + case processor_mode::ABORT_MODE: + case processor_mode::UNDEFINED_MODE: + return true; + } + return false; +} + +const char * cur_mode_str() { + switch (arm_proc_mode.mode) { + case processor_mode::SYSTEM_MODE: + return "SYSTEM"; + case processor_mode::USER_MODE: + return "USER"; + case processor_mode::FIQ_MODE: + return "FIQ"; + case processor_mode::IRQ_MODE: + return "IRQ"; + case processor_mode::SUPERVISOR_MODE: + return "SUPERVISOR"; + case processor_mode::ABORT_MODE: + return "ABORT"; + case processor_mode::UNDEFINED_MODE: + return "UNDEFINED"; + } + return 0; +} + + +// Exception vector addresses +static const unsigned int RESET_ADDR = 0x00000000; +static const unsigned int RESET_ADDR_HI = 0xffff0000; +static const unsigned int UNDEFINED_ADDR = 0x00000004; +static const unsigned int UNDEFINED_ADDR_HI = 0xffff0004; +static const unsigned int SWI_ADDR = 0x00000008; +static const unsigned int SWI_ADDR_HI = 0xffff0008; +static const unsigned int PREFETCH_ABORT_ADDR = 0x0000000c; +static const unsigned int PREFETCH_ABORT_ADDR_HI = 0xffff000c; +static const unsigned int DATA_ABORT_ADDR = 0x00000010; +static const unsigned int DATA_ABORT_ADDR_HI = 0xffff0010; +static const unsigned int IRQ_ADDR = 0x00000018; +static const unsigned int IRQ_ADDR_HI = 0xffff0018; +static const unsigned int FIQ_ADDR = 0x0000001c; +static const unsigned int FIQ_ADDR_HI = 0xffff001c; + +// Whoever calls this interrupt, it must enforce correct exception priority, +// since we can't enforce this here. We simply service the first one to call +// this method. The correct exception priority is: +// Highest 1 Reset (async) +// 2 Data abort (async) +// 3 FIQ (instruction boundaries) +// 4 IRQ (instruction boundaries) +// 5 Prefetch abort (async) +// Lowest 6 Undefined instruction (async) +// SWI (sync) + +// Interrupt handler behavior for interrupt port inta. +void service_interrupt(unsigned excep_type) { + unsigned cpsr = readCPSR(); + + // FIQ disabled? + if ((cpsr & (1 << 6)) && excep_type == EXCEPTION_FIQ) + return; + + // IRQ disabled? + if ((cpsr & (1 << 7)) && excep_type == EXCEPTION_IRQ) + return; + + switch(excep_type) { + case EXCEPTION_RESET: + R14_svc = 0; + SPSR_svc = 0; + cpsr = cpsr & ~processor_mode::MODE_MASK; + cpsr = cpsr | processor_mode::SUPERVISOR_MODE; + cpsr = cpsr | (1 << 6); // disable FIQ +#ifdef HIGH_VECTOR + ac_pc = RESET_ADDR_HI; +#else + ac_pc = RESET_ADDR; +#endif + break; + case EXCEPTION_UNDEFINED_INSTR: + R14_und = ac_pc; // address of the next instruction after the undef + // instruction. we expect this to run only after a + // cycle of archc behavioral simulation has been + // completed, because ac_pc is set with pc+4 + // in the end of each cycle. + SPSR_und = cpsr; + cpsr = cpsr & ~processor_mode::MODE_MASK; + cpsr = cpsr | processor_mode::UNDEFINED_MODE; +#ifdef HIGH_VECTOR + ac_pc = UNDEFINED_ADDR_HI; +#else + ac_pc = UNDEFINED_ADDR; +#endif + break; + case EXCEPTION_SWI: + R14_svc = ac_pc; // remember ac_pc is pc+4 at each end of cycle + SPSR_svc = cpsr; + cpsr = cpsr & ~processor_mode::MODE_MASK; + cpsr = cpsr | processor_mode::SUPERVISOR_MODE; +#ifdef HIGH_VECTOR + ac_pc = SWI_ADDR_HI; +#else + ac_pc = SWI_ADDR; +#endif + break; + case EXCEPTION_PREFETCH_ABORT: + R14_abt = ac_pc; // remember ac_pc is pc+4 at each end of cycle + SPSR_abt = cpsr; + cpsr = cpsr & ~processor_mode::MODE_MASK; + cpsr = cpsr | processor_mode::ABORT_MODE; +#ifdef HIGH_VECTOR + ac_pc = PREFETCH_ABORT_ADDR_HI; +#else + ac_pc = PREFETCH_ABORT_ADDR; +#endif + break; + case EXCEPTION_DATA_ABORT: + R14_abt = ac_pc + 4; // remember ac_pc is pc+4 at each end of + // cycle data aborts sets R14_abt to pc+8 + SPSR_abt = cpsr; + cpsr = cpsr & ~processor_mode::MODE_MASK; + cpsr = cpsr | processor_mode::ABORT_MODE; +#ifdef HIGH_VECTOR + ac_pc = DATA_ABORT_ADDR_HI; +#else + ac_pc = DATA_ABORT_ADDR; +#endif + break; + case EXCEPTION_IRQ: + R14_irq = ac_pc + 4; // remember ac_pc is pc+4 at each end of cycle + // or the address of a branch target. + // irq sets R14_irq to next instruction to be + // executed +4 + SPSR_irq = cpsr; + cpsr = cpsr & ~processor_mode::MODE_MASK; + cpsr = cpsr | processor_mode::IRQ_MODE; +#ifdef HIGH_VECTOR + ac_pc = IRQ_ADDR_HI; +#else + ac_pc = IRQ_ADDR; +#endif + break; + case EXCEPTION_FIQ: + R14_fiq = ac_pc + 4; // remember ac_pc is pc+4 at each end of cycle + // or the address of a branch target. + // irq sets R14_irq to next instruction to be + // executed +4 + SPSR_fiq = cpsr; + cpsr = cpsr & ~processor_mode::MODE_MASK; + cpsr = cpsr | processor_mode::FIQ_MODE; + cpsr = cpsr | (1 << 6); // disable FIQ +#ifdef HIGH_VECTOR + ac_pc = FIQ_ADDR_HI; +#else + ac_pc = FIQ_ADDR; +#endif + break; + default: + assert(0 && "Unknown interrupt type!"); + abort(); + break; + } + cpsr = cpsr & ~(1 << 5); // execute in ARM state + cpsr = cpsr | (1 << 7); // disable normal interrupts + + writeCPSR(cpsr); +} + +// Support functions used in arm_isa.cpp to avoid code repetition + +void ADD(int rd, int rn, bool s); +void ADC(int rd, int rn, bool s); +void AND(int rd, int rn, bool s); +void B(int h, int offset); +void BX(int rm); +void BIC(int rd, int rn, bool s); +void CDP(); +void CLZ(int rd, int rm); +void CMN(int rn); +void CMP(int rn); +void EOR(int rd, int rn, bool s); +void LDC(); +void LDM(int rlist, bool r); +void LDR(int rd, int rn); +void LDRB(int rd, int rn); +void LDRBT(int rd, int rn); +void LDRD(int rd, int rn); +void LDRH(int rd, int rn); +void LDRSB(int rd, int rn); +void LDRSH(int rd, int rn); +void LDRT(int rd, int rn); +void MCR(); +void MLA(int rd, int rn, int rm, int rs, bool s); +void MOV(int rd, bool s); +void MRC(); +void MRS(int rd, bool r, int zero3, int subop2, int func2, int subop1, int rm, + int field); +void MUL(int rd, int rm, int rs, bool s); +void MVN(int rd, bool s); +void ORR(int rd, int rn, bool s); +void RSB(int rd, int rn, bool s); +void RSC(int rd, int rn, bool s); +void SBC(int rd, int rn, bool s); +void SMLAL(int rdhi, int rdlo, int rm, int rs, bool s); +void SMULL(int rdhi, int rdlo, int rm, int rs, bool s); +void STC(); +void STM(int rn, int rlist, unsigned r); +void STR(int rd, int rn); +void STRB(int rd, int rn); +void STRBT(int rd, int rn); +void STRD(int rd, int rn); +void STRH(int rd, int rn); +void STRT(int rd, int rn); +void SUB(int rd, int rn, bool s); +void SWP(int rd, int rn, int rm); +void SWPB(int rd, int rn, int rm); +void TEQ(int rn); +void TST(int rn); +void UMLAL(int rdhi, int rdlo, int rm, int rs, bool s); +void UMULL(int rdhi, int rdlo, int rm, int rs, bool s); +void DSMLA(int rd, int rn); +void DSMUL(int rd); + diff --git a/pdl/arm/arm_nonblock.ac b/pdl/arm/arm_nonblock.ac new file mode 100644 index 0000000..0c7c6f9 --- /dev/null +++ b/pdl/arm/arm_nonblock.ac @@ -0,0 +1,48 @@ +/** + * @file arm.ac + * @author Danilo Marcolin Caravana + * Rafael Auler + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Apr 2012 + * + * @brief The ArchC ARMv5e functional model. + * + * @attention Copyright (C) 2002-2012 --- The ArchC Team + * + */ + +AC_ARCH(arm){ + ac_tlm2_nb_port MEM:512M; + + //ac_icache IC("2w", 128, 32, "wb", "fifo"); + //ac_dcache DC("2w", 512, 32, "wt", "fifo"); + + ac_icache IC("2w", 128, 8, "wt", "fifo"); + ac_dcache DC("2w", 128, 8, "wt", "fifo"); + + ac_tlm2_intr_port intr_port; + + ac_regbank RB:16; + // ac_tlm_intr_port inta; // system level interrupt port + ac_reg R14_irq, R14_fiq, R14_svc, R14_abt, R14_und, R13_irq, R13_svc; + ac_reg R13_abt, R13_und, R13_fiq; + ac_reg SPSR_irq, SPSR_fiq, SPSR_svc, SPSR_abt, SPSR_und; + // FIQ private regs + ac_reg R12_fiq, R11_fiq, R10_fiq, R9_fiq, R8_fiq; + ac_wordsize 32; + ac_reg id; + ARCH_CTOR(arm) { + ac_isa("arm_isa.ac"); + set_endian("little"); + IC.bindTo(MEM); + DC.bindTo(MEM); + }; +}; \ No newline at end of file diff --git a/pdl/arm/arm_syscall.H b/pdl/arm/arm_syscall.H new file mode 100644 index 0000000..4f27849 --- /dev/null +++ b/pdl/arm/arm_syscall.H @@ -0,0 +1,47 @@ +/****************************************************** + * ArchC Architecture Dependent Syscall header file. * + * This file is automatically generated by ArchC * + * WITHOUT WARRANTY OF ANY KIND, either express * + * or implied. * + * For more information on ArchC, please visit: * + * http://www.archc.org * + * * + * The ArchC Team * + * Computer Systems Laboratory (LSC) * + * IC-UNICAMP * + * http://www.lsc.ic.unicamp.br * + ******************************************************/ + + +#ifndef arm_SYSCALL_H +#define arm_SYSCALL_H + +#include "arm_arch.H" +#include "arm_arch_ref.H" +#include "arm_parms.H" +#include "ac_syscall.H" + +//arm system calls +class arm_syscall : public ac_syscall, public arm_arch_ref +{ +public: + arm_syscall(arm_arch& ref) : ac_syscall(ref, arm_parms::AC_RAMSIZE), arm_arch_ref(ref) {}; + virtual ~arm_syscall() {}; + + void get_buffer(int argn, unsigned char* buf, unsigned int size); + void set_buffer(int argn, unsigned char* buf, unsigned int size); + void set_buffer_noinvert(int argn, unsigned char* buf, unsigned int size); + void host2guestmemcpy(uint32_t dst, unsigned char *src, unsigned int size); + void guest2hostmemcpy(unsigned char *dst, uint32_t src, unsigned int size); + int get_int(int argn); + void set_int(int argn, int val); + void return_from_syscall(); + void set_prog_args(int argc, char **argv); + int *get_syscall_table(); + void set_pc(unsigned val); + void set_return(unsigned val); + unsigned get_return(); + bool is_mmap_anonymous(uint32_t flags); +}; + +#endif diff --git a/pdl/arm/arm_syscall.cpp b/pdl/arm/arm_syscall.cpp new file mode 100644 index 0000000..1277f55 --- /dev/null +++ b/pdl/arm/arm_syscall.cpp @@ -0,0 +1,234 @@ +/** + * @file arm_syscall.cpp + * @author Danilo Marcolin Caravana + * Rafael Auler + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Apr 2012 + * + * @brief The ArchC ARMv5e functional model. + * + * @attention Copyright (C) 2002-2012 --- The ArchC Team + * + */ + +#include "arm_syscall.H" + +using namespace arm_parms; + +void arm_syscall::get_buffer(int argn, unsigned char* buf, unsigned int size) { + unsigned int addr = RB.read(argn); + + for (unsigned int i = 0; iread_byte(addr); + } +} + +void arm_syscall::guest2hostmemcpy(unsigned char *dst, uint32_t src, + unsigned int size) { + for (unsigned int i = 0; i < size; i++) { + dst[i] = DATA_PORT->read_byte(src++); + } +} + +void arm_syscall::set_buffer(int argn, unsigned char* buf, unsigned int size) { + unsigned int addr = RB.read(argn); + + for (unsigned int i = 0; iwrite_byte(addr, buf[i]); + //printf("\nMEM[%d]=%d", addr, buf[i]); + } +} + +void arm_syscall::host2guestmemcpy(uint32_t dst, unsigned char *src, + unsigned int size) { + for (unsigned int i = 0; i < size; i++) { + DATA_PORT->write_byte(dst++, src[i]); + } +} + +void arm_syscall::set_buffer_noinvert(int argn, unsigned char* buf, unsigned int size) { + unsigned int addr = RB.read(argn); + + for (unsigned int i = 0; iwrite(addr, *(unsigned int *) &buf[i]); + } +} + +void arm_syscall::set_pc(unsigned val) { + RB.write(15, val); + ac_pc.write(val); +} + +void arm_syscall::set_return(unsigned val) { + RB.write(14, val); +} + +unsigned arm_syscall::get_return() { + return (unsigned) RB.read(14); +} + +int arm_syscall::get_int(int argn) { + return RB.read(argn); +} + +void arm_syscall::set_int(int argn, int val) { + RB.write(argn, val); +} + +void arm_syscall::return_from_syscall() { + ac_pc = RB.read(14); +} + +bool arm_syscall::is_mmap_anonymous(uint32_t flags) { + return flags & 0x20; +} + +void arm_syscall::set_prog_args(int argc, char **argv) { + int i, j, base; + + unsigned int ac_argv[30]; + char ac_argstr[512]; + + base = AC_RAM_END - 512; + + + for (i=0, j=0; iwrite(AC_RAM_END-512-124, argc); + } + + if (ref.ac_dyn_loader.get_init_arraysz() != 0) { + set_return(0x80); + } + + if (ref.ac_dyn_loader.is_glibc()) { + + //Set a1 to our finalization hook + RB.write(0, 0x84); + + } else { + /* Configure for newlib with libac_sysc */ + //Set a1 to argument count + RB.write(0, argc); + + //Set a2 to the string pointers + RB.write(1, AC_RAM_END-512-120); + } + +} + + +#define ARM__NR_SYSCALL_BASE 0x900000 + +#define ARM__NR_restart_syscall (ARM__NR_SYSCALL_BASE+ 0) +#define ARM__NR_exit (ARM__NR_SYSCALL_BASE+ 1) +#define ARM__NR_fork (ARM__NR_SYSCALL_BASE+ 2) +#define ARM__NR_read (ARM__NR_SYSCALL_BASE+ 3) +#define ARM__NR_write (ARM__NR_SYSCALL_BASE+ 4) +#define ARM__NR_open (ARM__NR_SYSCALL_BASE+ 5) +#define ARM__NR_close (ARM__NR_SYSCALL_BASE+ 6) +#define ARM__NR_creat (ARM__NR_SYSCALL_BASE+ 8) +#define ARM__NR_time (ARM__NR_SYSCALL_BASE+ 13) +#define ARM__NR_lseek (ARM__NR_SYSCALL_BASE+ 19) +#define ARM__NR_getpid (ARM__NR_SYSCALL_BASE+ 20) +#define ARM__NR_access (ARM__NR_SYSCALL_BASE+ 33) +#define ARM__NR_kill (ARM__NR_SYSCALL_BASE+ 37) +#define ARM__NR_dup (ARM__NR_SYSCALL_BASE+ 41) +#define ARM__NR_times (ARM__NR_SYSCALL_BASE+ 43) +#define ARM__NR_brk (ARM__NR_SYSCALL_BASE+ 45) +#define ARM__NR_gettimeofday (ARM__NR_SYSCALL_BASE+ 78) +#define ARM__NR_settimeofday (ARM__NR_SYSCALL_BASE+ 79) +#define ARM__NR_mmap (ARM__NR_SYSCALL_BASE+ 90) +#define ARM__NR_munmap (ARM__NR_SYSCALL_BASE+ 91) +#define ARM__NR_socketcall (ARM__NR_SYSCALL_BASE+102) +#define ARM__NR_stat (ARM__NR_SYSCALL_BASE+106) +#define ARM__NR_lstat (ARM__NR_SYSCALL_BASE+107) +#define ARM__NR_fstat (ARM__NR_SYSCALL_BASE+108) +#define ARM__NR_uname (ARM__NR_SYSCALL_BASE+122) +#define ARM__NR__llseek (ARM__NR_SYSCALL_BASE+140) +#define ARM__NR_readv (ARM__NR_SYSCALL_BASE+145) +#define ARM__NR_writev (ARM__NR_SYSCALL_BASE+146) +#define ARM__NR_mmap2 (ARM__NR_SYSCALL_BASE+192) +#define ARM__NR_stat64 (ARM__NR_SYSCALL_BASE+195) +#define ARM__NR_lstat64 (ARM__NR_SYSCALL_BASE+196) +#define ARM__NR_fstat64 (ARM__NR_SYSCALL_BASE+197) +#define ARM__NR_getuid32 (ARM__NR_SYSCALL_BASE+199) +#define ARM__NR_getgid32 (ARM__NR_SYSCALL_BASE+200) +#define ARM__NR_geteuid32 (ARM__NR_SYSCALL_BASE+201) +#define ARM__NR_getegid32 (ARM__NR_SYSCALL_BASE+202) +#define ARM__NR_fcntl64 (ARM__NR_SYSCALL_BASE+221) +#define ARM__NR_exit_group (ARM__NR_SYSCALL_BASE+248) + + +int *arm_syscall::get_syscall_table() { + static int syscall_table[] = { + ARM__NR_restart_syscall, + ARM__NR_exit, + ARM__NR_fork, + ARM__NR_read, + ARM__NR_write, + ARM__NR_open, + ARM__NR_close, + ARM__NR_creat, + ARM__NR_time, + ARM__NR_lseek, + ARM__NR_getpid, + ARM__NR_access, + ARM__NR_kill, + ARM__NR_dup, + ARM__NR_times, + ARM__NR_brk, + ARM__NR_mmap, + ARM__NR_munmap, + ARM__NR_stat, + ARM__NR_lstat, + ARM__NR_fstat, + ARM__NR_uname, + ARM__NR__llseek, + ARM__NR_readv, + ARM__NR_writev, + ARM__NR_mmap2, + ARM__NR_stat64, + ARM__NR_lstat64, + ARM__NR_fstat64, + ARM__NR_getuid32, + ARM__NR_getgid32, + ARM__NR_geteuid32, + ARM__NR_getegid32, + ARM__NR_fcntl64, + ARM__NR_exit_group, + ARM__NR_socketcall, + ARM__NR_gettimeofday, + ARM__NR_settimeofday, + 666 /* clock_gettime = unavailable */ + }; + return syscall_table; +} diff --git a/pdl/arm/arm_to_archc.relmap b/pdl/arm/arm_to_archc.relmap new file mode 100644 index 0000000..d1ce62c --- /dev/null +++ b/pdl/arm/arm_to_archc.relmap @@ -0,0 +1,18 @@ +# This file contains a one-to-one mapping between ARM ABI relocation +# codes and ArchC's generated linker relocation codes. Its intended +# use is to perform a conversion using the acrelconvert tool. + +# R_ARM_RELATIVE +23 = 1 +# R_ARM_COPY +20 = 2 +# R_ARM_JUMPSLOT +22 = 3 +# R_ARM_GLOBDAT +21 = 4 +# R_ARM_ABS32 +2 = 7 +# R_ARM_REL32 +3 = 10 + +# End of file diff --git a/pdl/arm/compiler_info.ac b/pdl/arm/compiler_info.ac new file mode 100644 index 0000000..e154516 --- /dev/null +++ b/pdl/arm/compiler_info.ac @@ -0,0 +1,439 @@ +// ARM C Compiler Backend Information File +// Part of ARM ArchC Model + +//====================-- Machine specific rules --============================// + + + +//=====================-- Registers definitions --============================// + +define registers GPR:regs as ( + r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 +); + +// Current Program Status Register +define registers CPSR:regs as ( SR ); // Status registers + +//===========================-- ABI stuff --==================================// + +redefine operand tgtimm size to 8; + +define abi as ( + define callee save registers as (r4 r5 r6 r7); + define reserved registers as (r9 r10 r13 r14 r15); + define auxiliar registers as (r9 r10); + //define calling convention for int as stack size 4 alignment 4; + define calling convention for int as (r0 r1 r2 r3); + define calling convention for int as stack size 4 alignment 4; + define return convention for int as (r0 r1); + define programcounter register as r15; + define stackpointer register as r13; + define framepointer register as r11; + define return register as r14; + define stack grows down alignment 8; + define pcoffset -8; +); + +//==================-- Instruction semantic fragments --======================// + +//====-- Adressing mode fragments -====// + +// Simple addressing mode frag +define semantic fragment SimpleAddrMode as ( + Op5:GPR; +); + +// Register shifted by imm +define semantic fragment RegShiftedAddrMode as ( + (shl Op5:GPR imm:Op7:tgtimm); +); + +// Register right shifted by imm +define semantic fragment RegRightShiftedAddrMode as ( + (shr Op5:GPR imm:Op7:tgtimm); +); + +// Register arithmetic right shifted by imm +define semantic fragment RegARightShiftedAddrMode as ( + (asr Op5:GPR imm:Op7:tgtimm); +); + +define semantic fragment RegRotRightAddrMode as ( + (ror Op5:GPR imm:Op7:tgtimm); +); + +// Register shifted by imm +define semantic fragment RegShiftedAddr2Mode as ( + (shl Op5:GPR Op7:GPR); +); + +// Register right shifted by imm +define semantic fragment RegRightShiftedAddr2Mode as ( + (shr Op5:GPR Op7:GPR); +); + +// Register arithmetic right shifted by imm +define semantic fragment RegARightShiftedAddr2Mode as ( + (asr Op5:GPR Op7:GPR); +); + +define semantic fragment RegRotRightAddr2Mode as ( + (ror Op5:GPR Op7:GPR); +); + +// Register shifted right by 1 +define semantic fragment RegRotAddrMode as ( + (shr Op5:GPR const:int:1); +); + +// Immediate +define semantic fragment ImmAddrMode as ( + imm:Op5:tgtimm; +); + +//=======================-- Instructions definitions --=======================// + +// Branch instructions +define instruction b semantic as ( + let Op1 = "" in + (jump imm:Op2:int); + let Op1 = "lt" in + (cjump const:cond:lt SR:CPSR imm:Op2:int); + let Op1 = "gt" in + (cjump const:cond:gt SR:CPSR imm:Op2:int); + let Op1 = "le" in + (cjump const:cond:le SR:CPSR imm:Op2:int); + let Op1 = "ge" in + (cjump const:cond:ge SR:CPSR imm:Op2:int); + let Op1 = "lo" in + (cjump const:cond:ult SR:CPSR imm:Op2:int); + let Op1 = "hi" in + (cjump const:cond:ugt SR:CPSR imm:Op2:int); + let Op1 = "hs" in + (cjump const:cond:uge SR:CPSR imm:Op2:int); + let Op1 = "ls" in + (cjump const:cond:ule SR:CPSR imm:Op2:int); + let Op1 = "ne" in + (cjump const:cond:ne SR:CPSR imm:Op2:int); + let Op1 = "eq" in + (cjump const:cond:eq SR:CPSR imm:Op2:int); +) cost 1; +define instruction b semantic as ( + let Op1 = "" in + (call imm:Op2:int); +) cost 1; +define instruction bx semantic as ( + let Op1 = "" in + (jump Op2:GPR); +) cost 1; +define instruction blx2 semantic as ( + let Op1 = "" in + (call Op2:GPR); +) cost 1; + +// Data processing instructions + +//====-- AND --====// +define instruction and1 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (and Op4:GPR SimpleAddrMode:fragment)); +) cost 1; +define instruction and1 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (and Op4:GPR RegShiftedAddrMode:fragment)); +) cost 1; +define instruction and1 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (and Op4:GPR RegRotAddrMode:fragment)); +) cost 1; +define instruction and2 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (and Op4:GPR RegShiftedAddr2Mode:fragment)); +) cost 1; +define instruction and3 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (and Op4:GPR ImmAddrMode:fragment)); +) cost 1; + +//====-- EOR --====// +define instruction eor1 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (xor Op4:GPR SimpleAddrMode:fragment)); +) cost 1; +define instruction eor1 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (xor Op4:GPR RegShiftedAddrMode:fragment)); +) cost 1; +define instruction eor1 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (xor Op4:GPR RegRotAddrMode:fragment)); +) cost 1; +define instruction eor2 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (xor Op4:GPR RegShiftedAddr2Mode:fragment)); +) cost 1; +define instruction eor3 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (xor Op4:GPR ImmAddrMode:fragment)); +) cost 1; + +//====-- SUB --====// +define instruction sub1 semantic as ( +let Op1 = "", Op2 = "" in + (transfer Op3:GPR (- Op4:GPR SimpleAddrMode:fragment)); +) cost 1; +define instruction sub1 semantic as ( +let Op1 = "", Op2 = "" in + (transfer Op3:GPR (- Op4:GPR RegShiftedAddrMode:fragment)); +) cost 1; +define instruction sub1 semantic as ( +let Op1 = "", Op2 = "" in + (transfer Op3:GPR (- Op4:GPR RegRotAddrMode:fragment)); +) cost 1; +define instruction sub2 semantic as ( +let Op1 = "", Op2 = "" in + (transfer Op3:GPR (- Op4:GPR RegShiftedAddr2Mode:fragment)); +) cost 1; +define instruction sub3 semantic as ( +let Op1 = "", Op2 = "" in + (transfer Op3:GPR (- Op4:GPR ImmAddrMode:fragment)); +) cost 1; + +//====-- ADD --====// +define instruction add1 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (+ Op4:GPR SimpleAddrMode:fragment)); +) cost 1; +define instruction add1 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (+ Op4:GPR RegShiftedAddrMode:fragment)); +) cost 1; +define instruction add1 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (+ Op4:GPR RegRotAddrMode:fragment)); +) cost 1; +define instruction add1 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (pcrelative Op4:GPR)); +) cost 1; +define instruction add2 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (+ Op4:GPR RegShiftedAddr2Mode:fragment)); +) cost 1; +define instruction add3 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (+ Op4:GPR ImmAddrMode:fragment)); +) cost 1; +define instruction add3 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (pcrelative imm:Op4:tgtimm)); +) cost 1; + +//====-- MUL --====// +define instruction mul semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR (* Op4:GPR Op5:GPR)); +) cost 10; + +define instruction smull semantic as ( + let Op1 = "", Op2 = "", Op3 = "r9" in + (transfer Op4:GPR (mulhs Op5:GPR Op6:GPR)); +) cost 10; + +define instruction umull semantic as ( + let Op1 = "", Op2 = "", Op3 = "r9" in + (transfer Op4:GPR (mulhu Op5:GPR Op6:GPR)); +) cost 10; + +//====-- ORR --====// +define instruction orr1 semantic as ( +let Op1 = "", Op2 = "" in + (transfer Op3:GPR (or Op4:GPR SimpleAddrMode:fragment)); +) cost 1; +define instruction orr1 semantic as ( +let Op1 = "", Op2 = "" in + (transfer Op3:GPR (or Op4:GPR RegShiftedAddrMode:fragment)); +) cost 1; +define instruction orr1 semantic as ( +let Op1 = "", Op2 = "" in + (transfer Op3:GPR (or Op4:GPR RegRotAddrMode:fragment)); +) cost 1; +define instruction orr2 semantic as ( +let Op1 = "", Op2 = "" in + (transfer Op3:GPR (or Op4:GPR RegShiftedAddr2Mode:fragment)); +) cost 1; +define instruction orr3 semantic as ( +let Op1 = "", Op2 = "" in + (transfer Op3:GPR (or Op4:GPR ImmAddrMode:fragment)); +) cost 1; + +//====-- CMP --====// +define instruction cmp1 semantic as ( +let Op1 = "" in + (transfer SR:CPSR (comp Op2:GPR SimpleAddrMode:fragment params (Op3))); +) cost 1; +define instruction cmp1 semantic as ( +let Op1 = "" in + (transfer SR:CPSR (comp Op2:GPR RegShiftedAddrMode:fragment params (Op3 Op4))); +) cost 1; +define instruction cmp1 semantic as ( +let Op1 = "" in + (transfer SR:CPSR (comp Op2:GPR RegRotAddrMode:fragment params (Op3))); +) cost 1; +define instruction cmp2 semantic as ( +let Op1 = "" in + (transfer SR:CPSR (comp Op2:GPR RegShiftedAddr2Mode:fragment params (Op3 Op4))); +) cost 1; +define instruction cmp3 semantic as ( +let Op1 = "" in + (transfer SR:CPSR (comp Op2:GPR ImmAddrMode:fragment params (Op3))); +) cost 1; + +//====-- MOV --====// +define instruction mov1 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR SimpleAddrMode:fragment params (Op4)); +) cost 1; +define instruction mov1 semantic as ( + (ret); +) cost 1; +define instruction mov1 semantic as ( + (nop); +) cost 1; +define instruction mov1 semantic as ( + let Op1 = "", Op2 = "", Op5 = "LSL" in + (transfer Op3:GPR RegShiftedAddrMode:fragment params (Op4 Op6)); + let Op1 = "", Op2 = "", Op5 = "LSR" in + (transfer Op3:GPR RegRightShiftedAddrMode:fragment params (Op4 Op6)); + let Op1 = "", Op2 = "", Op5 = "ASR" in + (transfer Op3:GPR RegARightShiftedAddrMode:fragment params (Op4 Op6)); + let Op1 = "", Op2 = "", Op5 = "ROR" in + (transfer Op3:GPR RegRotRightAddrMode:fragment params (Op4 Op6)); +) cost 1; +define instruction mov1 semantic as ( + let Op1 = "", Op2 = "" in + (transfer Op3:GPR RegRotAddrMode:fragment params (Op4)); +) cost 1; +define instruction mov2 semantic as ( + let Op1 = "", Op2 = "", Op5 = "LSL" in + (transfer Op3:GPR RegShiftedAddr2Mode:fragment params (Op4 Op6)); + let Op1 = "", Op2 = "", Op5 = "LSR" in + (transfer Op3:GPR RegRightShiftedAddr2Mode:fragment params (Op4 Op6)); + let Op1 = "", Op2 = "", Op5 = "ASR" in + (transfer Op3:GPR RegARightShiftedAddr2Mode:fragment params (Op4 Op6)); + let Op1 = "", Op2 = "", Op5 = "ROR" in + (transfer Op3:GPR RegRotRightAddr2Mode:fragment params (Op4 Op6)); +// (transfer Op3:GPR const:int:1); +) cost 1; +define instruction mov3 semantic as ( + let Op1 = "", Op2 = "" in + // {SR:CPSR == const:int:1} -> + (transfer Op3:GPR ImmAddrMode:fragment params (Op4)); +) cost 1; + +//====-- TEQ --====// +//define instruction teq1 semantic as ( + //let Op1 = "" in + //{Op2:GPR == Op3:GPR} -> (transfer SR:CPSR const:int:1); + //let Op1 = "" in +// {Op2:GPR < Op3:GPR} -> (transfer SR:CPSR const:int:10); +//) cost 1; + +//====-- STR --====// +define instruction str1 semantic as ( + let Op1 = "" in + (transfer (memref Op3:GPR) Op2:GPR); +) cost 1; +define instruction str1 semantic as () cost 1; +define instruction str1 semantic as () cost 1; +define instruction str1 semantic as ( + let Op1 = "" in + (transfer (memref (add Op3:GPR imm:Op4:tgtimm)) Op2:GPR); +) cost 1; + +define instruction str2 semantic as ( + let Op1 = "" in + (transfer (memref (add Op3:GPR Op4:GPR)) Op2:GPR); +) cost 1; +define instruction str2 semantic as ( + let Op1 = "" in + (transfer (memref (sub Op3:GPR Op4:GPR)) Op2:GPR); +) cost 1; + +//STRB +define instruction strb1 semantic as ( + let Op1 = "" in + (transfer (memref Op3:GPR) (trunc Op2:GPR const:num:8)); +) cost 1; + +//STRH +define instruction strh semantic as ( + let Op1 = "" in + (transfer (memref Op3:GPR) (trunc Op2:GPR const:num:16)); +) cost 1; + +//====-- LDR --====// +define instruction ldr1 semantic as ( + let Op1 = "" in + (transfer Op2:GPR (memref Op3:GPR)); +) cost 1; +define instruction ldr1 semantic as () cost 1; +define instruction ldr1 semantic as () cost 1; +define instruction ldr1 semantic as ( + let Op1 = "" in + (transfer Op2:GPR (memref (add Op3:GPR imm:Op4:tgtimm))); +) cost 1; + +define instruction ldr2 semantic as ( + let Op1 = "" in + (transfer Op2:GPR (memref (add Op3:GPR Op4:GPR))); +) cost 1; +define instruction ldr2 semantic as ( + let Op1 = "" in + (transfer Op2:GPR (memref (sub Op3:GPR Op4:GPR))); +) cost 1; +define instruction ldr2 semantic as () cost 1; +define instruction ldr2 semantic as ( + let Op1 = "", Op5 = "LSL" in + (transfer Op2:GPR (memref (add Op3:GPR RegShiftedAddrMode:fragment params (Op4 Op6)))); + let Op1 = "", Op5 = "LSR" in + (transfer Op2:GPR (memref (add Op3:GPR RegRightShiftedAddrMode:fragment params (Op4 Op6)))); + let Op1 = "", Op5 = "ASR" in + (transfer Op2:GPR (memref (add Op3:GPR RegARightShiftedAddrMode:fragment params (Op4 Op6)))); +) cost 1; +define instruction ldr2 semantic as ( + let Op1 = "", Op5 = "LSL" in + (transfer Op2:GPR (memref (sub Op3:GPR RegShiftedAddrMode:fragment params (Op4 Op6)))); + let Op1 = "", Op5 = "LSR" in + (transfer Op2:GPR (memref (sub Op3:GPR RegRightShiftedAddrMode:fragment params (Op4 Op6)))); + let Op1 = "", Op5 = "ASR" in + (transfer Op2:GPR (memref (sub Op3:GPR RegARightShiftedAddrMode:fragment params (Op4 Op6)))); +) cost 1; + +//LDRB +define instruction ldrb1 semantic as ( + let Op1 = "" in + (transfer Op2:GPR (zext (memref Op3:GPR) const:num:8)); +) cost 1; + +//LDRH +define instruction ldrh semantic as ( + let Op1 = "" in + (transfer Op2:GPR (zext (memref Op3:GPR) const:num:16)); +) cost 1; + +//LDRSB +define instruction ldrsb semantic as ( + let Op1 = "" in + (transfer Op2:GPR (sext (memref Op3:GPR) const:num:8)); +) cost 1; + +//LDRSH +define instruction ldrsh semantic as ( + let Op1 = "" in + (transfer Op2:GPR (sext (memref Op3:GPR) const:num:16)); +) cost 1; + +//translate (transfer a3:regs (+ a1:immed a2:immed)); + +//translate (transfer a3:int (+ a1:int a2:int)); diff --git a/pdl/arm/defines_gdb b/pdl/arm/defines_gdb new file mode 100644 index 0000000..ac0752a --- /dev/null +++ b/pdl/arm/defines_gdb @@ -0,0 +1,20 @@ +//Number of registers +#define NUM_REGISTERS 16 + +//Number stack pointer register +#define NUM_REGISTER_SP 13 + +//Number frame pointer register +#define NUM_REGISTER_FP 11 + +//Number program counter register +#define NUM_REGISTER_PC 15 + +//Number first return procedures register +#define NUM_REGISTER_RET1 14 + +//Number second return procedures register - only SPARC +#define NUM_REGISTER_RET2 -1 + +//Offset add in pc register - only SPARC +#define OFFSET 0 diff --git a/pdl/arm/dynamic_info.ac b/pdl/arm/dynamic_info.ac new file mode 100644 index 0000000..96101b7 --- /dev/null +++ b/pdl/arm/dynamic_info.ac @@ -0,0 +1,35 @@ +/* *** Dynamic linking information *** */ + +/* The name of the dynamic interpreter. This is put in the .interp + section. */ +#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1" + +#define PLT_HEADER_SIZE 16 + +/* The size in bytes of an entry in the procedure linkage table. */ +#define PLT_ENTRY_SIZE 16 + +/* The first entry in a procedure linkage table looks like + this. It is set up so that any shared library function that is + called before the relocation has been set up calls the dynamic + linker first. */ +ac_plt0_entry (PLT_HEADER_SIZE / 4) = + { + 0xe52de004, /* str lr, [sp, #-4]! */ + 0xe59fe010, /* ldr lr, [pc, #16] */ + 0xe08fe00e, /* add lr, pc, lr */ + 0xe5bef008, /* ldr pc, [lr, #8]! */ + }; + +/* Subsequent entries in a procedure linkage table look like + this. */ +ac_plt_entry (PLT_ENTRY_SIZE / 4) = + { + 0xe28fc600, /* add ip, pc, #NN */ + 0xe28cca00, /* add ip, ip, #NN */ + 0xe5bcf000, /* ldr pc, [ip, #NN]! */ + 0x00000000, /* unused */ + }; + +#define ac_model_can_patch_plt + diff --git a/pdl/arm/dynamic_patch.ac b/pdl/arm/dynamic_patch.ac new file mode 100644 index 0000000..6f78b8a --- /dev/null +++ b/pdl/arm/dynamic_patch.ac @@ -0,0 +1,41 @@ + +/* ARM Model - Dynamic linking helper functions */ + +/* Input: got_displacement, plt_address */ +ac_patch_plt0_entry() +{ + + /* Calculate the displacement between the PLT slot and &GOT[0]. */ + got_displacement -= 16; + + /* The displacement value goes in the otherwise-unused last word of + the second entry. */ + ac_patch_bits (32, plt_address + 28, got_displacement); /* 32 bits, location to write, value to write */ +} + +/* Input: got_displacement, plt_offset, plt_address */ +ac_patch_plt_entry() +{ + unsigned int entry_copy[PLT_ENTRY_SIZE / 4]; + + /* got_displacement has the displacement between this PLT entry and its related GOT entry */ + got_displacement -= 8; /* We'll use it PC relative, and ARM pc-relative is PC + 8 */ + + /* Get a copy of the plt entry instructions already stored there */ + entry_copy[0] = (unsigned int) ac_get_bits(32, plt_address + plt_offset + 0); + entry_copy[1] = (unsigned int) ac_get_bits(32, plt_address + plt_offset + 4); + entry_copy[2] = (unsigned int) ac_get_bits(32, plt_address + plt_offset + 8); + + /* Relocate these plt entry instructions using ARM rotation mechanism to store large + immediates */ + + entry_copy[0] |= ((got_displacement & 0x0ff00000) >> 20); + entry_copy[1] |= ((got_displacement & 0x000ff000) >> 12); + entry_copy[2] |= (got_displacement & 0x00000fff); + + /* Write back the result */ + + ac_patch_bits(32, plt_address + plt_offset + 0, entry_copy[0]); + ac_patch_bits(32, plt_address + plt_offset + 4, entry_copy[1]); + ac_patch_bits(32, plt_address + plt_offset + 8, entry_copy[2]); +} diff --git a/pdl/arm/modifiers b/pdl/arm/modifiers new file mode 100644 index 0000000..87d4d04 --- /dev/null +++ b/pdl/arm/modifiers @@ -0,0 +1,159 @@ +#define rotate_right(v, n) (v >> n | v << (32 - n)) + +/* ARM immediate encoding routine + * Based on Binutils' ARM port + */ +ac_modifier_encode(aimm) +{ + unsigned int a; + unsigned int i; + +#define rotate_left(v, n) (v << n | v >> (32 - n)) + + for (i = 0; i < 32; i += 2) + if ((a = rotate_left (reloc->input, i)) <= 0xff) { + reloc->Type_DPI3.rotate = i >> 1; + reloc->Type_DPI3.imm8 = a; + return; + } + + reloc->error = 1; +} + +ac_modifier_decode(aimm) +{ + reloc->output = rotate_right(reloc->input, (reloc->Type_DPI3.rotate << 1)); +} + +/* + * "Branch" and "Branch and Link" instructions immediate modifier + * Coded as 24bit, 2 times right shifted (ARM ISA is 32bits word aligned) + * pc-relative + 8 offset. + */ +ac_modifier_encode(bimm) +{ + reloc->output = (reloc->input - reloc->address - 8) >>2; +} + +ac_modifier_decode(bimm) +{ + int val = (int) reloc->input; + if (val & 0x00800000) + val |= 0xFF000000; + reloc->output = (val << 2) + reloc->address + 8; +} + + +/* + * "Branch and Exchange to thumb mode" instruction immediate modifier + * Coded as 24bit, 2 times right shifted (Thumb instructions is + * 16bits word aligned, so bit 1 is coded in field "H") + * pc-relative + 8 offset. + */ +ac_modifier_encode(bximm) +{ + unsigned int modifiedImm = reloc->input; + modifiedImm = modifiedImm - reloc->address - 8; + + reloc->Type_BBLT.h = (modifiedImm >> 1) & 0x01; + reloc->Type_BBLT.offset = modifiedImm >> 2; +} + +ac_modifier_decode(bximm) +{ + reloc->output = (reloc->input << 2) + reloc->address + 8; +} + +/* Converts pc-relative immediates, rotated - used only + * in ADR pseudo instruction + */ +ac_modifier_encode(pcrelrot) +{ + unsigned int pcrelat = reloc->input - reloc->address - 8; + unsigned int a; + unsigned int i; + + // Determines if ADR will be ADD or SUB + if ((pcrelat & 0x80000000) == 0) + reloc->Type_DPI3.func1 = 0x04; // ADD + else + { + reloc->Type_DPI3.func1 = 0x02; // SUB + pcrelat = 0 - pcrelat; + } + + for (i = 0; i < 32; i += 2) + if ((a = rotate_left (pcrelat, i)) <= 0xff) { + reloc->Type_DPI3.rotate = ((i >> 1)&0xF); + reloc->Type_DPI3.imm8 = (a & 0xFF); + return; + } + + reloc->error = 1; +} + +ac_modifier_decode(pcrelrot) +{ + reloc->error = 0; +} + +/* converts pc-relative immediate (used only in pseudo LDR) + */ +ac_modifier_encode(pcrelldr) +{ + unsigned int pcrelat = reloc->input - reloc->address - 8; + // Determines if LDR will have negative or positive offset + if ((pcrelat & 0x80000000) == 0) + reloc->Type_LSI.u = 0x01; // ADD + else + { + reloc->Type_LSI.u = 0x00; // SUB + pcrelat = 0 - pcrelat; + } + reloc->Type_LSI.imm12 = 0xFFF & pcrelat; +} +ac_modifier_decode(pcrelldr) +{ + reloc->output = reloc->input + reloc->address + 8; +} + +/* Multiple data transfer register list element - codifies + * a register number into a bit in the register list. + * Uses the list operator to obtain list of registers parsed. + */ +ac_modifier_encode(dorlist) +{ + int init_range = -1; + unsigned i = 0; + + while (list_results_has_data(reloc->list_results)) + { + char separator = list_results_get_separator(reloc->list_results); + unsigned int result = list_results_next(&(reloc->list_results)); + if (init_range != -1) + { + for (i = init_range; i <= result; i++) + reloc->output = reloc->output | (1 << i); + } + else + reloc->output = reloc->output | (1 << result); + init_range = -1; + if (separator == '-') + init_range = result; + } +} + +ac_modifier_decode(dorlist) +{ + unsigned i = 0; + unsigned val = reloc->input; + + for (i = 0; i < 16; i++) + { + unsigned aux = val >> i; + if (aux & 1) { + list_results_store(&(reloc->list_results), i); + } + } +} + diff --git a/pdl/mips/.gitignore b/pdl/mips/.gitignore new file mode 100644 index 0000000..455e0fd --- /dev/null +++ b/pdl/mips/.gitignore @@ -0,0 +1,24 @@ +Makefile +Makefile.archc +main.cpp +main.cpp.tmpl +*.o +*.x +*.a +mips.H +mips.cpp +mips.x +mips_arch.H +mips_arch.cpp +mips_arch_ref.H +mips_arch_ref.cpp +mips_bhv_macros.H +mips_isa.H +mips_isa.cpp.tmpl +mips_isa_init.cpp +mips_parms.H +mips_syscall.H.tmpl +mips_syscall.cpp.tmpl +mips_ih_bhv_macros.H +mips_intr_handlers.H +mips_intr_handlers.cpp* diff --git a/pdl/mips/CONTRIBUTING.md b/pdl/mips/CONTRIBUTING.md new file mode 100644 index 0000000..ccd53d7 --- /dev/null +++ b/pdl/mips/CONTRIBUTING.md @@ -0,0 +1,12 @@ +# Contributing + +## Submitting a Pull Request + +1. Fork it. +2. Create a branch (`git checkout -b my_project`) +3. Commit your changes (`git commit -a`) [Tips for better commit message](https://robots.thoughtbot.com/5-useful-tips-for-a-better-commit-message) +4. Push to the branch (`git push origin my_project`) +5. Open a [Pull Request][1] +6. Enjoy a refreshing Diet Coke and wait doing more + +[1]: https://github.com/ArchC/mips/pulls diff --git a/pdl/mips/COPYING b/pdl/mips/COPYING new file mode 100644 index 0000000..d445e88 --- /dev/null +++ b/pdl/mips/COPYING @@ -0,0 +1,74 @@ + ArchC DEVELOPMENT PUBLIC LICENSE + +Everyone is permitted to copy and distribute verbatim copies of this +license document, but changing it is not allowed. + + Preamble + +You received this software from a trusted source and for research +purposes. Using or modifying this Program implies full acceptance of +this license. Please contact the person who send or gave you access to +this program for further information. + + ArchC DEVELOPMENT PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + +This license extends to all Programs contained in the package that +you received, including all subdirectories from this root, except if +the file header indicates another license. + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. + + 1. You may copy verbatim copies of the Program's source code as you +receive it, in any medium, for personal use, provided that you copy +copyright notice and disclaimer of warranty; and keep intact all the +notices that refer to this License and to the absence of any warranty. + +Personal use can be extended to a laboratory facility or a shared room +only if you are in charge of a research group that contributes to this +program and only with developing and research purposes. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy such +modifications or work under the terms of Section 1 above, provided +that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must not share, publish or distribute this program, either + in parts or in original form. You must not share, publish or + distribute programs that use this Program, either in parts or in + its original form. + + + 3. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or using the Program (or any work based on the Program), you +indicate your acceptance of this License to do so, and all its terms +and conditions for copying, distributing or modifying the Program or +works based on it. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the software in its development phase. + + NO WARRANTY + + 4. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + END OF TERMS AND CONDITIONS + diff --git a/pdl/mips/HISTORY.md b/pdl/mips/HISTORY.md new file mode 100644 index 0000000..2588c6b --- /dev/null +++ b/pdl/mips/HISTORY.md @@ -0,0 +1,89 @@ +## 2.4.0 + +* Revision numbers following the ArchC release +* Instructions with cycles annotations +* Two new .ac files to use with MPSoCBench (block and nonblock) +* mips_isa.cpp using the reserved work DATA_PORT to data request. See the [commit message](https://github.com/ArchC/mips/commit/fcf7eceb1e54de3037c3c9a0f785ab1606494c42). +* Interrupt handler support. It is inactive in standalone simulator. +* New PowerSC tables + +[Full changelog](https://github.com/ArchC/mips/compare/v2.3.0...v2.4.0) + +## 2.3.0 +* Revision numbers following the ArchC release ++ PowerSC support with power tables +* Memory instructions only use word size methods ++ Added id register for core identification + +[Full changelog](https://github.com/ArchC/mips/compare/v1.0.2...v2.3.0) + +## 1.0.2 +* Bugfix in DEBUG mode + +[Full changelog](https://github.com/ArchC/mips/compare/v1.0.1...v1.0.2) + +## 1.0.1 +* Updated syscall emulation library to setup multiprocessor stack + (this version can be used with the updated compilers) + +[Full changelog](https://github.com/ArchC/mips/compare/v1.0.0...v1.0.1) + +## 1.0.0 +* Changed name from mips1 to mips + +[Full changelog](https://github.com/ArchC/mips/compare/v0.7.8...v1.0.0) + +## 0.7.8 ++ Added binary utilities support files +* ArchC 2.0 compliant + +[Full changelog](https://github.com/ArchC/mips/compare/v0.7.7...v0.7.8) + +## 0.7.7-archc2.0beta3 +- Removed delayed assignements by creating the npc register ++ Created lo and hi registers and removed them from RB[32] and RB[33] + +[Full changelog](https://github.com/ArchC/mips/compare/v0.7.6...v0.7.7) + +## 0.7.6-archc2.0beta3 + ++ Added license headers +* Changed the assembly information for 'break' instruction + +[Full changelog](https://github.com/ArchC/mips/compare/v0.7.5-1...v0.7.6) + +## 0.7.5-archc2.0beta1 + +* Model compliant with ArchC 2.0beta1 + +[Full changelog](https://github.com/ArchC/mips/compare/v0.7.5...v0.7.5-1) + +## 0.7.5 + ++ Added 'bgtu' pseudo-insn ++ Added alternative assembly syntaxes to the lwl and lwr instructions +* Fixed the operand encoding of the nop 'instruction' + +[Full changelog](https://github.com/ArchC/mips/compare/v0.7.4...v0.7.5) + +## 0.7.4 + ++ Included assembly language syntax information + +## 0.7.3 + +* Use ArchC support for debug messages: ac_debug_model.H +* Use operator[] syntax to read register banks, which is faster + +## 0.7.2 + ++ Included optimization instruction methods for compiled simulation +* Separate nop instruction from sll to optimize simulation + +## 0.7.1 + ++ Included file for GDB integration + +## 0.7.0 + +* Model passed selected Mediabench and Mibench applications diff --git a/pdl/mips/README.md b/pdl/mips/README.md new file mode 100644 index 0000000..24d0c5f --- /dev/null +++ b/pdl/mips/README.md @@ -0,0 +1,75 @@ +MIPS ArchC functional model +===== + +This is the MIPS ArchC functional model. + +License +------- + - ArchC models are provided under the ArchC license. + See [Copying](COPYING) file for details on this license. + +acsim +----- +This model has the system call emulation functions implemented, +so it is a good idea to turn on the ABI option. + +To use acsim, the interpreted simulator: + + acsim mips.ac -abi (create the simulator) + make (compile) + mips.x --load= [args] (run an application) + +The [args] are optional arguments for the application. + +There are two formats recognized for application : +- ELF binary matching ArchC specifications +- hexadecimal text file for ArchC + + + +Binary utilities +---------------- +To generate binary utilities use: + + acbingen.sh -i -a mips.ac + +This will generate the tools source files using the architecture +name (if omitted, mips1 is used), copy them to the +binutils source tree, build and install them into the directory + (which -must- be an absolute path). +Use "acbingen.sh -h" to get information about the command-line +options available. + + +Change history +------------ + +See [History](HISTORY.md) + + +Contributing +------------ + +See [Contributing](CONTRIBUTING.md) + + +More +---- + +Remember that ArchC models and SystemC library must be compiled with +the same GCC version, otherwise you will get compilation problems. + +Several documents which further information can be found in the 'doc' +subdirectory. + +You can find language overview, models, and documentation at +http://www.archc.org + + + +Thanks for the interest. We hope you enjoy using ArchC! + +The ArchC Team +Computer Systems Laboratory (LSC) +IC-UNICAMP +http://www.lsc.ic.unicamp.br diff --git a/pdl/mips/arch_power_stats.H b/pdl/mips/arch_power_stats.H new file mode 100644 index 0000000..09c1fd7 --- /dev/null +++ b/pdl/mips/arch_power_stats.H @@ -0,0 +1,672 @@ +#ifdef POWER_SIM +#include +#include + +/* Data struct definition. You should think that it is a row in a table. Each profile will have a certain number of tables. + The basic idea is use a profile, with a pre-fixed number of operational frequencies. Each frequency, with a specific + table of values */ + +// This group should be parameters, not defines + +#define NUM_INSTR 59 + +/**** Power Tables using FPGAs *****/ +//#define POWER_TABLE_FILE "acpower_table_mips_cycloneV_25Mhz.csv" +//#define POWER_TABLE_FILE "acpower_table_mips_cycloneV_50Mhz.csv" +//define POWER_TABLE_FILE "acpower_table_mips_cycloneV_100Mhz.csv" +//#define POWER_TABLE_FILE "acpower_table_mips_xc3s1200e_100Mhz.csv" +//#define POWER_TABLE_FILE "acpower_table_mips_xc6slx75_100Mhz.csv" +//#define POWER_TABLE_FILE "acpower_table_mips_ep3sl50_100mhz.csv" +//#define POWER_TABLE_FILE "acpower_table_mips_xc4vlx15_100Mhz.csv" +//#define POWER_TABLE_FILE "acpower_table_mips_xc5vlx50t_100Mhz.csv" + +/**** Power Tables using ASICS *****/ +//#define POWER_TABLE_FILE "ac_power_table_mips_ASIC_freepdk45_50Mhz.csv" +//#define POWER_TABLE_FILE "ac_power_table_mips_ASIC_freepdk45_125Mhz.csv" +//#define POWER_TABLE_FILE "ac_power_table_mips_ASIC_freepdk45_250Mhz.csv" +//#define POWER_TABLE_FILE "ac_power_table_mips_ASIC_freepdk45_400Mhz.csv" + +/**** Power Tables with multiples profiles (Useful for DVFS control) *****/ +// #define POWER_TABLE_FILE "acpower_table_mips_cycloneV_25Mhz_100Mhz.csv" +#define POWER_TABLE_FILE "acpower_table_mips_ASIC_freepdk45_50_125_250_400Mhz.csv" +//#define POWER_TABLE_FILE "acpower_table_mips_ASIC_freepdk45_125_250_400Mhz.csv" + +#define WINDOW_REPORT +#define WINDOW_REPORT_FILE "window_power_report" +#define START_WINDOW_SIZE 1000000 + +#define MAX_LINESIZE_CSV_FILE 10240 // Inefficient and non-scalable +#define MAX_INSTR_NAME_SIZE 30 +#define MAX_POWER_STATS_NAME_SIZE 30 +#define MAX_POWER_STATS_DESCR_SIZE 140 + +#define TYPE_LINE_NUM_PROFILE 0 +#define TYPE_LINE_PROFILE 1 +#define TYPE_LINE_STALL 2 +#define TYPE_LINE_OP 3 + +#define CYCLES_PER_FREQUENCY_EXCHANGE 20000 // nanoseconds = or 20 micro seconds +#define CYCLES_TO_RESTART 300 + +//#define DEBUG + +class power_stats { + private: + struct profile + { + char power_stats_name[MAX_POWER_STATS_NAME_SIZE]; + char power_stats_descr[MAX_POWER_STATS_DESCR_SIZE]; + + unsigned int freq; + double freq_scale; + double power_scale; + double power[NUM_INSTR+1]; + double stall_power; + + }; + + struct power_stats_data + { + char instr_name[NUM_INSTR+1][MAX_INSTR_NAME_SIZE]; + profile* p; + int index_nop; + }; + + struct dynamic_data + { + #ifdef WINDOW_REPORT + long long window_num_instr; + double window_energy; + double window_power; + long long window_count; + unsigned int window_size; + #endif + + + double execution_time; + sc_core::sc_time system_time; + long long total_num_instr; + double total_energy; + double total_power; + + /*****/ + double edp; + double energy_per_core; + + int delta_instr; + int last_delta_instr; + + double delta_t; + + unsigned int actual_profile; + unsigned int num_profiles; + + bool freq_changed; + }; + + dynamic_data dyn; + power_stats_data psc_data; + + + #ifdef WINDOW_REPORT + FILE* out_window_power_report; + + #endif + + #ifdef DEBUG + FILE* debug_file; + int contador_debug; + #endif + + + + + public: + psc_cell_power_info psc_info; + + // Constructor + power_stats(const char* proc_name): psc_info(proc_name, "Processor") + { + PSC_NUM_FIRST_SAMPLES(0x7FFFFFFF); + init(POWER_TABLE_FILE); + + /*Initialize power state using profile 0*/ + dyn.actual_profile = 0; + dyn.total_num_instr = 0; + dyn.total_energy = 0; + dyn.total_power = 0; + + /******/ + dyn.edp = 0; + dyn.energy_per_core = 0; + dyn.delta_instr = 0; + dyn.delta_t = 0; + dyn.last_delta_instr = 0; + + dyn.freq_changed = false; + + + char filename[512]; + + #ifdef WINDOW_REPORT + dyn.window_size = START_WINDOW_SIZE; + dyn.window_num_instr = 0; + dyn.window_energy = 0; + dyn.window_power = 0; + dyn.window_count = 0; + dyn.execution_time = 0; + dyn.system_time = sc_time(0,SC_NS); + + /****/ + + strcpy(filename, WINDOW_REPORT_FILE); + strcat(filename, "_"); + strcat(filename, proc_name); + strcat(filename, ".csv"); + out_window_power_report = fopen(filename, "w"); + if (out_window_power_report == NULL) { + perror("Couldn't open specified out_window_power_report file"); + exit(1); + } + /****/ + #endif + + #ifdef DEBUG + strcpy (filename, "debug_power"); + strcat(filename, "_"); + strcat(filename, proc_name); + strcat(filename, ".txt"); + + debug_file = fopen(filename, "w"); + if (debug_file == NULL) { + perror("Couldn't open specified debug file"); + exit(1); + } + contador_debug = 0; + + print_psc_data(); + #endif + } + + + // Destructor + ~power_stats() + { + free(psc_data.p); + + #ifdef WINDOW_REPORT + fclose(out_window_power_report); + #endif + + #ifdef DEBUG + fclose(debug_file); + #endif + } + + double get_power() { + return psc_info.get_power(); + } + + double get_power_instruction(int id, int profile) + { + // [J] * [1/s] = [W] + + double power = psc_data.p[profile].power[id] * psc_data.p[profile].power_scale * psc_data.p[profile].freq_scale * psc_data.p[profile].freq; + + #ifdef DEBUG + fprintf(debug_file,"\nGetting power instruction."); + fprintf(debug_file,"\nprofile: %d\t id: %d\t power[id]*power_scale*freq_scale*freq = %f * %f * %f * %d" , profile, id, psc_data.p[profile].power[id], psc_data.p[profile].power_scale, psc_data.p[profile].freq_scale, psc_data.p[profile].freq); + fprintf(debug_file,"\nReturning: %f", power); + contador_debug++; + #endif + + return power; + } + + double update_energy (int id, int profile) + { + + //printf("\nupdate_energy id=%d profile=%d", id, profile); + + double energy_per_instruction = psc_data.p[profile].power[id]; // * psc_data.p[profile].power_scale; + + set_edp(dyn.edp + energy_per_instruction); + dyn.energy_per_core = dyn.energy_per_core + energy_per_instruction; + } + + /*double get_newEnergy_stamp (int prof) + { + double total_instr = get_total_num_instr(); + dyn.delta_instr = total_instr - dyn.last_delta_instr; // total de instr executadas no delta_T atual + dyn.last_delta_instr = total_instr; + + double edp = get_edp(); + double energyStampUsingInstr = edp / dyn.delta_instr; + + double t = sc_time_stamp().to_seconds(); + + return energyStampUsingInstr; // em nanojoules + }*/ + + double get_energy_stamp (int prof) + { + + dyn.delta_instr = get_total_num_instr() - dyn.delta_instr; // total de instr executadas no delta_T atual + int freq = psc_data.p[prof].freq; // freq em MegaHz + double cycle_time_ns = 1000/freq; // tempo de um ciclo em nanossegundos + double edp = get_edp(); + + double energyStampUsingFreq = (double) edp*dyn.delta_instr*cycle_time_ns; + + dyn.delta_t = sc_time_stamp().to_seconds() - dyn.delta_t; + + + double t = dyn.delta_t*1000000000; // em nanossegundos + + + double energyStampUsingTime = edp*t; + + return energyStampUsingTime; + } + + void initialize_energy_stamp() + { + dyn.edp = 0.0; + dyn.delta_instr = 0; + + } + + double get_edp () + { + return dyn.edp; + } + void set_edp (double value) + { + dyn.edp = value; + } + int type_line(int line, int num_profiles) + { + if (num_profiles == 0) + { + return TYPE_LINE_NUM_PROFILE; + } + else if (line <= num_profiles + 1) + { + return TYPE_LINE_PROFILE; + } + else if (line == num_profiles + 2) + { + return TYPE_LINE_STALL; + } + else + return TYPE_LINE_OP; + } + + #ifdef WINDOW_REPORT + void incr_window_energy(double v) + { + dyn.window_energy += v; + } + + void reset_window_data() + { + dyn.window_num_instr = 0; + dyn.window_energy = 0; + dyn.window_power = 0; + } + + void calc_window_power() + { + + dyn.window_power = dyn.window_energy / dyn.window_num_instr; + } + + void window_power_report() + { + + fprintf(out_window_power_report, "%d,%.10lf,%lld,%.10lf\n", dyn.actual_profile, dyn.execution_time, dyn.window_count, dyn.window_power); + } + #endif + + void incr_total_energy(double v) { + dyn.total_energy += v; + + } + + void incr_execution_time(int num_instr, int p) + { + + dyn.system_time = sc_time_stamp (); + + dyn.execution_time += num_instr / (psc_data.p[dyn.actual_profile].freq * psc_data.p[dyn.actual_profile].freq_scale); + + } + + void update_stat_power(int instr_id, int n = 1) + { + + #ifdef DEBUG + if (n!=1) + { + printf("\nPOWER_STATS: calculating power after change frequency."); + printf("\nPOWER_STATS: NOP id: %d , NOP power: %f",instr_id, get_power_instruction(instr_id, dyn.actual_profile)); + } + #endif + + dyn.total_num_instr = dyn.total_num_instr + n; + incr_execution_time(n, dyn.actual_profile); + + incr_total_energy(n * get_power_instruction(instr_id, dyn.actual_profile)); + + + update_energy(instr_id, dyn.actual_profile); + + #ifdef WINDOW_REPORT + + dyn.window_num_instr = dyn.window_num_instr + n; + + + incr_window_energy(n* get_power_instruction(instr_id, dyn.actual_profile)); + + + if (dyn.window_num_instr >= dyn.window_size) + { + dyn.window_count++; + calc_window_power(); + window_power_report(); + reset_window_data(); + } + #endif + + } + + + double get_total_num_instr () + { + return dyn.total_num_instr; + } + double get_total_energy() + { + return dyn.total_energy; + } + + double get_total_power () + { + calc_total_power(); + return dyn.total_power; + } + void calc_total_power() + { + dyn.total_power = dyn.total_energy / dyn.total_num_instr; + + #ifdef DEBUG + fprintf(debug_file,"\n\nCalculating total power = %f:", dyn.total_power); + #endif + } + + void powersc_connect() + { + calc_total_power(); + + // teste + psc_info.set_power(dyn.total_power); + psc_info.set_level(PSC_RT_LEVEL); + PSC_INSERT_CELL(psc_info); + + } + + void report() + { + PSC_REPORT_POWER; + dyn.system_time = sc_time_stamp(); + + } + + double getEnergyPerCore() + { + return dyn.energy_per_core; + } + char* next_strtok(const char* param, FILE* f, int pos_line) + { + char* pch = NULL; + pch = strtok(NULL,param); + if (pch == NULL) { + printf("Error reading csv file, line %d. Unexpected format\n", pos_line); + fclose(f); + exit(1); + } + return pch; + } + + // Read from file + void init(const char* filename) + { + FILE* f = NULL; + char c = 0; + char line[MAX_LINESIZE_CSV_FILE]; + char instr_name[MAX_INSTR_NAME_SIZE]; + char aux[MAX_LINESIZE_CSV_FILE]; + double value; + char* res; + + unsigned int index = 0; + unsigned int pos_line = 0; + unsigned int valid_line = 0; + unsigned int profile_id = 0; + fpos_t pos; + + char* pch = NULL; + + // Get self PATH + char buff[1024]; + strcpy (buff, POWER_SIM); + strcat (buff, "/"); + strcat (buff, filename); + + f = fopen(buff, "r"); + if (f == NULL) { + sprintf(aux, "Power file %s not found", buff); + perror(aux); + exit(1); + } + + dyn.num_profiles = 0; // Set a default value + + int state_id = 0; + + do { + //fgetpos (f, &pos); + res = fgets(line, MAX_LINESIZE_CSV_FILE, f); // Get a new line from file + if (feof(f)) break; + pos_line++; // It says what line I am reading now + pch = strtok(line, ",\""); // It parses the line + + + if (pch[0] == '#'); // If it is a comment, ignore + else if (pch == NULL) break; + else + { // Just found a valid new line + valid_line++; + // First Valid Line: number of profiles + switch(type_line(valid_line, dyn.num_profiles)) + { + case TYPE_LINE_NUM_PROFILE: + dyn.num_profiles = atoi(pch); + + psc_data.p = (profile *)malloc(sizeof(profile) * dyn.num_profiles); + // Cleaning table + for(int j = 0; j <= NUM_INSTR; j++) { + strcpy(psc_data.instr_name[j], ""); + for (int i = 0; i < dyn.num_profiles; i++) { + psc_data.p[i].power[j] = 0; + } + } + break; + + case TYPE_LINE_PROFILE: + + profile_id = state_id++; + + if (profile_id >= dyn.num_profiles) { + printf("Error: Invalid profile_id greater than num_profiles: %d > %d\n", + profile_id, dyn.num_profiles); + } + + //pch = next_strtok(",\"", f, pos_line); + psc_data.p[profile_id].freq = atoi(pch); + + pch = next_strtok(",\"", f, pos_line); + psc_data.p[profile_id].freq_scale = atof(pch); + + pch = next_strtok(",\"", f, pos_line); + psc_data.p[profile_id].power_scale = atof(pch); + + pch = next_strtok(",\"", f, pos_line); + strcpy(psc_data.p[profile_id].power_stats_name, pch); + + pch = next_strtok(",\"", f, pos_line); + strcpy(psc_data.p[profile_id].power_stats_descr, pch); + break; + case TYPE_LINE_STALL: + psc_data.p[0].stall_power = atof(pch); + + for(int i = 1; i < dyn.num_profiles;i++) { + pch = next_strtok(",\"", f, pos_line); + psc_data.p[i].stall_power = atof(pch); + } + break; + default: // TYPE_LINE_OP + + index = atoi(pch); + if (index <= NUM_INSTR) { + pch = next_strtok(",\"", f, pos_line); + strcpy(psc_data.instr_name[index], pch); + if (!strcmp(pch,"nop")) psc_data.index_nop = index; // capture the NOP index + + for(int i = 0; i < dyn.num_profiles;i++) + { + pch = next_strtok(",\"", f, pos_line); + psc_data.p[i].power[index] = atof(pch); + } + } + break; + } + } + } while(!feof(f)); + + fclose(f); + + + } + + void print_psc_data() { + + + + #ifdef DEBUG + + int i = 0, p = 0; + for(p = 0; p < dyn.num_profiles; p++) { + printf("\nProfile %d\n", p); + printf("Name: %s\n", psc_data.p[p].power_stats_name); + printf("Description: %s\n", psc_data.p[p].power_stats_descr); + printf("Frequency: %d\n\n", psc_data.p[p].freq); + printf("Frequency: %f\n\n", psc_data.p[p].freq_scale); + printf("NOP Power: %f\n\n", psc_data.p[p].power[psc_data.index_nop]); + + fprintf(debug_file,"\nProfile %d\n", p); + fprintf(debug_file,"Name: %s\n", psc_data.p[p].power_stats_name); + fprintf(debug_file,"Description: %s\n", psc_data.p[p].power_stats_descr); + fprintf(debug_file,"Frequency: %d\n\n", psc_data.p[p].freq); + fprintf(debug_file,"Frequency: %f\n\n", psc_data.p[p].freq_scale); + fprintf(debug_file,"NOP Power: %f\n\n", psc_data.p[p].power[psc_data.index_nop]); + } + + printf("Instr ID | Instruction Name"); + fprintf(debug_file,"Instr ID | Instruction Name"); + for(p = 0; p < dyn.num_profiles; p++) { + printf(" | Power Profile %d", p); + fprintf(debug_file," | Power Profile %d", p); + } + printf("\n"); + fprintf(debug_file,"\n"); + for(i = 1; i <= NUM_INSTR; i++) { + printf("%8d | %16s", i, psc_data.instr_name[i]); + fprintf(debug_file,"%8d | %16s", i, psc_data.instr_name[i]); + for(p = 0; p < dyn.num_profiles; p++) { + printf(" | %15.3lf", psc_data.p[p].power[i]); + fprintf(debug_file," | %15.3lf", psc_data.p[p].power[i]); + + } + + printf("\n"); + fprintf(debug_file,"\n"); + } + + #endif + } + + + /****** NEW DVFS FUNCTIONS *******/ + int getPowerState() + { + return dyn.actual_profile; + } + + void setPowerState (int state) + { + + if (state < dyn.num_profiles) + { + dyn.actual_profile = state; + + update_stat_power (psc_data.index_nop, CYCLES_PER_FREQUENCY_EXCHANGE); + + dyn.freq_changed = true; + + #ifdef DEBUG + printf("\nPOWER_STATS: updating the power state to %d ",state); + #endif + } + } + + bool needToWait() + { + if (dyn.freq_changed) + { + dyn.freq_changed = false; + return (true); + } + else return (false); + + + } + + int getNumberOfStates() + { + return dyn.num_profiles; + } + + void completeListOfStates (int* list) + { + + #ifdef DEBUG + printf("\nPOWER_STATS: returning the list of available states"); + #endif + + for (int i=0; i= 0 ) && ( reg < 32 ) ) + return RB.read( reg ); + else { + if (reg == 33) + return lo; + else if (reg == 34) + return hi; + else + /* pc */ + if ( reg == 37 ) + return ac_pc; + } + + return 0; +} + + +void mips::reg_write( int reg, ac_word value ) { + /* general purpose registers */ + if ( ( reg >= 0 ) && ( reg < 32 ) ) + RB.write( reg, value ); + else + { + /* lo, hi */ + if ( ( reg >= 33 ) && ( reg < 35 ) ) + RB.write( reg - 1, value ); + else + /* pc */ + if ( reg == 37 ) + ac_pc = value; + } +} + + +unsigned char mips::mem_read( unsigned int address ) { + return INST_PORT->read_byte( address ); +} + + +void mips::mem_write( unsigned int address, unsigned char byte ) { + INST_PORT->write_byte( address, byte ); +} diff --git a/pdl/mips/mips_isa.ac b/pdl/mips/mips_isa.ac new file mode 100644 index 0000000..dbd0833 --- /dev/null +++ b/pdl/mips/mips_isa.ac @@ -0,0 +1,442 @@ +/** + * @file mips_isa.ac + * @author Sandro Rigo + * Marcus Bartholomeu + * Alexandro Baldassin (acasm information) + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Thu, 29 Jun 2006 14:49:08 -0300 + * + * @brief The ArchC MIPS-I functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + */ + +AC_ISA(mips){ + + ac_format Type_R = "%op:6 %rs:5 %rt:5 %rd:5 %shamt:5 %func:6"; + ac_format Type_I = "%op:6 %rs:5 %rt:5 %imm:16:s"; + ac_format Type_J = "%op:6 %addr:26"; + + ac_instr lb, lbu, lh, lhu, lw, lwl, lwr; + ac_instr sb, sh, sw, swl, swr; + ac_instr addi, addiu, slti, sltiu, andi, ori, xori, lui; + ac_instr add, addu, sub, subu, slt, sltu; + ac_instr instr_and, instr_or, instr_xor, instr_nor; + ac_instr nop, sll, srl, sra, sllv, srlv, srav; + ac_instr mult, multu, div, divu; + ac_instr mfhi, mthi, mflo, mtlo; + ac_instr j, jal; + ac_instr jr, jalr; + ac_instr beq, bne, blez, bgtz, bltz, bgez, bltzal, bgezal; + ac_instr sys_call, instr_break; + + +// gas MIPS specific register names + ac_asm_map reg { + "$"[0..31] = [0..31]; + "$zero" = 0; + "$at" = 1; + "$v"[0..1] = [2..3]; + "$a"[0..3] = [4..7]; + "$t"[0..7] = [8..15]; + "$s"[0..7] = [16..23]; + "$t"[8..9] = [24..25]; + "$k"[0..1] = [26..27]; + "$gp" = 28; + "$sp" = 29; + "$fp" = 30; + "$ra" = 31; + } + + ISA_CTOR(mips){ + + lb.set_asm("lb %reg, \%lo(%exp)(%reg)", rt, imm, rs); + lb.set_asm("lb %reg, (%reg)", rt, rs, imm=0); + lb.set_asm("lb %reg, %imm (%reg)", rt, imm, rs); + lb.set_decoder(op=0x20); + + lbu.set_asm("lbu %reg, \%lo(%exp)(%reg)", rt, imm, rs); + lbu.set_asm("lbu %reg, (%reg)", rt, rs, imm=0); + lbu.set_asm("lbu %reg, %imm (%reg)", rt, imm, rs); + lbu.set_decoder(op=0x24); + + lh.set_asm("lh %reg, \%lo(%exp)(%reg)", rt, imm, rs); + lh.set_asm("lh %reg, (%reg)", rt, rs, imm=0); + lh.set_asm("lh %reg, %imm (%reg)", rt, imm, rs); + lh.set_decoder(op=0x21); + + lhu.set_asm("lhu %reg, \%lo(%exp)(%reg)", rt, imm, rs); + lhu.set_asm("lhu %reg, (%reg)", rt, rs, imm=0); + lhu.set_asm("lhu %reg, %imm (%reg)", rt, imm, rs); + lhu.set_decoder(op=0x25); + + lw.set_asm("lw %reg, \%lo(%exp)(%reg)", rt, imm, rs); + lw.set_asm("lw %reg, (%reg)", rt, rs, imm=0); + lw.set_asm("lw %reg, %imm (%reg)", rt, imm, rs); + lw.set_decoder(op=0x23); + + lwl.set_asm("lwl %reg, \%lo(%exp)(%reg)", rt, imm, rs); + lwl.set_asm("lwl %reg, (%reg)", rt, rs, imm=0); + lwl.set_asm("lwl %reg, %imm (%reg)", rt, imm, rs); + lwl.set_decoder(op=0x22); + + lwr.set_asm("lwr %reg, \%lo(%exp)(%reg)", rt, imm, rs); + lwr.set_asm("lwr %reg, (%reg)", rt, rs, imm=0); + lwr.set_asm("lwr %reg, %imm (%reg)", rt, imm, rs); + lwr.set_decoder(op=0x26); + + sb.set_asm("sb %reg, \%lo(%exp)(%reg)", rt, imm, rs); + sb.set_asm("sb %reg, (%reg)", rt, rs, imm=0); + sb.set_asm("sb %reg, %imm (%reg)", rt, imm, rs); + sb.set_decoder(op=0x28); + + sh.set_asm("sh %reg, \%lo(%exp)(%reg)", rt, imm, rs); + sh.set_asm("sh %reg, (%reg)", rt, rs, imm=0); + sh.set_asm("sh %reg, %imm (%reg)", rt, imm, rs); + sh.set_decoder(op=0x29); + + sw.set_asm("sw %reg, \%lo(%exp)(%reg)", rt, imm, rs); + sw.set_asm("sw %reg, (%reg)", rt, rs, imm=0); + sw.set_asm("sw %reg, %imm (%reg)", rt, imm, rs); + sw.set_decoder(op=0x2B); + + swl.set_asm("swl %reg, (%reg)", rt, rs, imm=0); + swl.set_asm("swl %reg, %imm (%reg)", rt, imm, rs); + swl.set_decoder(op=0x2A); + + swr.set_asm("swr %reg, (%reg)", rt, rs, imm=0); + swr.set_asm("swr %reg, %imm (%reg)", rt, imm, rs); + swr.set_decoder(op=0x2E); + + addi.set_asm("addi %reg, %reg, %exp", rt, rs, imm); + addi.set_asm("add %reg, %reg, %exp", rt, rs, imm); + addi.set_asm("add %reg, $0, %exp", rt, imm, rs=0); + addi.set_decoder(op=0x08); + addi.set_cycles(4); + + addiu.set_asm("addiu %reg, %reg, %exp", rt, rs, imm); + addiu.set_asm("addiu %reg, %reg, \%lo(%exp)", rt, rs, imm); + addiu.set_asm("addu %reg, %reg, %exp", rt, rs, imm); + addiu.set_decoder(op=0x09); + + slti.set_asm("slti %reg, %reg, %exp", rt, rs, imm); + slti.set_asm("slt %reg, %reg, %exp", rt, rs, imm); + slti.set_decoder(op=0x0A); + + sltiu.set_asm("sltiu %reg, %reg, %exp", rt, rs, imm); + sltiu.set_asm("sltu %reg, %reg, %exp", rt, rs, imm); + sltiu.set_decoder(op=0x0B); + + andi.set_asm("andi %reg, %reg, %imm", rt, rs, imm); + andi.set_asm("and %reg, %reg, %imm", rt, rs, imm); + andi.set_decoder(op=0x0C); + andi.set_cycles(1); + + ori.set_asm("ori %reg, %reg, %imm", rt, rs, imm); + ori.set_asm("or %reg, %reg, %imm", rt, rs, imm); + ori.set_decoder(op=0x0D); + ori.set_cycles(1); + + + xori.set_asm("xori %reg, %reg, %imm", rt, rs, imm); + xori.set_asm("xor %reg, %reg, %imm", rt, rs, imm); + xori.set_decoder(op=0x0E); + ori.set_cycles(1); + + lui.set_asm("lui %reg, %exp", rt, imm); + lui.set_asm("lui %reg, \%hi(%imm(carry))", rt, imm); + lui.set_asm("lui %reg, \%hi(%exp(carry))", rt, imm); + lui.set_decoder(op=0x0F, rs=0x00); + lui.set_cycles(1); + + add.set_asm("add %reg, %reg, %reg", rd, rs, rt); + add.set_decoder(op=0x00, func=0x20); + add.set_cycles(4); + + addu.set_asm("addu %reg, %reg, %reg", rd, rs, rt); + addu.set_asm("move %reg, %reg", rd, rs, rt="$zero"); + addu.set_decoder(op=0x00, func=0x21); + addu.set_cycles(4); + + sub.set_asm("sub %reg, %reg, %reg", rd, rs, rt); + sub.set_decoder(op=0x00, func=0x22); + sub.set_cycles(4); + + subu.set_asm("subu %reg, %reg, %reg", rd, rs, rt); + subu.set_decoder(op=0x00, func=0x23); + subu.set_cycles(4); + + slt.set_asm("slt %reg, %reg, %reg", rd, rs, rt); + slt.set_decoder(op=0x00, func=0x2A); + slt.set_cycles(1); + + sltu.set_asm("sltu %reg, %reg, %reg", rd, rs, rt); + sltu.set_decoder(op=0x00, func=0x2B); + slt.set_cycles(1); + + instr_and.set_asm("and %reg, %reg, %reg", rd, rs, rt); + instr_and.set_decoder(op=0x00, func=0x24); + + instr_or.set_asm("or %reg, %reg, %reg", rd, rs, rt); + instr_or.set_decoder(op=0x00, func=0x25); + + instr_xor.set_asm("xor %reg, %reg, %reg", rd, rs, rt); + instr_xor.set_decoder(op=0x00, func=0x26); + + instr_nor.set_asm("nor %reg, %reg, %reg", rd, rs, rt); + instr_nor.set_decoder(op=0x00, func=0x27); + + nop.set_asm("nop", rs=0, rt=0, shamt=0); + nop.set_decoder(op=0x00, rd=0x00, func=0x00); + + sll.set_asm("sll %reg, %reg, %imm", rd, rt, shamt); + sll.set_decoder(op=0x00, func= 0x00); + sll.set_cycles(1); + + srl.set_asm("srl %reg, %reg, %imm", rd, rt, shamt); + srl.set_decoder(op=0x00, func= 0x02); + sll.set_cycles(1); + + sra.set_asm("sra %reg, %reg, %imm", rd, rt, shamt); + sra.set_decoder(op=0x00, func= 0x03); + sll.set_cycles(1); + + sllv.set_asm("sllv %reg, %reg, %reg", rd, rt, rs); + sllv.set_asm("sll %reg, %reg, %reg", rd, rt, rs); // gas + sllv.set_decoder(op=0x00, func= 0x04); + sllv.set_cycles(1); + + srlv.set_asm("srlv %reg, %reg, %reg", rd, rt, rs); + srlv.set_asm("srl %reg, %reg, %reg", rd, rt, rs); // gas + srlv.set_decoder(op=0x00, func= 0x06); + srlv.set_cycles(1); + + srav.set_asm("srav %reg, %reg, %reg", rd, rt, rs); + srav.set_asm("sra %reg, %reg, %reg", rd, rt, rs); // gas + srav.set_decoder(op=0x00, func= 0x07); + srlv.set_cycles(1); + + mult.set_asm("mult %reg, %reg", rs, rt); + mult.set_decoder(op=0x00, func=0x18); + mult.set_cycles(4); + + multu.set_asm("multu %reg, %reg", rs, rt); + multu.set_decoder(op=0x00, func=0x19); + multu.set_cycles(4); + + div.set_asm("div %reg, %reg", rs, rt); + div.set_decoder(op=0x00, func=0x1A); + div.set_cycles(30);//media + + divu.set_asm("divu %reg, %reg", rs, rt); + divu.set_decoder(op=0x00, func=0x1B); + divu.set_cycles(30);//media + + + mfhi.set_asm("mfhi %reg", rd); + mfhi.set_decoder(op=0x00, func=0x10); + + mthi.set_asm("mthi %reg", rs); + mthi.set_decoder(op=0x00, func=0x11); + + mflo.set_asm("mflo %reg", rd); + mflo.set_decoder(op=0x00, func=0x12); + + mtlo.set_asm("mtlo %reg", rs); + mtlo.set_decoder(op=0x00, func=0x13); + + j.set_asm("j %exp(align)", addr); + j.set_decoder(op=0x02); + + jal.set_asm("jal %exp(align)", addr); + jal.set_asm("jal %exp(align)", addr); //compiler_info related + jal.set_decoder(op=0x03); + + jr.set_asm("jr %reg", rs); + jr.set_asm("j %reg", rs); + jr.set_asm("ret", rs = "$ra"); + jr.set_decoder(op=0x00, func= 0x08); + + jalr.set_asm("jalr %reg, %reg", rd, rs); + jalr.set_asm("jalr %reg", rs, rd="$ra"); + jalr.set_asm("jal %reg", rs, rd="$ra"); // gas + jalr.set_decoder(op=0x00, func= 0x09); + + beq.set_asm("beq %reg, %reg, %exp(pcrel)", rs, rt, imm); + beq.set_asm("b %exp(pcrel)", imm, rs=0, rt=0); // gas + beq.set_asm("beqz %reg, %exp(pcrel)", rs, imm, rt=0); // gas + beq.set_decoder(op=0x04); + + bne.set_asm("bgtu %reg, $0, %exp(pcrel)", rs, imm, rt=0x00); // bgtu with second operand fixed in 0 + bne.set_asm("bne %reg, %reg, %exp(pcrel)", rs, rt, imm); + bne.set_asm("bnez %reg, %exp(pcrel)", rs, imm, rt=0); + bne.set_decoder(op=0x05); + + blez.set_asm("blez %reg, %exp(pcrel)", rs, imm); + blez.set_decoder(op=0x06, rt=0x00); + + bgtz.set_asm("bgtz %reg, %exp(pcrel)", rs, imm); + bgtz.set_decoder(op=0x07, rt=0x00); + + bltz.set_asm("bltz %reg, %exp(pcrel)", rs, imm); + bltz.set_decoder(op=0x01, rt=0x00); + + bgez.set_asm("bgez %reg, %exp(pcrel)", rs, imm); + bgez.set_decoder(op=0x01, rt=0x01); + + bltzal.set_asm("bltzal %reg, %exp(pcrel)", rs, imm); + bltzal.set_decoder(op=0x01, rt=0x10); + + bgezal.set_asm("bgezal %reg, %exp(pcrel)", rs, imm); + bgezal.set_decoder(op=0x01, rt=0x11); + + sys_call.set_asm("syscall"); + sys_call.set_decoder(op=0x00, func=0x0C, rt=0, rs=0, rd=0, shamt=0); + + instr_break.set_asm("break", rt=0); + instr_break.set_asm("break %imm", rt); + instr_break.set_decoder(op=0x00, func=0x0D); + + + pseudo_instr("li %reg, %imm") { + "lui %0, \%hi(%1)"; + "ori %0, %0, %1"; + } + + pseudo_instr("la %reg, %addr") { + "lui %0, \%hi(%1)"; + "addiu %0, %0, \%lo(%1)"; + } + + pseudo_instr("sw %reg, %exp") { + "lui $at, \%hi(%1)"; + "sw %0, \%lo(%1)($at)"; + } + + pseudo_instr("lw %reg, %exp") { + "lui %0, \%hi(%1)"; + "lw %0, \%lo(%1)(%0)"; + } + + pseudo_instr("subu %reg, %reg, %imm") { + "addiu %0, %1, -%2"; + } + + pseudo_instr("ble %reg, %reg, %exp") { + "slt $at, %1, %0"; + "beq $at, $zero, %2"; + } + + pseudo_instr("ble %reg, %imm, %exp") { + "slti $at, %0, %1+1"; + "bne $at, $zero, %2"; + } + + pseudo_instr("mul %reg, %reg, %reg") { + "multu %1, %2"; + "mflo %0"; + } + + pseudo_instr("bge %reg, %reg, %exp") { + "slt $at, %0, %1"; + "beq $at, $zero, %2"; + } + + pseudo_instr("bgt %reg, %imm, %exp") { + "slti $at, %0, %1+1"; + "beq $at, $zero, %2"; + } + + pseudo_instr("mul %reg, %reg, %imm") { + "addiu $at, $zero, %2"; + "mult %1, $at"; + "mflo %0"; + } + + pseudo_instr("lw %reg, %exp (%reg)") { + /* this should be 'li %0, %1', but 'li' is a conditional pseudo in gas :/ + - this only works when %exp < 2^16-1 - should be enough for validation */ + "lui %0, %1"; + "addu %0, %0, %2"; + "lw %0, (%0)"; + } + + pseudo_instr("sw %reg, %exp (%reg)") { +/* this should be 'li %0, %1', but 'li' is a conditional pseudo in gas :/ + - this only works when %exp < 2^16-1 - should be enough for validation */ + "lui $at, %1"; + "addu $at, $at, %2"; + "sw %0, ($at)"; + } + + pseudo_instr("bne %reg, %imm, %exp") { + "addiu $at, $zero, %1"; + "bne %0, $at, %2"; + } + + +/*******************************************************/ +/* Optional properties to optimize compiled simulation */ +/*******************************************************/ + + + j.is_jump(((ac_pc+4) & 0xF0000000) | (addr<<2)); + j.delay(1); + + jal.is_jump(((ac_pc+4) & 0xF0000000) | (addr<<2)); + jal.delay(1); + jal.behavior(RB[31] = (ac_pc+4)+4;); + + jr.is_jump(RB[rs]); + jr.delay(1); + + jalr.is_jump(RB[rs]); + jalr.delay(1); + jalr.behavior(RB[(rd==0)?31:rd] = (ac_pc+4)+4;); + + + + beq.is_branch((ac_pc+4) + (imm<<2)); + beq.cond(RB[rs] == RB[rt]); + beq.delay(1); + + bne.is_branch((ac_pc+4) + (imm<<2)); + bne.cond(RB[rs] != RB[rt]); + bne.delay(1); + + blez.is_branch((ac_pc+4) + (imm<<2)); + blez.cond((RB[rs] == 0 ) || (RB[rs]&0x80000000 )); + blez.delay(1); + + bgtz.is_branch((ac_pc+4) + (imm<<2)); + bgtz.cond(!(RB[rs] & 0x80000000) && (RB[rs]!=0)); + bgtz.delay(1); + + bltz.is_branch((ac_pc+4) + (imm<<2)); + bltz.cond(RB[rs] & 0x80000000); + bltz.delay(1); + + bgez.is_branch((ac_pc+4) + (imm<<2)); + bgez.cond(!(RB[rs] & 0x80000000)); + bgez.delay(1); + + bltzal.is_branch((ac_pc+4) + (imm<<2)); + bltzal.cond(RB[rs] & 0x80000000); + bltzal.delay(1); + + bgezal.is_branch((ac_pc+4) + (imm<<2)); + bgezal.cond(!(RB[rs] & 0x80000000)); + bgezal.delay(1); + + }; + +}; diff --git a/pdl/mips/mips_isa.cpp b/pdl/mips/mips_isa.cpp new file mode 100644 index 0000000..be2640b --- /dev/null +++ b/pdl/mips/mips_isa.cpp @@ -0,0 +1,723 @@ +/** + * @file mips_isa.cpp + * @author Sandro Rigo + * Marcus Bartholomeu + * Alexandro Baldassin (acasm information) + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:50:52 -0300 + * + * @brief The ArchC i8051 functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + */ + +#include "mips_isa.H" +#include "mips_isa_init.cpp" +#include "mips_bhv_macros.H" + + +//If you want debug information for this model, uncomment next line +//#define DEBUG_MODEL +#include "ac_debug_model.H" + + +//!User defined macros to reference registers. +#define Ra 31 +#define Sp 29 + +// 'using namespace' statement to allow access to all +// mips-specific datatypes +using namespace mips_parms; + +static int processors_started = 0; +#define DEFAULT_STACK_SIZE (256*1024) + +//!Generic instruction behavior method. +void ac_behavior( instruction ) +{ + dbg_printf("----- PC=%#x ----- %lld\n", (int) ac_pc, ac_instr_counter); + // dbg_printf("----- PC=%#x NPC=%#x ----- %lld\n", (int) ac_pc, (int)npc, ac_instr_counter); +#ifndef NO_NEED_PC_UPDATE + ac_pc = npc; + npc = ac_pc + 4; +#endif +}; + +//! Instruction Format behavior methods. +void ac_behavior( Type_R ){} +void ac_behavior( Type_I ){} +void ac_behavior( Type_J ){} + +//!Behavior called before starting simulation +void ac_behavior(begin) +{ + dbg_printf("@@@ begin behavior @@@\n"); + RB[0] = 0; + npc = ac_pc + 4; + + // Is is not required by the architecture, but makes debug really easier + for (int regNum = 0; regNum < 32; regNum ++) + RB[regNum] = 0; + hi = 0; + lo = 0; + + RB[29] = AC_RAM_END - 1024 - processors_started++ * DEFAULT_STACK_SIZE; +} + +//!Behavior called after finishing simulation +void ac_behavior(end) +{ + dbg_printf("@@@ end behavior @@@\n"); +} + + +//!Instruction lb behavior method. +void ac_behavior( lb ) +{ + char byte; + dbg_printf("lb r%d, %d(r%d)\n", rt, imm & 0xFFFF, rs); + byte = DATA_PORT->read_byte(RB[rs]+ imm); + RB[rt] = (ac_Sword)byte ; + dbg_printf("Result = %#x\n", RB[rt]); +}; + +//!Instruction lbu behavior method. +void ac_behavior( lbu ) +{ + unsigned char byte; + dbg_printf("lbu r%d, %d(r%d)\n", rt, imm & 0xFFFF, rs); + byte = DATA_PORT->read_byte(RB[rs]+ imm); + RB[rt] = byte ; + dbg_printf("Result = %#x\n", RB[rt]); +}; + +//!Instruction lh behavior method. +void ac_behavior( lh ) +{ + short int half; + dbg_printf("lh r%d, %d(r%d)\n", rt, imm & 0xFFFF, rs); + half = DATA_PORT->read_half(RB[rs]+ imm); + RB[rt] = (ac_Sword)half ; + dbg_printf("Result = %#x\n", RB[rt]); +}; + +//!Instruction lhu behavior method. +void ac_behavior( lhu ) +{ + unsigned short int half; + half = DATA_PORT->read_half(RB[rs]+ imm); + RB[rt] = half ; + dbg_printf("Result = %#x\n", RB[rt]); +}; + +//!Instruction lw behavior method. +void ac_behavior( lw ) +{ + dbg_printf("lw r%d, %d(r%d)\n", rt, imm & 0xFFFF, rs); + RB[rt] = DATA_PORT->read(RB[rs]+ imm); + dbg_printf("Result = %#x\n", RB[rt]); +}; + +//!Instruction lwl behavior method. +void ac_behavior( lwl ) +{ + dbg_printf("lwl r%d, %d(r%d)\n", rt, imm & 0xFFFF, rs); + unsigned int addr, offset; + ac_Uword data; + + addr = RB[rs] + imm; + offset = (addr & 0x3) * 8; + data = DATA_PORT->read(addr & 0xFFFFFFFC); + data <<= offset; + data |= RB[rt] & ((1<read(addr & 0xFFFFFFFC); + data >>= offset; + data |= RB[rt] & (0xFFFFFFFF << (32-offset)); + RB[rt] = data; + dbg_printf("Result = %#x\n", RB[rt]); +}; + +//!Instruction sb behavior method. +void ac_behavior( sb ) +{ + unsigned char byte; + dbg_printf("sb r%d, %d(r%d)\n", rt, imm & 0xFFFF, rs); + byte = RB[rt] & 0xFF; + DATA_PORT->write_byte(RB[rs] + imm, byte); + dbg_printf("Result = %#x\n", (int) byte); +}; + +//!Instruction sh behavior method. +void ac_behavior( sh ) +{ + unsigned short int half; + dbg_printf("sh r%d, %d(r%d)\n", rt, imm & 0xFFFF, rs); + half = RB[rt] & 0xFFFF; + DATA_PORT->write_half(RB[rs] + imm, half); + dbg_printf("Result = %#x\n", (int) half); +}; + +//!Instruction sw behavior method. +void ac_behavior( sw ) +{ + dbg_printf("sw r%d, %d(r%d)\n", rt, imm & 0xFFFF, rs); + DATA_PORT->write(RB[rs] + imm, RB[rt]); + dbg_printf("Result = %#x\n", RB[rt]); +}; + +//!Instruction swl behavior method. +void ac_behavior( swl ) +{ + dbg_printf("swl r%d, %d(r%d)\n", rt, imm & 0xFFFF, rs); + unsigned int addr, offset; + ac_Uword data; + + addr = RB[rs] + imm; + offset = (addr & 0x3) * 8; + data = RB[rt]; + data >>= offset; + data |= DATA_PORT->read(addr & 0xFFFFFFFC) & (0xFFFFFFFF << (32-offset)); + DATA_PORT->write(addr & 0xFFFFFFFC, data); + dbg_printf("Result = %#x\n", data); +}; + +//!Instruction swr behavior method. +void ac_behavior( swr ) +{ + dbg_printf("swr r%d, %d(r%d)\n", rt, imm & 0xFFFF, rs); + unsigned int addr, offset; + ac_Uword data; + + addr = RB[rs] + imm; + offset = (3 - (addr & 0x3)) * 8; + data = RB[rt]; + data <<= offset; + data |= DATA_PORT->read(addr & 0xFFFFFFFC) & ((1<write(addr & 0xFFFFFFFC, data); + dbg_printf("Result = %#x\n", data); +}; + +//!Instruction addi behavior method. +void ac_behavior( addi ) +{ + dbg_printf("addi r%d, r%d, %d\n", rt, rs, imm & 0xFFFF); + RB[rt] = RB[rs] + imm; + dbg_printf("Result = %#x\n", RB[rt]); + //Test overflow + if ( ((RB[rs] & 0x80000000) == (imm & 0x80000000)) && + ((imm & 0x80000000) != (RB[rt] & 0x80000000)) ) { + fprintf(stderr, "EXCEPTION(addi): integer overflow.\n"); exit(EXIT_FAILURE); + } +}; + +//!Instruction addiu behavior method. +void ac_behavior( addiu ) +{ + dbg_printf("addiu r%d, r%d, %d\n", rt, rs, imm & 0xFFFF); + RB[rt] = RB[rs] + imm; + dbg_printf("Result = %#x\n", RB[rt]); +}; + +//!Instruction slti behavior method. +void ac_behavior( slti ) +{ + dbg_printf("slti r%d, r%d, %d\n", rt, rs, imm & 0xFFFF); + // Set the RD if RS< IMM + if( (ac_Sword) RB[rs] < (ac_Sword) imm ) + RB[rt] = 1; + // Else reset RD + else + RB[rt] = 0; + dbg_printf("Result = %#x\n", RB[rt]); +}; + +//!Instruction sltiu behavior method. +void ac_behavior( sltiu ) +{ + dbg_printf("sltiu r%d, r%d, %d\n", rt, rs, imm & 0xFFFF); + // Set the RD if RS< IMM + if( (ac_Uword) RB[rs] < (ac_Uword) imm ) + RB[rt] = 1; + // Else reset RD + else + RB[rt] = 0; + dbg_printf("Result = %#x\n", RB[rt]); +}; + +//!Instruction andi behavior method. +void ac_behavior( andi ) +{ + dbg_printf("andi r%d, r%d, %d\n", rt, rs, imm & 0xFFFF); + RB[rt] = RB[rs] & (imm & 0xFFFF) ; + dbg_printf("Result = %#x\n", RB[rt]); +}; + +//!Instruction ori behavior method. +void ac_behavior( ori ) +{ + dbg_printf("ori r%d, r%d, %d\n", rt, rs, imm & 0xFFFF); + RB[rt] = RB[rs] | (imm & 0xFFFF) ; + dbg_printf("Result = %#x\n", RB[rt]); +}; + +//!Instruction xori behavior method. +void ac_behavior( xori ) +{ + dbg_printf("xori r%d, r%d, %d\n", rt, rs, imm & 0xFFFF); + RB[rt] = RB[rs] ^ (imm & 0xFFFF) ; + dbg_printf("Result = %#x\n", RB[rt]); +}; + +//!Instruction lui behavior method. +void ac_behavior( lui ) +{ + dbg_printf("lui r%d, r%d, %d\n", rt, rs, imm & 0xFFFF); + // Load a constant in the upper 16 bits of a register + // To achieve the desired behaviour, the constant was shifted 16 bits left + // and moved to the target register ( rt ) + RB[rt] = imm << 16; + dbg_printf("Result = %#x\n", RB[rt]); +}; + +//!Instruction add behavior method. +void ac_behavior( add ) +{ + dbg_printf("add r%d, r%d, r%d\n", rd, rs, rt); + RB[rd] = RB[rs] + RB[rt]; + dbg_printf("Result = %#x\n", RB[rd]); + //Test overflow + if ( ((RB[rs] & 0x80000000) == (RB[rd] & 0x80000000)) && + ((RB[rd] & 0x80000000) != (RB[rt] & 0x80000000)) ) { + fprintf(stderr, "EXCEPTION(add): integer overflow.\n"); exit(EXIT_FAILURE); + } +}; + +//!Instruction addu behavior method. +void ac_behavior( addu ) +{ + dbg_printf("addu r%d, r%d, r%d\n", rd, rs, rt); + RB[rd] = RB[rs] + RB[rt]; + //cout << " RS: " << (unsigned int)RB[rs] << " RT: " << (unsigned int)RB[rt] << endl; + //cout << " Result = " << (unsigned int)RB[rd] <> shamt; + dbg_printf("Result = %#x\n", RB[rd]); +}; + +//!Instruction sra behavior method. +void ac_behavior( sra ) +{ + dbg_printf("sra r%d, r%d, %d\n", rd, rs, shamt); + RB[rd] = (ac_Sword) RB[rt] >> shamt; + dbg_printf("Result = %#x\n", RB[rd]); +}; + +//!Instruction sllv behavior method. +void ac_behavior( sllv ) +{ + dbg_printf("sllv r%d, r%d, r%d\n", rd, rt, rs); + RB[rd] = RB[rt] << (RB[rs] & 0x1F); + dbg_printf("Result = %#x\n", RB[rd]); +}; + +//!Instruction srlv behavior method. +void ac_behavior( srlv ) +{ + dbg_printf("srlv r%d, r%d, r%d\n", rd, rt, rs); + RB[rd] = RB[rt] >> (RB[rs] & 0x1F); + dbg_printf("Result = %#x\n", RB[rd]); +}; + +//!Instruction srav behavior method. +void ac_behavior( srav ) +{ + dbg_printf("srav r%d, r%d, r%d\n", rd, rt, rs); + RB[rd] = (ac_Sword) RB[rt] >> (RB[rs] & 0x1F); + dbg_printf("Result = %#x\n", RB[rd]); +}; + +//!Instruction mult behavior method. +void ac_behavior( mult ) +{ + dbg_printf("mult r%d, r%d\n", rs, rt); + + long long result; + int half_result; + + result = (ac_Sword) RB[rs]; + result *= (ac_Sword) RB[rt]; + + half_result = (result & 0xFFFFFFFF); + // Register LO receives 32 less significant bits + lo = half_result; + + half_result = ((result >> 32) & 0xFFFFFFFF); + // Register HI receives 32 most significant bits + hi = half_result ; + + dbg_printf("Result = %#llx\n", result); +}; + +//!Instruction multu behavior method. +void ac_behavior( multu ) +{ + dbg_printf("multu r%d, r%d\n", rs, rt); + + unsigned long long result; + unsigned int half_result; + + result = RB[rs]; + result *= RB[rt]; + + half_result = (result & 0xFFFFFFFF); + // Register LO receives 32 less significant bits + lo = half_result; + + half_result = ((result>>32) & 0xFFFFFFFF); + // Register HI receives 32 most significant bits + hi = half_result ; + + dbg_printf("Result = %#llx\n", result); +}; + +//!Instruction div behavior method. +void ac_behavior( div ) +{ + dbg_printf("div r%d, r%d\n", rs, rt); + // Register LO receives quotient + lo = (ac_Sword) RB[rs] / (ac_Sword) RB[rt]; + // Register HI receives remainder + hi = (ac_Sword) RB[rs] % (ac_Sword) RB[rt]; +}; + +//!Instruction divu behavior method. +void ac_behavior( divu ) +{ + dbg_printf("divu r%d, r%d\n", rs, rt); + // Register LO receives quotient + lo = RB[rs] / RB[rt]; + // Register HI receives remainder + hi = RB[rs] % RB[rt]; +}; + +//!Instruction mfhi behavior method. +void ac_behavior( mfhi ) +{ + dbg_printf("mfhi r%d\n", rd); + RB[rd] = hi; + dbg_printf("Result = %#x\n", RB[rd]); +}; + +//!Instruction mthi behavior method. +void ac_behavior( mthi ) +{ + dbg_printf("mthi r%d\n", rs); + hi = RB[rs]; + dbg_printf("Result = %#x\n", (unsigned int) hi); +}; + +//!Instruction mflo behavior method. +void ac_behavior( mflo ) +{ + dbg_printf("mflo r%d\n", rd); + RB[rd] = lo; + dbg_printf("Result = %#x\n", RB[rd]); +}; + +//!Instruction mtlo behavior method. +void ac_behavior( mtlo ) +{ + dbg_printf("mtlo r%d\n", rs); + lo = RB[rs]; + dbg_printf("Result = %#x\n", (unsigned int) lo); +}; + +//!Instruction j behavior method. +void ac_behavior( j ) +{ + dbg_printf("j %d\n", addr); + addr = addr << 2; +#ifndef NO_NEED_PC_UPDATE + npc = (ac_pc & 0xF0000000) | addr; +#endif + dbg_printf("Target = %#x\n", (ac_pc & 0xF0000000) | addr ); +}; + +//!Instruction jal behavior method. +void ac_behavior( jal ) +{ + dbg_printf("jal %d\n", addr); + // Save the value of PC + 8 (return address) in $ra ($31) and + // jump to the address given by PC(31...28)||(addr<<2) + // It must also flush the instructions that were loaded into the pipeline + RB[Ra] = ac_pc+4; //ac_pc is pc+4, we need pc+8 + + addr = addr << 2; +#ifndef NO_NEED_PC_UPDATE + npc = (ac_pc & 0xF0000000) | addr; +#endif + + dbg_printf("Target = %#x\n", (ac_pc & 0xF0000000) | addr ); + dbg_printf("Return = %#x\n", ac_pc+4); +}; + +//!Instruction jr behavior method. +void ac_behavior( jr ) +{ + dbg_printf("jr r%d\n", rs); + // Jump to the address stored on the register reg[RS] + // It must also flush the instructions that were loaded into the pipeline +#ifndef NO_NEED_PC_UPDATE + npc = RB[rs], (void) 1; +#endif + dbg_printf("Target = %#x\n", RB[rs]); +}; + +//!Instruction jalr behavior method. +void ac_behavior( jalr ) +{ + dbg_printf("jalr r%d, r%d\n", rd, rs); + // Save the value of PC + 8(return address) in rd and + // jump to the address given by [rs] + +#ifndef NO_NEED_PC_UPDATE + npc = RB[rs], (void) 1; +#endif + dbg_printf("Target = %#x\n", RB[rs]); + + if( rd == 0 ) //If rd is not defined use default + rd = Ra; + RB[rd] = ac_pc+4; + dbg_printf("Return = %#x\n", ac_pc+4); +}; + +//!Instruction beq behavior method. +void ac_behavior( beq ) +{ + dbg_printf("beq r%d, r%d, %d\n", rt, rs, imm & 0xFFFF); + if( RB[rs] == RB[rt] ){ +#ifndef NO_NEED_PC_UPDATE + npc = ac_pc + (imm<<2); +#endif + dbg_printf("Taken to %#x\n", ac_pc + (imm<<2)); + } +}; + +//!Instruction bne behavior method. +void ac_behavior( bne ) +{ + dbg_printf("bne r%d, r%d, %d\n", rt, rs, imm & 0xFFFF); + if( RB[rs] != RB[rt] ){ +#ifndef NO_NEED_PC_UPDATE + npc = ac_pc + (imm<<2); +#endif + dbg_printf("Taken to %#x\n", ac_pc + (imm<<2)); + } +}; + +//!Instruction blez behavior method. +void ac_behavior( blez ) +{ + dbg_printf("blez r%d, %d\n", rs, imm & 0xFFFF); + if( (RB[rs] == 0 ) || (RB[rs]&0x80000000 ) ){ +#ifndef NO_NEED_PC_UPDATE + npc = ac_pc + (imm<<2), (void) 1; +#endif + dbg_printf("Taken to %#x\n", ac_pc + (imm<<2)); + } +}; + +//!Instruction bgtz behavior method. +void ac_behavior( bgtz ) +{ + dbg_printf("bgtz r%d, %d\n", rs, imm & 0xFFFF); + if( !(RB[rs] & 0x80000000) && (RB[rs]!=0) ){ +#ifndef NO_NEED_PC_UPDATE + npc = ac_pc + (imm<<2); +#endif + dbg_printf("Taken to %#x\n", ac_pc + (imm<<2)); + } +}; + +//!Instruction bltz behavior method. +void ac_behavior( bltz ) +{ + dbg_printf("bltz r%d, %d\n", rs, imm & 0xFFFF); + if( RB[rs] & 0x80000000 ){ +#ifndef NO_NEED_PC_UPDATE + npc = ac_pc + (imm<<2); +#endif + dbg_printf("Taken to %#x\n", ac_pc + (imm<<2)); + } +}; + +//!Instruction bgez behavior method. +void ac_behavior( bgez ) +{ + dbg_printf("bgez r%d, %d\n", rs, imm & 0xFFFF); + if( !(RB[rs] & 0x80000000) ){ +#ifndef NO_NEED_PC_UPDATE + npc = ac_pc + (imm<<2); +#endif + dbg_printf("Taken to %#x\n", ac_pc + (imm<<2)); + } +}; + +//!Instruction bltzal behavior method. +void ac_behavior( bltzal ) +{ + dbg_printf("bltzal r%d, %d\n", rs, imm & 0xFFFF); + RB[Ra] = ac_pc+4; //ac_pc is pc+4, we need pc+8 + if( RB[rs] & 0x80000000 ){ +#ifndef NO_NEED_PC_UPDATE + npc = ac_pc + (imm<<2); +#endif + dbg_printf("Taken to %#x\n", ac_pc + (imm<<2)); + } + dbg_printf("Return = %#x\n", ac_pc+4); +}; + +//!Instruction bgezal behavior method. +void ac_behavior( bgezal ) +{ + dbg_printf("bgezal r%d, %d\n", rs, imm & 0xFFFF); + RB[Ra] = ac_pc+4; //ac_pc is pc+4, we need pc+8 + if( !(RB[rs] & 0x80000000) ){ +#ifndef NO_NEED_PC_UPDATE + npc = ac_pc + (imm<<2); +#endif + dbg_printf("Taken to %#x\n", ac_pc + (imm<<2)); + } + dbg_printf("Return = %#x\n", ac_pc+4); +}; + +//!Instruction sys_call behavior method. +void ac_behavior( sys_call ) +{ + dbg_printf("syscall\n"); + stop(); +} + +//!Instruction instr_break behavior method. +void ac_behavior( instr_break ) +{ + fprintf(stderr, "instr_break behavior not implemented.\n"); + exit(EXIT_FAILURE); +} diff --git a/pdl/mips/mips_nonblock.ac b/pdl/mips/mips_nonblock.ac new file mode 100644 index 0000000..c72b791 --- /dev/null +++ b/pdl/mips/mips_nonblock.ac @@ -0,0 +1,66 @@ +/** + * @file mips.ac + * @author Sandro Rigo + * Marcus Bartholomeu + * Alexandro Baldassin (acasm information) + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Thu, 29 Jun 2006 14:49:08 -0300 + * + * @brief The ArchC MIPS-I functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +AC_ARCH(mips){ + + ac_tlm2_nb_port MEM:512M; + //ac_icache IC("2w", 128, 32, "wb", "fifo"); + //ac_dcache DC("2w", 512, 32, "wt", "fifo"); + + ac_icache IC("dm", 64, 8, "wt", "none"); + ac_dcache DC("dm", 64, 8, "wt", "none"); + + ac_tlm2_intr_port intr_port; + + ac_regbank RB:32; + ac_reg npc; + ac_reg hi, lo; + + ac_wordsize 32; + ac_fetchsize 32; + ac_reg id; + + ARCH_CTOR(mips) { + + ac_isa("mips_isa.ac"); + set_endian("big"); + + IC.bindTo(MEM); + DC.bindTo(MEM); + + + }; +}; diff --git a/pdl/mips/mips_syscall.H b/pdl/mips/mips_syscall.H new file mode 100644 index 0000000..dc738da --- /dev/null +++ b/pdl/mips/mips_syscall.H @@ -0,0 +1,40 @@ +/****************************************************** + * ArchC Architecture Dependent Syscall header file. * + * This file is automatically generated by ArchC * + * WITHOUT WARRANTY OF ANY KIND, either express * + * or implied. * + * For more information on ArchC, please visit: * + * http://www.archc.org * + * * + * The ArchC Team * + * Computer Systems Laboratory (LSC) * + * IC-UNICAMP * + * http://www.lsc.ic.unicamp.br * + ******************************************************/ + + +#ifndef mips_SYSCALL_H +#define mips_SYSCALL_H + +#include "mips_arch.H" +#include "mips_arch_ref.H" +#include "mips_parms.H" +#include "ac_syscall.H" + +//mips system calls +class mips_syscall : public ac_syscall, public mips_arch_ref +{ +public: + mips_syscall(mips_arch& ref) : ac_syscall(ref, mips_parms::AC_RAMSIZE), mips_arch_ref(ref) {}; + virtual ~mips_syscall() {}; + + void get_buffer(int argn, unsigned char* buf, unsigned int size); + void set_buffer(int argn, unsigned char* buf, unsigned int size); + void set_buffer_noinvert(int argn, unsigned char* buf, unsigned int size); + int get_int(int argn); + void set_int(int argn, int val); + void return_from_syscall(); + void set_prog_args(int argc, char **argv); +}; + +#endif diff --git a/pdl/mips/mips_syscall.cpp b/pdl/mips/mips_syscall.cpp new file mode 100644 index 0000000..fa36582 --- /dev/null +++ b/pdl/mips/mips_syscall.cpp @@ -0,0 +1,125 @@ +/** + * @file mips_syscall.cpp + * @author Sandro Rigo + * Marcus Bartholomeu + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:50:52 -0300 + * + * @brief The ArchC MIPS-I functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include "mips_syscall.H" + +// 'using namespace' statement to allow access to all +// mips-specific datatypes +using namespace mips_parms; +unsigned procNumber = 0; + +void mips_syscall::get_buffer(int argn, unsigned char* buf, unsigned int size) +{ + unsigned int addr = RB[4+argn]; + + for (unsigned int i = 0; iread_byte(addr); + } +} + +void mips_syscall::set_buffer(int argn, unsigned char* buf, unsigned int size) +{ + unsigned int addr = RB[4+argn]; + + for (unsigned int i = 0; iwrite_byte(addr, buf[i]); + //printf("\nDATA_PORT[%d]=%d", addr, buf[i]); + + } +} + +void mips_syscall::set_buffer_noinvert(int argn, unsigned char* buf, unsigned int size) +{ + unsigned int addr = RB[4+argn]; + + for (unsigned int i = 0; iwrite(addr, *(unsigned int *) &buf[i]); + //printf("\nDATA_PORT_no[%d]=%d", addr, buf[i]); + } +} + +int mips_syscall::get_int(int argn) +{ + return RB[4+argn]; +} + +void mips_syscall::set_int(int argn, int val) +{ + RB[2+argn] = val; +} + +void mips_syscall::return_from_syscall() +{ + ac_pc = RB[31]; + npc = ac_pc + 4; +} + +void mips_syscall::set_prog_args(int argc, char **argv) +{ + + + int i, j, base; + + unsigned int ac_argv[30]; + char ac_argstr[512]; + + base = AC_RAM_END - 512 - procNumber * 64 * 1024; + for (i=0, j=0; iType_I.imm = (reloc->input + 0x00008000) >> 16; + +// Same as above (simpler) +// reloc->output = (reloc->input + 0x00008000) >> 16; +} + + +ac_modifier_decode(carry) +{ +} + + +ac_modifier_encode(align) +{ + reloc->Type_J.addr = reloc->input >> 2; + +// Simpler and same as above +// reloc->output = reloc->input >> 2; +} + + +ac_modifier_decode(align) +{ + reloc->output = reloc->input << 2; +} + + +ac_modifier_encode(pcrel) +{ + reloc->Type_I.imm = (reloc->input - (reloc->address + 4)) >> 2; + +// Simpler version of the above +// reloc->output = (reloc->input - (reloc->address + 4)) >> 2; +} + + +ac_modifier_decode(pcrel) +{ + reloc->output = (reloc->input << 2) + reloc->address + 4; +} diff --git a/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_125Mhz.csv b/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_125Mhz.csv new file mode 100644 index 0000000..47f7dbe --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_125Mhz.csv @@ -0,0 +1,65 @@ +# Number of profiles,,,,, +1,,,,, +# ProfileID,Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +125,1.00E+06,1.00E-12,Tiwari in ASIC 45nm,Tiwari Method for FreePDK45nm +# Stall consumption,,,,, +15.1,,,,, +1,lb,50.05,,, +2,lbu,41.94,,, +3,lh,48.51,,, +4,lhu,44.27,,, +5,lw,41.42,,, +6,lwl,41.42,,, +7,lwr,41.42,,, +8,sb,45.11,,, +9,sh,44.91,,, +10,sw,35.09,,, +11,swl,35.09,,, +12,swr,35.09,,, +13,addi,47.53,,, +14,addiu,48.69,,, +15,slti,40.54,,, +16,sltiu,40.39,,, +17,andi,37.32,,, +18,ori,50.4,,, +19,xori,48.17,,, +20,lui,41.42,,, +21,add,43.24,,, +22,addu,43.27,,, +23,sub,43.01,,, +24,subu,43.1,,, +25,slt,35.12,,, +26,sltu,35.13,,, +27,instr_and,35.14,,, +28,instr_or,54.14,,, +29,instr_xor,42.2,,, +30,instr_nor,45.13,,, +31,nop,32.58,,, +32,sll,35.09,,, +33,srl,35.03,,, +34,sra,35.15,,, +35,sllv,33.38,,, +36,srlv,43.5,,, +37,srav,40.48,,, +38,mult,46.51,,, +39,multu,46.12,,, +40,div,50.64,,, +41,divu,51.3,,, +42,mfhi,33.38,,, +43,mthi,33.39,,, +44,mflo,39.19,,, +45,mtlo,38.67,,, +46,j,48.96,,, +47,jal,53.76,,, +48,jr,40.49,,, +49,jalr,39.25,,, +50,beq,48.47,,, +51,bne,48.47,,, +52,blez,48.47,,, +53,bgtz,48.47,,, +54,bltz,48.47,,, +55,bgez,48.47,,, +56,bltzal,48.47,,, +57,bgezal,48.47,,, +58,sys_call,0,,, +59,instr_break,0,,, diff --git a/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_125_250_400Mhz.csv b/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_125_250_400Mhz.csv new file mode 100644 index 0000000..e00270b --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_125_250_400Mhz.csv @@ -0,0 +1,67 @@ +# Number of profiles +3 +#Characterization Frequency, Frequency Scale, EPI Scale,Characterization Name,Characterization Description +125,1.00E+06,1.00E-12,Tiwari in ASIC 45nm,Tiwari Method for FreePDK45nm +250,1.00E+06,1.00E-12,Tiwari in ASIC 45nm,Tiwari Method for FreePDK45nm +400,1.00E+06,1.00E-12,Tiwari in ASIC 45nm,Tiwari Method for FreePDK45nm +# Stall consumption +15.1,14.5,14.1 +1,lb,50.05,45.4,42.2 +2,lbu,41.94,41.58,38.57 +3,lh,48.51,45.76,43.2 +4,lhu,44.27,43.55,41.59 +5,lw,41.42,41.21,38.96 +6,lwl,41.42,41.21,38.96 +7,lwr,41.42,41.21,38.96 +8,sb,45.11,41.19,40.73 +9,sh,44.91,40.98,40.35 +10,sw,35.09,34.77,34.69 +11,swl,35.09,34.77,34.69 +12,swr,35.09,34.77,34.69 +13,addi,47.53,47.46,48.12 +14,addiu,48.69,47.71,48.37 +15,slti,40.54,40.06,39.72 +16,sltiu,40.39,39.83,39.6 +17,andi,37.32,36.68,36.61 +18,ori,50.4,51.64,45.06 +19,xori,48.17,47.18,44.36 +20,lui,41.42,41.21,38.96 +21,add,43.24,38.69,43.78 +22,addu,43.27,38.66,43.58 +23,sub,43.01,41.89,42.59 +24,subu,43.1,41.9,42.69 +25,slt,35.12,34.78,35.58 +26,sltu,35.13,34.76,35.48 +27,instr_and,35.14,34.71,34.55 +28,instr_or,54.14,43.68,43.87 +29,instr_xor,42.2,38.93,40.64 +30,instr_nor,45.13,45.45,47.86 +31,nop,32.58,32.38,32.28 +32,sll,35.09,34.77,34.69 +33,srl,35.03,34.84,34.71 +34,sra,35.15,49.58,35.36 +35,sllv,33.38,33.16,33.06 +36,srlv,43.5,38.56,40.45 +37,srav,40.48,36.78,41.31 +38,mult,46.51,42.69,41.23 +39,multu,46.12,41.98,40.22 +40,div,50.64,47.64,44.97 +41,divu,51.3,44.59,44.32 +42,mfhi,33.38,33.16,33.06 +43,mthi,33.39,33.16,33.06 +44,mflo,39.19,37.08,35.71 +45,mtlo,38.67,36.79,35.63 +46,j,48.96,39.58,39.84 +47,jal,53.76,43.17,43.21 +48,jr,40.49,37.9,35.16 +49,jalr,39.25,36.71,36.62 +50,beq,48.47,44.88,45.75 +51,bne,48.47,44.88,45.75 +52,blez,48.47,44.88,45.75 +53,bgtz,48.47,44.88,45.75 +54,bltz,48.47,44.88,45.75 +55,bgez,48.47,44.88,45.75 +56,bltzal,48.47,44.88,45.75 +57,bgezal,48.47,44.88,45.75 +58,sys_call,0,0,0 +59,instr_break,0,0,0 \ No newline at end of file diff --git a/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_250Mhz.csv b/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_250Mhz.csv new file mode 100644 index 0000000..f6bc067 --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_250Mhz.csv @@ -0,0 +1,65 @@ +# Number of profiles,,,,, +1,,,,, +# ProfileID,Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +250,1.00E+06,1.00E-12,Tiwari in ASIC 45nm,Tiwari Method for FreePDK45nm +# Stall consumption,,,,, +14.5,,,,, +1,lb,45.4,,, +2,lbu,41.58,,, +3,lh,45.76,,, +4,lhu,43.55,,, +5,lw,41.21,,, +6,lwl,41.21,,, +7,lwr,41.21,,, +8,sb,41.19,,, +9,sh,40.98,,, +10,sw,34.77,,, +11,swl,34.77,,, +12,swr,34.77,,, +13,addi,47.46,,, +14,addiu,47.71,,, +15,slti,40.06,,, +16,sltiu,39.83,,, +17,andi,36.68,,, +18,ori,51.64,,, +19,xori,47.18,,, +20,lui,41.21,,, +21,add,38.69,,, +22,addu,38.66,,, +23,sub,41.89,,, +24,subu,41.9,,, +25,slt,34.78,,, +26,sltu,34.76,,, +27,instr_and,34.71,,, +28,instr_or,43.68,,, +29,instr_xor,38.93,,, +30,instr_nor,45.45,,, +31,nop,32.38,,, +32,sll,34.77,,, +33,srl,34.84,,, +34,sra,49.58,,, +35,sllv,33.16,,, +36,srlv,38.56,,, +37,srav,36.78,,, +38,mult,42.69,,, +39,multu,41.98,,, +40,div,47.64,,, +41,divu,44.59,,, +42,mfhi,33.16,,, +43,mthi,33.16,,, +44,mflo,37.08,,, +45,mtlo,36.79,,, +46,j,39.58,,, +47,jal,43.17,,, +48,jr,37.9,,, +49,jalr,36.71,,, +50,beq,44.88,,, +51,bne,44.88,,, +52,blez,44.88,,, +53,bgtz,44.88,,, +54,bltz,44.88,,, +55,bgez,44.88,,, +56,bltzal,44.88,,, +57,bgezal,44.88,,, +58,sys_call,0,,, +59,instr_break,0,,, diff --git a/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_400Mhz.csv b/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_400Mhz.csv new file mode 100644 index 0000000..f8bb7b6 --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_400Mhz.csv @@ -0,0 +1,65 @@ +# Number of profiles,,,,, +1,,,,, +# ProfileID,Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +400,1.00E+06,1.00E-12,Tiwari in ASIC 45nm,Tiwari Method for FreePDK45nm +# Stall consumption,,,,, +14.1,,,,, +1,lb,42.2,,, +2,lbu,38.57,,, +3,lh,43.2,,, +4,lhu,41.59,,, +5,lw,38.96,,, +6,lwl,38.96,,, +7,lwr,38.96,,, +8,sb,40.73,,, +9,sh,40.35,,, +10,sw,34.69,,, +11,swl,34.69,,, +12,swr,34.69,,, +13,addi,48.12,,, +14,addiu,48.37,,, +15,slti,39.72,,, +16,sltiu,39.6,,, +17,andi,36.61,,, +18,ori,45.06,,, +19,xori,44.36,,, +20,lui,38.96,,, +21,add,43.78,,, +22,addu,43.58,,, +23,sub,42.59,,, +24,subu,42.69,,, +25,slt,35.58,,, +26,sltu,35.48,,, +27,instr_and,34.55,,, +28,instr_or,43.87,,, +29,instr_xor,40.64,,, +30,instr_nor,47.86,,, +31,nop,32.28,,, +32,sll,34.69,,, +33,srl,34.71,,, +34,sra,35.36,,, +35,sllv,33.06,,, +36,srlv,40.45,,, +37,srav,41.31,,, +38,mult,41.23,,, +39,multu,40.22,,, +40,div,44.97,,, +41,divu,44.32,,, +42,mfhi,33.06,,, +43,mthi,33.06,,, +44,mflo,35.71,,, +45,mtlo,35.63,,, +46,j,39.84,,, +47,jal,43.21,,, +48,jr,35.16,,, +49,jalr,36.62,,, +50,beq,45.75,,, +51,bne,45.75,,, +52,blez,45.75,,, +53,bgtz,45.75,,, +54,bltz,45.75,,, +55,bgez,45.75,,, +56,bltzal,45.75,,, +57,bgezal,45.75,,, +58,sys_call,0,,, +59,instr_break,0,,, diff --git a/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_50Mhz.csv b/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_50Mhz.csv new file mode 100644 index 0000000..fde4d71 --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_50Mhz.csv @@ -0,0 +1,65 @@ +# Number of profiles,,,,, +1,,,,, +# ProfileID,Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +50,1.00E+06,1.00E-12,Tiwari in ASIC 45nm,Tiwari Method for FreePDK45nm +# Stall consumption,,,,, +16.2,,,,, +1,lb,50.48,,, +2,lbu,42.44,,, +3,lh,48.9,,, +4,lhu,44.85,,, +5,lw,41.63,,, +6,lwl,41.63,,, +7,lwr,41.63,,, +8,sb,47.83,,, +9,sh,47.52,,, +10,sw,35.53,,, +11,swl,35.53,,, +12,swr,35.53,,, +13,addi,58.27,,, +14,addiu,58.63,,, +15,slti,41,,, +16,sltiu,40.78,,, +17,andi,37.63,,, +18,ori,48.16,,, +19,xori,53.01,,, +20,lui,41.63,,, +21,add,62.72,,, +22,addu,61.98,,, +23,sub,62.72,,, +24,subu,61.84,,, +25,slt,35.62,,, +26,sltu,35.51,,, +27,instr_and,35.63,,, +28,instr_or,55.31,,, +29,instr_xor,60.88,,, +30,instr_nor,53.77,,, +31,nop,32.97,,, +32,sll,35.53,,, +33,srl,35.53,,, +34,sra,53.47,,, +35,sllv,33.76,,, +36,srlv,36.99,,, +37,srav,60.11,,, +38,mult,55.11,,, +39,multu,53.54,,, +40,div,51.8,,, +41,divu,54.91,,, +42,mfhi,33.76,,, +43,mthi,33.77,,, +44,mflo,42.42,,, +45,mtlo,41.8,,, +46,j,53.54,,, +47,jal,58.98,,, +48,jr,44.25,,, +49,jalr,48.2,,, +50,beq,52.21,,, +51,bne,52.21,,, +52,blez,52.21,,, +53,bgtz,52.21,,, +54,bltz,52.21,,, +55,bgez,52.21,,, +56,bltzal,52.21,,, +57,bgezal,52.21,,, +58,sys_call,0,,, +59,instr_break,0,,, diff --git a/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_50_125_250_400Mhz.csv b/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_50_125_250_400Mhz.csv new file mode 100644 index 0000000..6277982 --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_ASIC_freepdk45_50_125_250_400Mhz.csv @@ -0,0 +1,68 @@ +# Number of profiles +4 +#Characterization Frequency, Frequency Scale, EPI Scale,Characterization Name,Characterization Description +50,1.00E+06,1.00E-12,Tiwari in ASIC 45nm,Tiwari Method for FreePDK45nm +125,1.00E+06,1.00E-12,Tiwari in ASIC 45nm,Tiwari Method for FreePDK45nm +250,1.00E+06,1.00E-12,Tiwari in ASIC 45nm,Tiwari Method for FreePDK45nm +400,1.00E+06,1.00E-12,Tiwari in ASIC 45nm,Tiwari Method for FreePDK45nm +# Stall consumption +16.2,15.1,14.5,14.1 +1,lb,50.48,50.05,45.4,42.2 +2,lbu,42.44,41.94,41.58,38.57 +3,lh,48.9,48.51,45.76,43.2 +4,lhu,44.85,44.27,43.55,41.59 +5,lw,41.63,41.42,41.21,38.96 +6,lwl,41.63,41.42,41.21,38.96 +7,lwr,41.63,41.42,41.21,38.96 +8,sb,47.83,45.11,41.19,40.73 +9,sh,47.52,44.91,40.98,40.35 +10,sw,35.53,35.09,34.77,34.69 +11,swl,35.53,35.09,34.77,34.69 +12,swr,35.53,35.09,34.77,34.69 +13,addi,58.27,47.53,47.46,48.12 +14,addiu,58.63,48.69,47.71,48.37 +15,slti,41,40.54,40.06,39.72 +16,sltiu,40.78,40.39,39.83,39.6 +17,andi,37.63,37.32,36.68,36.61 +18,ori,48.16,50.4,51.64,45.06 +19,xori,53.01,48.17,47.18,44.36 +20,lui,41.63,41.42,41.21,38.96 +21,add,62.72,43.24,38.69,43.78 +22,addu,61.98,43.27,38.66,43.58 +23,sub,62.72,43.01,41.89,42.59 +24,subu,61.84,43.1,41.9,42.69 +25,slt,35.62,35.12,34.78,35.58 +26,sltu,35.51,35.13,34.76,35.48 +27,instr_and,35.63,35.14,34.71,34.55 +28,instr_or,55.31,54.14,43.68,43.87 +29,instr_xor,60.88,42.2,38.93,40.64 +30,instr_nor,53.77,45.13,45.45,47.86 +31,nop,32.97,32.58,32.38,32.28 +32,sll,35.53,35.09,34.77,34.69 +33,srl,35.53,35.03,34.84,34.71 +34,sra,53.47,35.15,49.58,35.36 +35,sllv,33.76,33.38,33.16,33.06 +36,srlv,36.99,43.5,38.56,40.45 +37,srav,60.11,40.48,36.78,41.31 +38,mult,55.11,46.51,42.69,41.23 +39,multu,53.54,46.12,41.98,40.22 +40,div,51.8,50.64,47.64,44.97 +41,divu,54.91,51.3,44.59,44.32 +42,mfhi,33.76,33.38,33.16,33.06 +43,mthi,33.77,33.39,33.16,33.06 +44,mflo,42.42,39.19,37.08,35.71 +45,mtlo,41.8,38.67,36.79,35.63 +46,j,53.54,48.96,39.58,39.84 +47,jal,58.98,53.76,43.17,43.21 +48,jr,44.25,40.49,37.9,35.16 +49,jalr,48.2,39.25,36.71,36.62 +50,beq,52.21,48.47,44.88,45.75 +51,bne,52.21,48.47,44.88,45.75 +52,blez,52.21,48.47,44.88,45.75 +53,bgtz,52.21,48.47,44.88,45.75 +54,bltz,52.21,48.47,44.88,45.75 +55,bgez,52.21,48.47,44.88,45.75 +56,bltzal,52.21,48.47,44.88,45.75 +57,bgezal,52.21,48.47,44.88,45.75 +58,sys_call,0,0,0,0 +59,instr_break,0,0,0,0 \ No newline at end of file diff --git a/pdl/mips/powersc/acpower_table_mips_cycloneV_100Mhz.csv b/pdl/mips/powersc/acpower_table_mips_cycloneV_100Mhz.csv new file mode 100644 index 0000000..34ce680 --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_cycloneV_100Mhz.csv @@ -0,0 +1,65 @@ +# Number of profiles +1 +# ProfileID, Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +100,1e6,1e-9,Tiwari in Cyclone V,Tiwari Method for Altera Cyclone V +# Stall consumption +0 +1,lb,2.19 +2,lbu,1.34 +3,lh,2.13 +4,lhu,1.39 +5,lw,1.79 +6,lwl,1.79 +7,lwr,1.79 +8,sb,2.34 +9,sh,2.4 +10,sw,2.5 +11,swl,2.5 +12,swr,2.5 +13,addi,1.57 +14,addiu,1.57 +15,slti,1.49 +16,sltiu,1.49 +17,andi,1.75 +18,ori,1.83 +19,xori,1.77 +20,lui,1.89 +21,add,1.14 +22,addu,1.13 +23,sub,1.11 +24,subu,1.12 +25,slt,0.88 +26,sltu,0.89 +27,instr_and,1.16 +28,instr_or,1.36 +29,instr_xor,1.18 +30,instr_nor,1.17 +31,nop,0.82 +32,sll,1.33 +33,srl,1.35 +34,sra,1.32 +35,sllv,1.11 +36,srlv,1.12 +37,srav,1.26 +38,mult,1.03 +39,multu,1.04 +40,div,2.15 +41,divu,2.2 +42,mfhi,1.56 +43,mthi,0.99 +44,mflo,1.53 +45,mtlo,0.99 +46,j,2.41 +47,jal,1.34 +48,jr,1.58 +49,jalr,1.95 +50,beq,2.03 +51,bne,2.03 +52,blez,2.03 +53,bgtz,2.03 +54,bltz,2.03 +55,bgez,2.03 +56,bltzal,2.03 +57,bgezal,2.03 +58,sys_call,0 +59,instr_break,0 diff --git a/pdl/mips/powersc/acpower_table_mips_cycloneV_25Mhz.csv b/pdl/mips/powersc/acpower_table_mips_cycloneV_25Mhz.csv new file mode 100644 index 0000000..bcac1eb --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_cycloneV_25Mhz.csv @@ -0,0 +1,65 @@ +# Number of profiles +1 +# ProfileID, Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +25,1e6,1e-9,"Tiwari in Cyclone V","Tiwari Method for Altera Cyclone V" +# Stall consumption +1.64 +1,lb,3.12 +2,lbu,2.3 +3,lh,3.13 +4,lhu,2.38 +5,lw,2.75 +6,lwl,2.75 +7,lwr,2.75 +8,sb,3.27 +9,sh,3.31 +10,sw,3.43 +11,swl,3.43 +12,swr,3.43 +13,addi,2.65 +14,addiu,2.65 +15,slti,2.62 +16,sltiu,2.64 +17,andi,2.78 +18,ori,2.83 +19,xori,2.76 +20,lui,2.94 +21,add,2.12 +22,addu,2.12 +23,sub,2.08 +24,subu,2.1 +25,slt,1.8 +26,sltu,1.82 +27,instr_and,2.15 +28,instr_or,2.36 +29,instr_xor,2.17 +30,instr_nor,2.16 +31,nop,1.76 +32,sll,2.42 +33,srl,2.48 +34,sra,2.45 +35,sllv,2.13 +36,srlv,2.15 +37,srav,2.29 +38,mult,1.87 +39,multu,1.88 +40,div,3.12 +41,divu,3.2 +42,mfhi,2.56 +43,mthi,1.89 +44,mflo,2.54 +45,mtlo,1.85 +46,j,3.42 +47,jal,2.29 +48,jr,2.49 +49,jalr,2.94 +50,beq,3.03 +51,bne,3.03 +52,blez,3.03 +53,bgtz,3.03 +54,bltz,3.03 +55,bgez,3.03 +56,bltzal,3.03 +57,bgezal,3.03 +58,sys_call,0 +59,instr_break,0 diff --git a/pdl/mips/powersc/acpower_table_mips_cycloneV_25Mhz_100Mhz.csv b/pdl/mips/powersc/acpower_table_mips_cycloneV_25Mhz_100Mhz.csv new file mode 100644 index 0000000..b704874 --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_cycloneV_25Mhz_100Mhz.csv @@ -0,0 +1,66 @@ +# Number of profiles +2 +# ProfileID, Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +25,1e6,1e-9,Tiwari in Cyclone V,Tiwari Method for Altera Cyclone V +100,1e6,1e-9,Tiwari in Cyclone V,Tiwari Method for Altera Cyclone V +# Stall consumption +1.64,0 +1,lb,3.12,2.19 +2,lbu,2.3,1.34 +3,lh,3.13,2.13 +4,lhu,2.38,1.39 +5,lw,2.75,1.79 +6,lwl,2.75,1.79 +7,lwr,2.75,1.79 +8,sb,3.27,2.34 +9,sh,3.31,2.4 +10,sw,3.43,2.5 +11,swl,3.43,2.5 +12,swr,3.43,2.5 +13,addi,2.65,1.57 +14,addiu,2.65,1.57 +15,slti,2.62,1.49 +16,sltiu,2.64,1.49 +17,andi,2.78,1.75 +18,ori,2.83,1.83 +19,xori,2.76,1.77 +20,lui,2.94,1.89 +21,add,2.12,1.14 +22,addu,2.12,1.13 +23,sub,2.08,1.11 +24,subu,2.1,1.12 +25,slt,1.8,0.88 +26,sltu,1.82,0.89 +27,instr_and,2.15,1.16 +28,instr_or,2.36,1.36 +29,instr_xor,2.17,1.18 +30,instr_nor,2.16,1.17 +31,nop,1.76,0.82 +32,sll,2.42,1.33 +33,srl,2.48,1.35 +34,sra,2.45,1.32 +35,sllv,2.13,1.11 +36,srlv,2.15,1.12 +37,srav,2.29,1.26 +38,mult,1.87,1.03 +39,multu,1.88,1.04 +40,div,3.12,2.15 +41,divu,3.2,2.2 +42,mfhi,2.56,1.56 +43,mthi,1.89,0.99 +44,mflo,2.54,1.53 +45,mtlo,1.85,0.99 +46,j,3.42,2.41 +47,jal,2.29,1.34 +48,jr,2.49,1.58 +49,jalr,2.94,1.95 +50,beq,3.03,2.03 +51,bne,3.03,2.03 +52,blez,3.03,2.03 +53,bgtz,3.03,2.03 +54,bltz,3.03,2.03 +55,bgez,3.03,2.03 +56,bltzal,3.03,2.03 +57,bgezal,3.03,2.03 +58,sys_call,0,0 +59,instr_break,0,0 \ No newline at end of file diff --git a/pdl/mips/powersc/acpower_table_mips_cycloneV_50Mhz.csv b/pdl/mips/powersc/acpower_table_mips_cycloneV_50Mhz.csv new file mode 100644 index 0000000..63d7282 --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_cycloneV_50Mhz.csv @@ -0,0 +1,65 @@ +# Number of profiles +1 +# ProfileID, Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +100,1e-6,1e+AC0-9,"Tiwari in Cyclone V","Tiwari Method for Altera Cyclone V" +# Stall consumption +0 +1,lb,1.25 +2,lbu,0.88 +3,lh,1.26 +4,lhu,0.91 +5,lw,1.09 +6,lwl,1.09 +7,lwr,1.09 +8,sb,1.35 +9,sh,1.37 +10,sw,1.43 +11,swl,1.43 +12,swr,1.43 +13,addi,0.95 +14,addiu,0.96 +15,slti,0.92 +16,sltiu,0.93 +17,andi,1.04 +18,ori,1.06 +19,xori,1.06 +20,lui,1.11 +21,add,0.75 +22,addu,0.76 +23,sub,0.73 +24,subu,0.75 +25,slt,0.64 +26,sltu,0.66 +27,instr_and,0.78 +28,instr_or,0.87 +29,instr_xor,0.77 +30,instr_nor,0.77 +31,nop,0.58 +32,sll,0.89 +33,srl,0.91 +34,sra,0.91 +35,sllv,0.74 +36,srlv,0.75 +37,srav,0.81 +38,mult,0.69 +39,multu,0.7 +40,div,1.27 +41,divu,1.32 +42,mfhi,0.91 +43,mthi,0.68 +44,mflo,0.91 +45,mtlo,0.68 +46,j,1.39 +47,jal,0.84 +48,jr,0.99 +49,jalr,1.16 +50,beq,1.23 +51,bne,1.23 +52,blez,1.23 +53,bgtz,1.23 +54,bltz,1.23 +55,bgez,1.23 +56,bltzal,1.23 +57,bgezal,1.23 +58,sys_call,0 +59,instr_break,0 diff --git a/pdl/mips/powersc/acpower_table_mips_ep3sl50_100mhz.csv b/pdl/mips/powersc/acpower_table_mips_ep3sl50_100mhz.csv new file mode 100644 index 0000000..5b23c70 --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_ep3sl50_100mhz.csv @@ -0,0 +1,65 @@ +# Number of profiles +1 +# ProfileID, Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +100,1e6,1e-9,"Tiwari in Cyclone V","Tiwari Method for Altera Cyclone V" +# Stall consumption +0 +1,lb,4.18 +2,lbu,2.33 +3,lh,4.39 +4,lhu,2.46 +5,lw,3.49 +6,lwl,3.49 +7,lwr,3.49 +8,sb,4.94 +9,sh,5.14 +10,sw,5.45 +11,swl,5.45 +12,swr,5.45 +13,addi,1.87 +14,addiu,1.87 +15,slti,1.79 +16,sltiu,1.79 +17,andi,1.95 +18,ori,1.92 +19,xori,1.96 +20,lui,2.45 +21,add,1.62 +22,addu,1.58 +23,sub,1.58 +24,subu,1.58 +25,slt,1.34 +26,sltu,1.35 +27,instr_and,1.57 +28,instr_or,1.56 +29,instr_xor,1.63 +30,instr_nor,1.61 +31,nop,1.26 +32,sll,2.02 +33,srl,2.13 +34,sra,2.12 +35,sllv,1.56 +36,srlv,1.57 +37,srav,1.57 +38,mult,1.47 +39,multu,1.46 +40,div,2.28 +41,divu,2.69 +42,mfhi,2.37 +43,mthi,1.29 +44,mflo,2.24 +45,mtlo,1.3 +46,j,5.69 +47,jal,1.78 +48,jr,3.07 +49,jalr,3.66 +50,beq,3.51 +51,bne,3.51 +52,blez,3.51 +53,bgtz,3.51 +54,bltz,3.51 +55,bgez,3.51 +56,bltzal,3.51 +57,bgezal,3.51 +58,sys_call,0 +59,instr_break,0 diff --git a/pdl/mips/powersc/acpower_table_mips_xc3s1200e_100Mhz.csv b/pdl/mips/powersc/acpower_table_mips_xc3s1200e_100Mhz.csv new file mode 100644 index 0000000..9f671c1 --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_xc3s1200e_100Mhz.csv @@ -0,0 +1,65 @@ +#Number of profiles +1 +#ProfileID,Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +100,1E6,1E-9,"mips-plasma-xc3s1200e","Plasma",Characterization,xc3s1200e at 100MHz" +#Stall consumption +0.171 +1,lb,5.59 +2,lbu,4.33 +3,lh,5.97 +4,lhu,4.02 +5,lw,5.25 +6,lwl,5.25 +7,lwr,5.25 +8,sb,6.48 +9,sh,6.73 +10,sw,6.84 +11,swl,6.84 +12,swr,6.84 +13,addi,1.55 +14,addiu,1.57 +15,slti,1.03 +16,sltiu,0.96 +17,andi,0.86 +18,ori,0.91 +19,xori,1.32 +20,lui,0.89 +21,add,1.71 +22,addu,1.65 +23,sub,1.72 +24,subu,1.63 +25,slt,0.7 +26,sltu,0.7 +27,instr_and,0.7 +28,instr_or,0.91 +29,instr_xor,1.64 +30,instr_nor,1.48 +31,nop,0.5 +32,sll,0.76 +33,srl,0.74 +34,sra,1.02 +35,sllv,0.71 +36,srlv,0.7 +37,srav,1 +38,mult,1.4 +39,multu,1.37 +40,div,2.89 +41,divu,2.88 +42,mfhi,0.61 +43,mthi,0.95 +44,mflo,0.61 +45,mtlo,0.91 +46,j,3.13 +47,jal,3.51 +48,jr,5.29 +49,jalr,4.99 +50,beq,2.8 +51,bne,2.8 +52,blez,2.8 +53,bgtz,2.8 +54,bltz,2.8 +55,bgez,2.8 +56,bltzal,2.8 +57,bgezal,2.8 +58,sys_call,0 +59,instr_break,0 \ No newline at end of file diff --git a/pdl/mips/powersc/acpower_table_mips_xc4vlx15_100Mhz.csv b/pdl/mips/powersc/acpower_table_mips_xc4vlx15_100Mhz.csv new file mode 100644 index 0000000..a764999 --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_xc4vlx15_100Mhz.csv @@ -0,0 +1,65 @@ +# Number of profiles +1 +# ProfileID, Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +100,1E6,1E-9,"Mips plasma xc2v1000i","Plasma Characterization xc2v1000i at 100MHz" +# Stall consumption +0 +1,lb,5.91 +2,lbu,4.76 +3,lh,6.43 +4,lhu,4.42 +5,lw,5.63 +6,lwl,5.63 +7,lwr,5.63 +8,sb,6.83 +9,sh,7.09 +10,sw,7.2 +11,swl,7.2 +12,swr,7.2 +13,addi,2.15 +14,addiu,2.17 +15,slti,1.59 +16,sltiu,1.52 +17,andi,1.36 +18,ori,1.42 +19,xori,1.89 +20,lui,1.4 +21,add,2.41 +22,addu,2.33 +23,sub,2.42 +24,subu,2.31 +25,slt,1.14 +26,sltu,1.14 +27,instr_and,1.14 +28,instr_or,1.42 +29,instr_xor,2.36 +30,instr_nor,2.13 +31,nop,0.82 +32,sll,1.19 +33,srl,1.18 +34,sra,1.53 +35,sllv,1.15 +36,srlv,1.14 +37,srav,1.53 +38,mult,2.05 +39,multu,2.01 +40,div,3.61 +41,divu,3.66 +42,mfhi,0.98 +43,mthi,1.38 +44,mflo,0.98 +45,mtlo,1.33 +46,j,3.83 +47,jal,4.31 +48,jr,5.34 +49,jalr,5.13 +50,beq,3.29 +51,bne,3.29 +52,blez,3.29 +53,bgtz,3.29 +54,bltz,3.29 +55,bgez,3.29 +56,bltzal,3.29 +57,bgezal,3.29 +58,sys_call,0 +59,instr_break,0 diff --git a/pdl/mips/powersc/acpower_table_mips_xc5vlx50t_100Mhz.csv b/pdl/mips/powersc/acpower_table_mips_xc5vlx50t_100Mhz.csv new file mode 100644 index 0000000..fc6f43c --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_xc5vlx50t_100Mhz.csv @@ -0,0 +1,65 @@ +# Number of profiles,, +1,, +# ProfileID, Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +100,1E6,1E-9,"mips plasma xc5vlx50t", "Plasma Characterization xc5vlx50t at 100MHz" +# Stall consumption +0 +1,lb,4.73 +2,lbu,3.85 +3,lh,5.36 +4,lhu,3.33 +5,lw,4.66 +6,lwl,4.66 +7,lwr,4.66 +8,sb,5.84 +9,sh,6.01 +10,sw,6.23 +11,swl,6.23 +12,swr,6.23 +13,addi,1.04 +14,addiu,1.05 +15,slti,0.83 +16,sltiu,0.81 +17,andi,0.76 +18,ori,0.8 +19,xori,0.93 +20,lui,0.77 +21,add,1.13 +22,addu,1.11 +23,sub,1.13 +24,subu,1.1 +25,slt,0.65 +26,sltu,0.65 +27,instr_and,0.65 +28,instr_or,0.8 +29,instr_xor,1.11 +30,instr_nor,1.02 +31,nop,0.53 +32,sll,0.67 +33,srl,0.67 +34,sra,0.91 +35,sllv,0.65 +36,srlv,0.65 +37,srav,0.84 +38,mult,0.99 +39,multu,0.98 +40,div,2.21 +41,divu,1.93 +42,mfhi,0.58 +43,mthi,0.71 +44,mflo,0.58 +45,mtlo,0.7 +46,j,2.88 +47,jal,3.88 +48,jr,3.95 +49,jalr,3.71 +50,beq,2.47 +51,bne,2.47 +52,blez,2.47 +53,bgtz,2.47 +54,bltz,2.47 +55,bgez,2.47 +56,bltzal,2.47 +57,bgezal,2.47 +58,sys_call,0 +59,instr_break,0 diff --git a/pdl/mips/powersc/acpower_table_mips_xc6slx75_100Mhz.csv b/pdl/mips/powersc/acpower_table_mips_xc6slx75_100Mhz.csv new file mode 100644 index 0000000..eb2334c --- /dev/null +++ b/pdl/mips/powersc/acpower_table_mips_xc6slx75_100Mhz.csv @@ -0,0 +1,65 @@ +# Number of profiles +1 +# ProfileID,Characterization,Frequency,Frequency,Scale,EPI,Scale,Characterization,Name,Characterization,Description +100,1E6,1E-9,"mips plasma xc6slx75","Plasma Characterization xc6slx75 at 100MHz" +# Stall consumption +0 +1,lb,5.08 +2,lbu,3.95 +3,lh,5.82 +4,lhu,3.61 +5,lw,5.1 +6,lwl,5.1 +7,lwr,5.1 +8,sb,6.3 +9,sh,6.53 +10,sw,6.64 +11,swl,6.64 +12,swr,6.64 +13,addi,1.24 +14,addiu,1.24 +15,slti,0.78 +16,sltiu,0.74 +17,andi,0.66 +18,ori,0.67 +19,xori,0.93 +20,lui,0.65 +21,add,1.24 +22,addu,1.2 +23,sub,1.24 +24,subu,1.2 +25,slt,0.56 +26,sltu,0.56 +27,instr_and,0.56 +28,instr_or,0.58 +29,instr_xor,1.18 +30,instr_nor,1.05 +31,nop,0.44 +32,sll,0.56 +33,srl,0.56 +34,sra,0.61 +35,sllv,0.56 +36,srlv,0.56 +37,srav,0.6 +38,mult,1.01 +39,multu,1 +40,div,2.52 +41,divu,2.61 +42,mfhi,0.48 +43,mthi,0.73 +44,mflo,0.48 +45,mtlo,0.69 +46,j,2.85 +47,jal,2.99 +48,jr,3.67 +49,jalr,3.44 +50,beq,2.32 +51,bne,2.32 +52,blez,2.32 +53,bgtz,2.32 +54,bltz,2.32 +55,bgez,2.32 +56,bltzal,2.32 +57,bgezal,2.32 +58,sys_call,0 +59,instr_break,0 diff --git a/pdl/powerpc/.gitignore b/pdl/powerpc/.gitignore new file mode 100644 index 0000000..2636a66 --- /dev/null +++ b/pdl/powerpc/.gitignore @@ -0,0 +1,26 @@ +Makefile +Makefile.archc +main.cpp +main.cpp.tmpl +*.o +*.x +*.a +powerpc.H +powerpc.cpp +powerpc.x +powerpc_arch.H +powerpc_arch.cpp +powerpc_arch_ref.H +powerpc_arch_ref.cpp +powerpc_bhv_macros.H +powerpc_isa.H +powerpc_isa.cpp.tmpl +powerpc_isa_init.cpp +powerpc_parms.H +powerpc_syscall.H +powerpc_syscall.H.tmpl +powerpc_ih_bhv_macros.H +powerpc_intr_handlers.H +powerpc_intr_handlers.cpp* + + diff --git a/pdl/powerpc/CONTRIBUTING.md b/pdl/powerpc/CONTRIBUTING.md new file mode 100644 index 0000000..23c5e58 --- /dev/null +++ b/pdl/powerpc/CONTRIBUTING.md @@ -0,0 +1,12 @@ +# Contributing + +## Submitting a Pull Request + +1. Fork it. +2. Create a branch (`git checkout -b my_project`) +3. Commit your changes (`git commit -a`) [Tips for better commit message](https://robots.thoughtbot.com/5-useful-tips-for-a-better-commit-message) +4. Push to the branch (`git push origin my_project`) +5. Open a [Pull Request][1] +6. Enjoy a refreshing Diet Coke and wait doing more + +[1]: https://github.com/ArchC/powerpc/pulls diff --git a/pdl/powerpc/COPYING b/pdl/powerpc/COPYING new file mode 100644 index 0000000..d445e88 --- /dev/null +++ b/pdl/powerpc/COPYING @@ -0,0 +1,74 @@ + ArchC DEVELOPMENT PUBLIC LICENSE + +Everyone is permitted to copy and distribute verbatim copies of this +license document, but changing it is not allowed. + + Preamble + +You received this software from a trusted source and for research +purposes. Using or modifying this Program implies full acceptance of +this license. Please contact the person who send or gave you access to +this program for further information. + + ArchC DEVELOPMENT PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + +This license extends to all Programs contained in the package that +you received, including all subdirectories from this root, except if +the file header indicates another license. + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. + + 1. You may copy verbatim copies of the Program's source code as you +receive it, in any medium, for personal use, provided that you copy +copyright notice and disclaimer of warranty; and keep intact all the +notices that refer to this License and to the absence of any warranty. + +Personal use can be extended to a laboratory facility or a shared room +only if you are in charge of a research group that contributes to this +program and only with developing and research purposes. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy such +modifications or work under the terms of Section 1 above, provided +that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must not share, publish or distribute this program, either + in parts or in original form. You must not share, publish or + distribute programs that use this Program, either in parts or in + its original form. + + + 3. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or using the Program (or any work based on the Program), you +indicate your acceptance of this License to do so, and all its terms +and conditions for copying, distributing or modifying the Program or +works based on it. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the software in its development phase. + + NO WARRANTY + + 4. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + END OF TERMS AND CONDITIONS + diff --git a/pdl/powerpc/HISTORY.md b/pdl/powerpc/HISTORY.md new file mode 100644 index 0000000..78bb301 --- /dev/null +++ b/pdl/powerpc/HISTORY.md @@ -0,0 +1,62 @@ +## 2.4.0 + +* Revision numbers following the ArchC release +* Instructions with cycles annotations +* Two new .ac files to use with MPSoCBench (block and nonblock) +* powerpc_isa.cpp using the reserved work DATA_PORT to data request. See the [commit message](https://github.com/ArchC/powerpc/commit/18be8f932ee67c61795a331aa4682c866c864358). +* Interrupt handler support. It is inactive in standalone simulator. + +[Full changelog](https://github.com/ArchC/powerpc/compare/v2.3.0...v2.4.0) + +## 2.3.0 +* Revision numbers following the ArchC release ++ Added id register for core identification + +[Full changelog](https://github.com/ArchC/powerpc/compare/v1.0.2...v2.3.0) + +## 1.0.1 +* Updated syscall emulation to work with new version of libac_sysc + (this new version of libac_sysc is used by GCC 4.8 cross compiler and above) + +[Full changelog](https://github.com/ArchC/powerpc/compare/v1.0.0...v1.0.1) + +## 1.0.0 +* ArchC 2.2 compliant + +[Full changelog](https://github.com/ArchC/powerpc/compare/v0.7.4...v1.0.0) + +## 0.7.4 +* Fixed gdb_funcs bug when using ArchC 2.0 or later +* ArchC 2.1 compliant + +[Full changelog](https://github.com/ArchC/powerpc/compare/v0.7.3...v0.7.4) + +## 0.7.3 ++ Added binary utilities support files +* Adjusted mullhw syntax +* ArchC 2.0 compliant + +[Full changelog](https://github.com/ArchC/powerpc/compare/v0.7.2...v0.7.3) + +## 0.7.2-archc2.0beta3 + ++ Added license headers + +[Full changelog](https://github.com/ArchC/powerpc/compare/v0.7.1-1...v0.7.2) + +## 0.7.1-archc2.0beta1 + +* Model compliant with ArchC 2.0beta1 + +## 0.7.1 + ++ Included optional properties to optimize compiled simulation +* Changed dprintf function (conflict with native dprintf()) +* Changed SC1 type (to include the LEV field) +* Changed XL2 type (to include the BH field) ++ Added assembly language information + +## 0.7.0 + +* Model passed selected Mediabench and Mibench applications ++ Included file for GDB integration diff --git a/pdl/powerpc/README.md b/pdl/powerpc/README.md new file mode 100644 index 0000000..4116c2f --- /dev/null +++ b/pdl/powerpc/README.md @@ -0,0 +1,74 @@ +PowerPC ArchC functional model +=============================== + +This is the POWERPC ArchC functional model. + +License +------- + - ArchC models are provided under the ArchC license. + See [Copying](COPYING) file for details on this license. + +acsim +----- +This model has the system call emulation functions implemented, +so it is a good idea to turn on the ABI option. + +To use acsim, the interpreted simulator: + + acsim powerpc.ac -abi (create the simulator) + make (compile) + powerpc.x --load= [args] (run an application) + +The [args] are optional arguments for the application. + +There are two formats recognized for application : +- ELF binary matching ArchC specifications +- hexadecimal text file for ArchC + + +Binary utilities +---------------- +To generate binary utilities use: + + acbingen.sh -i -a powerpc.ac + +This will generate the tools source files using the architeture +name (if omitted, powerpc is used), copy them to the +binutils source tree, build and install them into the directory + (which -must- be an absolute path). +Use "acbingen.sh -h" to get information about the command-line +options available. + + +Change history +------------ + +See [History](HISTORY.md) + + +Contributing +------------ + +See [Contributing](CONTRIBUTING.md) + + +More +---- + +Remember that ArchC models and SystemC library must be compiled with +the same GCC version, otherwise you will get compilation problems. + +Several documents which further information can be found in the 'doc' +subdirectory. + +You can find language overview, models, and documentation at +http://www.archc.org + + + +Thanks for the interest. We hope you enjoy using ArchC! + +The ArchC Team +Computer Systems Laboratory (LSC) +IC-UNICAMP +http://www.lsc.ic.unicamp.br diff --git a/pdl/powerpc/compiler_info.ac b/pdl/powerpc/compiler_info.ac new file mode 100644 index 0000000..c048d11 --- /dev/null +++ b/pdl/powerpc/compiler_info.ac @@ -0,0 +1,256 @@ +// PowerPC C Compiler Backend Information File +// Part of PowerPC ArchC Model + +//====================-- Machine specific rules --============================// + +// compu is a compare operator which forces unsigned comparisons +// and produces signed flags +define operator compu as arity 2; + +(cjump const:cond:ult (comp aa:any bb:any) cc:any) => + (cjump const:cond:lt (compu aa:any bb:any) cc:any); +(cjump const:cond:ugt (comp aa:any bb:any) cc:any) => + (cjump const:cond:gt (compu aa:any bb:any) cc:any); +(cjump const:cond:uge (comp aa:any bb:any) cc:any) => + (cjump const:cond:ge (compu aa:any bb:any) cc:any); +(cjump const:cond:ule (comp aa:any bb:any) cc:any) => + (cjump const:cond:le (compu aa:any bb:any) cc:any); + +(nop) => + (transfer AReg:regs (or AReg:regs AReg:regs const:byte:0)); + +(transfer a:regs b:regs) => + (transfer a:regs (or b:regs b:regs)); + +//=====================-- Registers definitions --============================// + +define registers GPR:regs as ( + r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 + r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 +); + +define operand spec as size 32 like int; + +define registers SPECIAL:spec as ( + CR CTR LR +); + +//===========================-- ABI stuff --==================================// + +redefine operand tgtimm size to 16; + +define abi as ( + define callee save registers as (r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 + r24 r25 r26 r27 r28 r29 r30 r31); + define reserved registers as (r1 r2 r13); + define auxiliar registers as (r11 r12); + //define calling convention for int as stack size 4 alignment 4; + define calling convention for int as (r3 r4 r5 r6 r7 r8 r9 r10); + define calling convention for int as stack size 4 alignment 4; + define return convention for int as (r3 r4); + //define programcounter register as PC; + define stackpointer register as r13; + define framepointer register as r14; + define return register as LR; + define stack grows down alignment 8; + define pcoffset -8; +); + +//==================-- Instruction semantic fragments --======================// + + + +//=======================-- Instructions definitions --=======================// + +// * DATA PROCESSING - FIXED POINT INSTRUCTIONS * + +/* Logical */ +define instruction ande semantic as ( + (transfer Op1:GPR (and Op2:GPR Op3:GPR)); +) cost 1; +define instruction andi_ semantic as ( + (transfer Op1:GPR (and Op2:GPR imm:Op3:tgtimm)); +) cost 1; +define instruction ore semantic as ( + (transfer Op1:GPR (or Op2:GPR Op3:GPR)); +) cost 1; +define instruction ori semantic as ( + //let Op1 = "r0", Op2 = "r0", Op3 = "0" in + //(nop); + (transfer Op1:GPR (or Op2:GPR imm:Op3:tgtimm)); +) cost 1; +define instruction xxor semantic as ( + (transfer Op1:GPR (xor Op2:GPR Op3:GPR)); +) cost 1; +define instruction xori semantic as ( + (transfer Op1:GPR (xor Op2:GPR imm:Op3:tgtimm)); +) cost 1; + +// Shift +define instruction rlwinm semantic as ( + let Op4 = "0", Op5 = "31" in + (transfer Op1:GPR (rol Op2:GPR imm:Op3:tgtimm)); +) cost 1; +define instruction slw semantic as ( + (transfer Op1:GPR (shl Op2:GPR Op3:GPR)); +) cost 1; +define instruction srw semantic as ( + (transfer Op1:GPR (shr Op2:GPR Op3:GPR)); +) cost 1; +define instruction srawi semantic as ( + (transfer Op1:GPR (asr Op2:GPR imm:Op3:tgtimm)); +) cost 1; +define instruction sraw semantic as ( + (transfer Op1:GPR (asr Op2:GPR Op3:GPR)); +) cost 1; + +// Special move instructions +define instruction mtspr semantic as () cost 10; +define instruction mtspr semantic as ( + (transfer LR:SPECIAL Op1:GPR); +) cost 10; + +define instruction mfspr semantic as () cost 10; +define instruction mfspr semantic as ( + (transfer Op1:GPR LR:SPECIAL); +) cost 10; + +// Arithmetic +define instruction add semantic as ( + (transfer Op1:GPR (+ Op2:GPR Op3:GPR)); +) cost 1; + +define instruction addi semantic as ( + (transfer Op1:GPR imm:Op2:tgtimm); +) cost 1; +define instruction addi semantic as () cost 1; +define instruction addi semantic as () cost 1; +define instruction addi semantic as ( + (transfer Op1:GPR (+ Op2:GPR imm:Op3:tgtimm)); +) cost 1; + +define instruction subf semantic as ( + (transfer Op1:GPR (- Op3:GPR Op2:GPR)); +) cost 1; + +define instruction subfic semantic as ( + (transfer Op1:GPR (- imm:Op3:tgtimm Op2:GPR)); +) cost 1; + +define instruction neg semantic as ( + (transfer Op1:GPR (~ Op2:GPR)); +) cost 1; + +define instruction mulli semantic as ( + (transfer Op1:GPR (* Op2:GPR imm:Op3:tgtimm)); +) cost 10; + +define instruction mullw semantic as ( + (transfer Op1:GPR (* Op2:GPR Op3:GPR)); +) cost 10; + +define instruction mulhw semantic as ( + (transfer Op1:GPR (mulhs Op2:GPR Op3:GPR)); +) cost 10; + +define instruction mulhwu semantic as ( + (transfer Op1:GPR (mulhu Op2:GPR Op3:GPR)); +) cost 10; + +// * LOAD/STORE INSTRUCTIONS * +define instruction lbz semantic as ( + (transfer Op1:GPR (zext (memref (+ Op3:GPR imm:Op2:tgtimm)) const:num:8)); +) cost 1; +define instruction lbzx semantic as ( + (transfer Op1:GPR (zext (memref (+ Op2:GPR Op3:GPR)) const:num:8)); +) cost 1; +define instruction lhz semantic as ( + (transfer Op1:GPR (zext (memref (+ Op3:GPR imm:Op2:tgtimm)) const:num:16)); +) cost 1; +define instruction lhzx semantic as ( + (transfer Op1:GPR (zext (memref (+ Op2:GPR Op3:GPR)) const:num:16)); +) cost 1; +define instruction lha semantic as ( + (transfer Op1:GPR (sext (memref (+ Op3:GPR imm:Op2:tgtimm)) const:num:16)); +) cost 1; +define instruction lhax semantic as ( + (transfer Op1:GPR (sext (memref (+ Op2:GPR Op3:GPR)) const:num:16)); +) cost 1; +define instruction lwz semantic as ( + (transfer Op1:GPR (memref (+ Op3:GPR imm:Op2:tgtimm))); +) cost 1; +define instruction lwzx semantic as ( + (transfer Op1:GPR (memref (+ Op2:GPR Op3:GPR))); +) cost 1; + +define instruction stb semantic as ( + (transfer (memref (+ Op3:GPR imm:Op2:tgtimm)) (trunc Op1:GPR const:num:8)); +) cost 1; +define instruction stbx semantic as ( + (transfer (memref (+ Op2:GPR Op3:GPR)) (trunc Op1:GPR const:num:8)); +) cost 1; +define instruction sth semantic as ( + (transfer (memref (+ Op3:GPR imm:Op2:tgtimm)) (trunc Op1:GPR const:num:16)); +) cost 1; +define instruction sthx semantic as ( + (transfer (memref (+ Op2:GPR Op3:GPR)) (trunc Op1:GPR const:num:16)); +) cost 1; +define instruction stw semantic as ( + (transfer (memref (+ Op3:GPR imm:Op2:tgtimm)) Op1:GPR); +) cost 1; +define instruction stwx semantic as ( + (transfer (memref (+ Op2:GPR Op3:GPR)) Op1:GPR); +) cost 1; + +define instruction extsb semantic as ( + (transfer Op1:GPR (sext Op2:GPR const:num:8)); +) cost 1; +define instruction extsh semantic as ( + (transfer Op1:GPR (sext Op2:GPR const:num:16)); +) cost 1; + +// * BRANCH INSTRUCTIONS AND COMPARISON * + +define instruction cmp semantic as ( + let Op1 = "0" in + (transfer CR:SPECIAL (comp Op2:GPR Op3:GPR)); +) cost 1; +define instruction cmpi semantic as ( + let Op1 = "0" in + (transfer CR:SPECIAL (comp Op2:GPR imm:Op3:tgtimm)); +) cost 1; +define instruction cmpl semantic as ( + let Op1 = "0" in + (transfer CR:SPECIAL (compu Op2:GPR Op3:GPR)); +) cost 1; +define instruction cmpli semantic as ( + let Op1 = "0" in + (transfer CR:SPECIAL (compu Op2:GPR imm:Op3:tgtimm)); +) cost 1; + +define instruction ba semantic as ( + (jump imm:Op1:int); +) cost 1; +define instruction bla semantic as ( + (call imm:Op1:int); +) cost 1; + +define instruction bclr semantic as ( + (ret); +) cost 1; + + +define instruction bc semantic as ( + let Op1 = "12", Op2 = "0" in + (cjump const:cond:lt CR:SPECIAL imm:Op3:int); + let Op1 = "12", Op2 = "1" in + (cjump const:cond:gt CR:SPECIAL imm:Op3:int); + let Op1 = "4", Op2 = "1" in + (cjump const:cond:le CR:SPECIAL imm:Op3:int); + let Op1 = "4", Op2 = "0" in + (cjump const:cond:ge CR:SPECIAL imm:Op3:int); + let Op1 = "4", Op2 = "2" in + (cjump const:cond:ne CR:SPECIAL imm:Op3:int); + let Op1 = "12", Op2 = "2" in + (cjump const:cond:eq CR:SPECIAL imm:Op3:int); +) cost 1; diff --git a/pdl/powerpc/defines_gdb b/pdl/powerpc/defines_gdb new file mode 100644 index 0000000..2d0f62b --- /dev/null +++ b/pdl/powerpc/defines_gdb @@ -0,0 +1,20 @@ +//Number of registers +#define NUM_REGISTERS 105 + +//Number stack pointer register +#define NUM_REGISTER_SP 1 + +//Number frame pointer register +#define NUM_REGISTER_FP 284 + +//Number program counter register +#define NUM_REGISTER_PC 96 + +//Number first return procedures register +#define NUM_REGISTER_RET1 99 + +//Number second return procedures register - only SPARC +#define NUM_REGISTER_RET2 -1 + +//Offset add in pc register - only SPARC +#define OFFSET 0 \ No newline at end of file diff --git a/pdl/powerpc/modifiers b/pdl/powerpc/modifiers new file mode 100644 index 0000000..94a07d8 --- /dev/null +++ b/pdl/powerpc/modifiers @@ -0,0 +1,24 @@ + +ac_modifier_encode(carry) +{ + reloc->D1.d = (reloc->input + 0x00008000) >> 16; + +// reloc->output = (reloc->input + 0x00008000) >> 16; +} + + +ac_modifier_decode(carry) +{ +} + + +ac_modifier_encode(pcrel) +{ + reloc->output = (reloc->input - reloc->address) >> 2; +} + + +ac_modifier_decode(pcrel) +{ + reloc->output = (reloc->input << 2) + reloc->address; +} diff --git a/pdl/powerpc/powerpc.ac b/pdl/powerpc/powerpc.ac new file mode 100644 index 0000000..c2bcf0e --- /dev/null +++ b/pdl/powerpc/powerpc.ac @@ -0,0 +1,54 @@ +/** + * @file powerpc.ac + * @author Bruno Corsi dos Santos + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Thu, 29 Jun 2006 14:49:05 -0300 + * + * @brief The ArchC POWERPC functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + */ + +AC_ARCH(powerpc) { + + ac_wordsize 32; + + ac_mem MEM:512M; + + ac_regbank GPR:32; + + ac_reg SPRG4; + ac_reg SPRG5; + ac_reg SPRG6; + ac_reg SPRG7; + ac_reg USPRG0; + + ac_reg XER; + + ac_reg MSR; + +// sc instruction not tested/used + ac_reg EVPR; + ac_reg SRR0; + ac_reg SRR1; + + ac_reg CR; + ac_reg LR; + ac_reg CTR; + ac_reg id; + ARCH_CTOR(powerpc) { + ac_isa("powerpc_isa.ac"); + ac_gdb("powerpc.xml"); + set_endian("big"); + }; + +}; diff --git a/pdl/powerpc/powerpc.xml b/pdl/powerpc/powerpc.xml new file mode 100644 index 0000000..28cf1e7 --- /dev/null +++ b/pdl/powerpc/powerpc.xml @@ -0,0 +1,83 @@ + + + + + + powerpc + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pdl/powerpc/powerpc64.ac b/pdl/powerpc/powerpc64.ac new file mode 100644 index 0000000..2f1d046 --- /dev/null +++ b/pdl/powerpc/powerpc64.ac @@ -0,0 +1,53 @@ +/** + * @file powerpc64.ac + * @author Jan Vrany + * + * LabWare + * + * @version 1.0 + * @date Mon, 14 Nov 2022 + * + * @brief The ArchC POWERPC64 functional model. + * + * @attention Copyright (C) 2022-2022 --- LabWare + * + */ + +AC_ARCH(powerpc64) { + + ac_wordsize 64; + + ac_mem MEM:512M; + + ac_regbank GPR:32; + + ac_reg SPRG4; + ac_reg SPRG5; + ac_reg SPRG6; + ac_reg SPRG7; + ac_reg USPRG0; + + ac_reg XER; + + ac_reg MSR; + +// sc instruction not tested/used + ac_reg EVPR; + ac_reg SRR0; + ac_reg SRR1; + + ac_reg CR; + ac_reg LR; + ac_reg CTR; + ac_reg id; + + ARCH_CTOR(powerpc64) { + ac_isa("powerpc_isa.ac"); + ac_isa("powerpc64_isa.ac"); + ac_gdb("powerpc.xml"); + + // PPC64le seems to be more common at least in + // Linux world. + set_endian("little"); + }; +}; diff --git a/pdl/powerpc/powerpc64_isa.ac b/pdl/powerpc/powerpc64_isa.ac new file mode 100644 index 0000000..e45a938 --- /dev/null +++ b/pdl/powerpc/powerpc64_isa.ac @@ -0,0 +1,120 @@ +/* ex: set tabstop=2 expandtab: + -*- Mode: C; tab-width: 2; indent-tabs-mode nil -*- +*/ +/** + * @file powerpc64_isa.ac + * @author Jan Vrany + * + * LabWare + * + * @version 1.0 + * @date Mon, 14 Nov 2022 + * + * @brief The ArchC POWERPC64 functional model. + * + * @attention Copyright (C) 2022-2022 --- LabWare + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* Note: This file contains only instruction not present in 32bit PowerPC */ + +AC_ISA(powerpc64) { + + /* + * See Power ISA (Version 3.1.B), Section 1.6.1.5 + */ + ac_format DS1 = "%opcd:6 %frsp:5 %ra:5 %ds:14:s %xo:2"; + ac_format DS2 = "%opcd:6 %frtp:5 %ra:5 %ds:14:s %xo:2"; + ac_format DS3 = "%opcd:6 %rs:5 %ra:5 %ds:14:s %xo:2"; + ac_format DS4 = "%opcd:6 %rsp:5 %ra:5 %ds:14:s %xo:2"; + ac_format DS5 = "%opcd:6 %rt:5 %ra:5 %ds:14:s %xo:2"; + ac_format DS6 = "%opcd:6 %vrs:5 %ra:5 %ds:14:s %xo:2"; + ac_format DS7 = "%opcd:6 %vrt:5 %ra:5 %ds:14:s %xo:2"; + + ac_instr tdi; + + ac_instr td; + + /* + * See Section 3.3.2.1 64-bit Fixed-Point Load Instructions + */ + ac_instr ld, ldu; + ac_instr ldx, ldux; + + /* + * See Section 3.3.3.1 64-bit Fixed-Point Store Instructions + */ + ac_instr std, stdu; + ac_instr stdx, stdux; + + /* + * See Section 3.3.13.1 64-bit Fixed-Point Logical Instructions + */ + ac_instr extsw; + + ISA_CTOR(powerpc64) { + + td.set_asm("td %imm, %reg, %reg", to, ra, rb); + td.set_asm("td%[trapcond] %reg, %reg", to, ra, rb); + td.set_decoder(opcd=31, xog=68); + td.set_cycles(1); + + tdi.set_asm("tdi %imm, %reg, %imm", to, ra, si); + tdi.set_asm("td%[trapcond]i %reg, %imm", to, ra, si); + tdi.set_decoder(opcd=2); + tdi.set_cycles(1); + + /* + * See Section 3.3.2.1 64-bit Fixed-Point Load Instructions + */ + ld.set_decoder(opcd=58, xo=0); + ld.set_asm("ld %reg, %exp(bimm) (%reg)", rt, ds, ra); + + ldu.set_decoder(opcd=58, xo=1); + ldu.set_asm("ldu %reg, %exp(bimm) (%reg)", rt, ds, ra); + + ldx.set_decoder(opcd=31, xog=21); + ldx.set_asm("ldx %reg, %reg, %reg", rt, ra, rb); + + ldux.set_decoder(opcd=31, xog=53); + ldux.set_asm("ldux %reg, %reg, %reg", rt, ra, rb); + + /* + * See Section 3.3.3.1 64-bit Fixed-Point Store Instructions + */ + std.set_decoder(opcd=62, xo=0); + std.set_asm("std %reg, %exp(bimm) (%reg)", rs, ds, ra); + + stdu.set_decoder(opcd=62, xo=1); + stdu.set_asm("stdu %reg, %exp(bimm) (%reg)", rs, ds, ra); + + stdx.set_decoder(opcd=31, xog=149); + stdx.set_asm("stdx %reg, %reg, %reg", rs, ra, rb); + + stdux.set_decoder(opcd=31, xog=181); + stdux.set_asm("stdux %reg, %reg, %reg", rs, ra, rb); + + /* + * See Section 3.3.13.1 64-bit Fixed-Point Logical Instructions + */ + extsw.set_decoder(opcd=31, xog=986); + extsw.set_asm("extsw %reg, %reg", ra, rs, rc=0); + extsw.set_asm("extsw. %reg, %reg", ra, rs, rc=1); + + }; // ISA_CTOR(powerpc64) + +}; // AC_ISA(powerpc64) diff --git a/pdl/powerpc/powerpc_block.ac b/pdl/powerpc/powerpc_block.ac new file mode 100644 index 0000000..666c714 --- /dev/null +++ b/pdl/powerpc/powerpc_block.ac @@ -0,0 +1,77 @@ +/** + * @file powerpc.ac + * @author Bruno Corsi dos Santos + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Thu, 29 Jun 2006 14:49:05 -0300 + * + * @brief The ArchC POWERPC functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +AC_ARCH(powerpc) { + + ac_wordsize 32; + ac_fetchsize 32; + + ac_tlm2_port MEM:512M; + ac_icache IC("2w", 128, 32, "wb", "fifo"); + ac_dcache DC("2w", 512, 32, "wt", "fifo"); + + + ac_reg id; + + ac_tlm2_intr_port intr_port; + + ac_regbank GPR:32; + + ac_reg SPRG4; + ac_reg SPRG5; + ac_reg SPRG6; + ac_reg SPRG7; + ac_reg USPRG0; + + ac_reg XER; + + ac_reg MSR; + +// sc instruction not tested/used + ac_reg EVPR; + ac_reg SRR0; + ac_reg SRR1; + + ac_reg CR; + ac_reg LR; + ac_reg CTR; + + ARCH_CTOR(powerpc) { + ac_isa("powerpc_isa.ac"); + set_endian("big"); + IC.bindTo(MEM); + DC.bindTo(MEM); + }; + +}; diff --git a/pdl/powerpc/powerpc_gdb_funcs.cpp b/pdl/powerpc/powerpc_gdb_funcs.cpp new file mode 100644 index 0000000..5d0c70b --- /dev/null +++ b/pdl/powerpc/powerpc_gdb_funcs.cpp @@ -0,0 +1,124 @@ +/** + * @file powerpc_gdb_funcs.cpp + * @author Bruno Corsi dos Santos + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:50:48 -0300 + * + * @brief The ArchC POWERPC functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + */ + +#include "powerpc.H" + +using namespace powerpc_parms; + +int powerpc::nRegs(void) { + return 104; +} + + +ac_word powerpc::reg_read( int reg ) { + unsigned int n; + + if ( ( reg >= 0 ) && ( reg < 32 ) ) + return GPR.read( reg ); + else { + switch (reg) { + + case 96: + n=ac_pc; + break; + + /* case ??: + n=MSR.read(); + break; */ + + case 98: + n=CR.read(); + break; + + case 99: + n=LR.read(); + break; + + case 100: + n=CTR.read(); + break; + + case 101: + n=XER.read(); + break; + + default: + return 0; + break; + + } + + return(n); + + } +} + + +void powerpc::reg_write( int reg, ac_word value ) { + + /* general purpose registers */ + if ( ( reg >= 0 ) && ( reg < 32 ) ) + GPR.write(reg,value); + else { + switch (reg) { + + case 96: + ac_pc=value; + break; + + /* case ??: + MSR.write(value); + break; + */ + + case 98: + CR.write(value); + break; + + case 99: + LR.write(value); + break; + + case 100: + CTR.write(value); + break; + + case 101: + XER.write(value); + break; + + default: + /* No completely implemented register */ + break; + + } + } +} + + +unsigned char powerpc::mem_read( unsigned int address ) { + return IM->read_byte( address ); +} + + +void powerpc::mem_write( unsigned int address, unsigned char byte ) { + IM->write_byte( address, byte ); +} + diff --git a/pdl/powerpc/powerpc_isa.ac b/pdl/powerpc/powerpc_isa.ac new file mode 100644 index 0000000..37863f7 --- /dev/null +++ b/pdl/powerpc/powerpc_isa.ac @@ -0,0 +1,1359 @@ +/* ex: set tabstop=2 expandtab: + -*- Mode: C; tab-width: 2; indent-tabs-mode nil -*- +*/ +/** + * @file powerpc_isa.ac + * @author Bruno Corsi dos Santos + * Alexandro Baldassin (assembly information) + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Thu, 29 Jun 2006 14:49:06 -0300 + * + * @brief The ArchC POWERPC functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * Copyright (C) 2022-2022 --- LabWare + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* Note: Instructions of 405 processor are not implemented */ + +AC_ISA(powerpc) { + + ac_format I1 = "%opcd:6 %li:24:s %aa:1 %lk:1"; + + ac_format B1 = "%opcd:6 %bo:5 %bi_cf:3 %bi_cb:2 %bd:14:s %aa:1 %lk:1"; + + ac_format SC1 = "%opcd:6 0x00:5 0x00:5 0x00:4 %lev:7 0x00:3 0x01:1 0x00:1"; + + ac_format D1 = "%opcd:6 %rt:5 %ra:5 %d:16:s"; + ac_format D2 = "%opcd:6 %rs:5 %ra:5 %si:16:s"; + ac_format D3 = "%opcd:6 %rs:5 %ra:5 %d:16:s"; + ac_format D4 = "%opcd:6 %rs:5 %ra:5 %ui:16"; + ac_format D5 = "%opcd:6 %bf:3 0x00:1 %l:1 %ra:5 %si:16:s"; + ac_format D6 = "%opcd:6 %bf:3 0x00:1 %l:1 %ra:5 %ui:16"; + ac_format D7 = "%opcd:6 %to:5 %ra:5 %si:16:s"; + + ac_format X1 = "%opcd:6 %rt:5 %ra:5 %rb:5 %xog:10 %rc:1"; + ac_format X2 = "%opcd:6 %rt:5 %ra:5 %rb:5 %xog:10 0x00:1"; + ac_format X3 = "%opcd:6 %rt:5 %ra:5 %nb:5 %xog:10 0x00:1"; + ac_format X4 = "%opcd:6 %rt:5 %ra:5 %ws:5 %xog:10 0x00:1"; + ac_format X5 = "%opcd:6 %rt:5 0x00:5 %rb:5 %xog:10 0x00:1"; + ac_format X6 = "%opcd:6 %rt:5 0x00:5 0x00:5 %xog:10 0x00:1"; + ac_format X7 = "%opcd:6 %rs:5 %ra:5 %rb:5 %xog:10 %rc:1"; + ac_format X8 = "%opcd:6 %rs:5 %ra:5 %rb:5 %xog:10 0x01:1"; + ac_format X9 = "%opcd:6 %rs:5 %ra:5 %rb:5 %xog:10 0x00:1"; + ac_format X10 = "%opcd:6 %rs:5 %ra:5 %nb:5 %xog:10 0x00:1"; + ac_format X11 = "%opcd:6 %rs:5 %ra:5 %ws:5 %xog:10 0x00:1"; + ac_format X12 = "%opcd:6 %rs:5 %ra:5 %sh:5 %xog:10 %rc:1"; + ac_format X13 = "%opcd:6 %rs:5 %ra:5 0x00:5 %xog:10 %rc:1"; + ac_format X14 = "%opcd:6 %rs:5 0x00:5 %rb:5 %xog:10 0x00:1"; + ac_format X15 = "%opcd:6 %rs:5 0x00:5 0x00:5 %xog:10 0x00:1"; + ac_format X16 = "%opcd:6 %bf:3 0x00:1 %l:1 %ra:5 %rb:5 %xog:10 0x00:1"; + ac_format X17 = "%opcd:6 %bf:3 0x00:2 %bfa:3 0x00:2 0x00:5 %xog:10 %rc:1"; + ac_format X18 = "%opcd:6 %bf:3 0x00:2 0x00:5 0x00:5 %xog:10 0x00:1"; + ac_format X19 = "%opcd:6 %bf:3 0x00:2 0x00:5 %u:5 %xog:10 %rc:1"; + ac_format X20 = "%opcd:6 %bf:3 0x00:2 0x00:5 0x00:5 %xog:10 0x00:1"; + ac_format X21 = "%opcd:6 %to:5 %ra:5 %rb:5 %xog:10 0x00:1"; + ac_format X22 = "%opcd:6 %bt:5 0x00:5 0x00:5 %xog:10 %rc:1"; + ac_format X23 = "%opcd:6 0x00:5 %ra:5 %rb:5 %xog:10 0x00:1"; + ac_format X24 = "%opcd:6 0x00:5 0x00:5 0x00:5 %xog:10 0x00:1"; + ac_format X25 = "%opcd:6 0x00:5 0x00:5 %e:1 0x00:4 %xog:10 0x00:1"; + ac_format X26 = "%opcd:6 0x00:4 %l:1 0x00:5 0x00:5 %xog:10 0x00:1"; + + ac_format XL1 = "%opcd:6 %bt:5 %ba:5 %bb:5 %xog:10 0x00:1"; + ac_format XL2 = "%opcd:6 %bo:5 %bi:5 0x00:3 %bh:2 %xog:10 %lk:1"; + ac_format XL3 = "%opcd:6 %bf:3 0x00:2 %bfa:3 0x00:2 0x00:5 %xog:10 0x00:1"; + ac_format XL4 = "%opcd:6 0x00:5 0x00:5 0x00:5 %xog:10 0x00:1"; + + ac_format XFX1 = "%opcd:6 %rt:5 %sprf:10 %xog:10 0x00:1"; + ac_format XFX2 = "%opcd:6 %rt:5 %dcrf:10 %xog:10 0x00:1"; + ac_format XFX3 = "%opcd:6 %rs:5 0x00:1 %xfm:8 0x00:1 %xog:10 0x00:1"; + ac_format XFX4 = "%opcd:6 %rs:5 %sprf:10 %xog:10 0x00:1"; + ac_format XFX5 = "%opcd:6 %rs:5 %dcrf:10 %xog:10 0x00:1"; + + ac_format XO1 = "%opcd:6 %rt:5 %ra:5 %rb:5 %oe:1 %xos:9 %rc:1"; + ac_format XO2 = "%opcd:6 %rt:5 %ra:5 %rb:5 0x00:1 %xos:9 %rc:1"; + ac_format XO3 = "%opcd:6 %rt:5 %ra:5 0x00:5 %oe:1 %xos:9 %rc:1"; + + ac_format M1 = "%opcd:6 %rs:5 %ra:5 %rb:5 %mb:5 %me:5 %rc:1"; + ac_format M2 = "%opcd:6 %rs:5 %ra:5 %sh:5 %mb:5 %me:5 %rc:1"; + + ac_instr b, ba, bl, bla; + + ac_instr bc; + + ac_instr sc; + + ac_instr addi, addic, addic_, addis, lbz, lbzu, lha, lhau, lhz, + lhzu, lmw, lwz, lwzu, mulli, subfic; + + ac_instr stb, stbu, sth, sthu, stmw, stw, stwu; + + ac_instr andi_, andis_, ori, oris, xori, xoris; + + ac_instr cmpi; + + ac_instr cmpli; + + ac_instr mullhw, mullhw_, mullhwu, mullhwu_; + + ac_instr lbzux, lbzx, lhaux, lhax, lhbrx, lhzux, lhzx, lswx, + lwbrx, lwzux, lwzx; + + ac_instr lswi; + + ac_instr mfcr, mfmsr; + + ac_instr ande, ande_, andc, andc_, eqv, eqv_, nand, nand_, + nor, nor_, ore, ore_, orc, orc_, slw, slw_, sraw, + sraw_, srw, srw_, xxor, xxor_; + + ac_instr stbux, stbx, sthbrx, sthux, stswx, stwbrx, stwux, stwx, + sthx; + + ac_instr stswi; + + ac_instr srawi, srawi_; + + ac_instr cntlzw, cntlzw_, extsb, extsb_, extsh, extsh_; + + ac_instr mtmsr; + + ac_instr cmp, cmpl; + + ac_instr mcrxr; + + ac_instr sync; + + ac_instr crand, crandc, creqv, crnand, crnor, cror, crorc, crxor; + + ac_instr bcctr, bcctrl, bclr, bclrl; + + ac_instr mcrf; + + ac_instr isync; + + ac_instr mfspr; + + ac_instr mtcrf; + + ac_instr mtspr; + + ac_instr add, add_, addo, addo_, addc, addc_, addco, addco_, + adde, adde_, addeo, addeo_, mullw, mullw_, mullwo, + mullwo_, divw, divw_, divwo, divwo_, divwu, divwu_, + divwou, divwou_, subf, subf_, subfo, subfo_, subfc, + subfc_, subfco, subfco_, subfe, subfe_, subfeo, + subfeo_; + + ac_instr twi; + + ac_instr tw; + +/* + + macchw, macchw_, macchwo, macchwo_, + macchws, macchws_, macchwso, macchwso_, macchwsu, + macchwsu_, macchwsuo, macchwsuo_, macchwu, + macchwu_, macchwuo, macchwuo_, machhw, machhw_, + machhwo, machhwo_, machhws, machhws_, machhwso, + machhwso_, machhwsu, machhwsu_, machhwsuo, machhwsuo_, + machhwu, machhwu_, machhwuo, machhwuo_, maclhw, + maclhw_, maclhwo, maclhwo_, maclhws, maclhws_, + maclhwso, maclhwso_, maclhwsu, maclhwsu_, maclhwsuo, + maclhwsuo_, maclhwu, maclhwu_, maclhwuo, maclhwuo_, + nmacchw, nmacchw_, nmacchwo, nmacchwo_, + nmacchws, nmacchws_, nmacchwso, nmacchwso_, + nmachhw, nmachhw_, nmachhwo, nmachhwo_, + nmachhws, nmachhws_, nmachhwso, nmachhwso_, + nmaclhw, nmaclhw_, nmaclhwo, nmaclhwo_, + nmaclhws, nmaclhws_, nmaclhwso, nmaclhwso_; +*/ + + + ac_instr mulhw, mulhw_, mulhwu, mulhwu_; + + ac_instr addme, addme_, addmeo, addmeo_, + addze, addze_, addzeo, addzeo_, + neg, neg_, nego, nego_, + subfme, subfme_, subfmeo, subfmeo_, + subfze, subfze_, subfzeo, subfzeo_; + + ac_instr rlwnm, rlwnm_; + + ac_instr rlwimi, rlwimi_, rlwinm, rlwinm_; + + + ac_asm_map reg { + /* default gas assembler uses numbers as register names */ + ""[0..31] = [0..31]; + } + + ac_asm_map trapcond { + "lt" = 16; + "le", "ne" = 20; + "eq" = 4; + "ge", "nl" = 12; + "ne" = 24; + "gt" = 8; + "llt" = 2; + "lle", "lng" = 6; + "lge", "lnl" = 5; + "lgt" = 1; + } + + ac_asm_map aa { + "" = 0; + "a" = 1; + } + + ac_asm_map lk { + "" = 0; + "l" = 1; + } + + ac_asm_map ccr { + "cr"[0..7] = [0..7]; + } + + ISA_CTOR(powerpc) { + + add.set_asm("add %reg, %reg, %reg", rt, ra, rb); + add.set_decoder(opcd=31, oe=0, xos=266, rc=0); + add.set_cycles(1); + + add_.set_asm("add. %reg, %reg, %reg", rt, ra, rb); + add_.set_decoder(opcd=31, oe=0, xos=266, rc=1); + add_.set_cycles(1); + + addo.set_asm("addo %reg, %reg, %reg", rt, ra, rb); + addo.set_decoder(opcd=31, oe=1, xos=266, rc=0); + addo.set_cycles(1); + + addo_.set_asm("addo. %reg, %reg, %reg", rt, ra, rb); + addo_.set_decoder(opcd=31, oe=1, xos=266, rc=1); + addo_.set_cycles(1); + + addc.set_asm("addc %reg, %reg, %reg", rt, ra, rb); + addc.set_decoder(opcd=31, oe=0, xos=10, rc=0); + addc.set_cycles(1); + + addc_.set_asm("addc. %reg, %reg, %reg", rt, ra, rb); + addc_.set_decoder(opcd=31, oe=0, xos=10, rc=1); + addc_.set_cycles(1); + + addco.set_asm("addco %reg, %reg, %reg", rt, ra, rb); + addco.set_decoder(opcd=31, oe=1, xos=10, rc=0); + addco.set_cycles(1); + + addco_.set_asm("addco. %reg, %reg, %reg", rt, ra, rb); + addco_.set_decoder(opcd=31, oe=1, xos=10, rc=1); + addco_.set_cycles(1); + + adde.set_asm("adde %reg, %reg, %reg", rt, ra, rb); + adde.set_decoder(opcd=31, oe=0, xos=138, rc=0); + adde.set_cycles(1); + + adde_.set_asm("adde. %reg, %reg, %reg", rt, ra, rb); + adde_.set_decoder(opcd=31, oe=0, xos=138, rc=1); + adde_.set_cycles(1); + + addeo.set_asm("addeo %reg, %reg, %reg", rt, ra, rb); + addeo.set_decoder(opcd=31, oe=1, xos=138, rc=0); + addeo.set_cycles(1); + + addeo_.set_asm("addeo. %reg, %reg, %reg", rt, ra, rb); + addeo_.set_decoder(opcd=31, oe=1, xos=138, rc=1); + addeo_.set_cycles(1); + + addi.set_asm("li %reg, %exp", rt, ra=0, d); + addi.set_asm("li %reg, %exp(carry)@ha", rt, ra=0, d); + addi.set_asm("la %reg, %exp@l(%imm)", rt, d, ra ); + addi.set_asm("addi %reg, %reg, %exp", rt, ra, d); + addi.set_decoder(opcd=14); + addi.set_cycles(1); + + addic.set_asm("addic %reg, %reg, %exp", rt, ra, d); + addic.set_decoder(opcd=12); + addic.set_cycles(1); + + addic_.set_asm("addic. %reg, %reg, %exp", rt, ra, d); + addic_.set_decoder(opcd=13); + addic_.set_cycles(1); + + addis.set_asm("lis %reg, %exp", rt, ra=0, d); + addis.set_asm("lis %reg, %exp(carry)@ha", rt, ra=0, d); + addis.set_asm("addis %reg, %reg, %exp", rt, ra, d); + addis.set_decoder(opcd=15); + addis.set_cycles(1); + + addme.set_asm("addme %reg, %reg", rt, ra); + addme.set_decoder(opcd=31, oe=0, xos=234, rc=0); + addme.set_cycles(1); + + addme_.set_asm("addme. %reg, %reg", rt, ra); + addme_.set_decoder(opcd=31, oe=0, xos=234, rc=1); + addme_.set_cycles(1); + + addmeo.set_asm("addmeo %reg, %reg", rt, ra); + addmeo.set_decoder(opcd=31, oe=1, xos=234, rc=0); + addmeo.set_cycles(1); + + addmeo_.set_asm("addmeo. %reg, %reg", rt, ra); + addmeo_.set_decoder(opcd=31, oe=1, xos=234, rc=1); + addmeo_.set_cycles(1); + + addze.set_asm("addze %reg, %reg", rt, ra); + addze.set_decoder(opcd=31, oe=0, xos=202, rc=0); + addze.set_cycles(1); + + addze_.set_asm("addze. %reg, %reg", rt, ra); + addze_.set_decoder(opcd=31, oe=0, xos=202, rc=1); + addze_.set_cycles(1); + + addzeo.set_asm("addzeo %reg, %reg", rt, ra); + addzeo.set_decoder(opcd=31, oe=1, xos=202, rc=0); + addzeo.set_cycles(1); + + addzeo_.set_asm("addzeo. %reg, %reg", rt, ra); + addzeo_.set_decoder(opcd=31, oe=1, xos=202, rc=1); + addzeo_.set_cycles(1); + + ande.set_asm("and %reg, %reg, %reg", ra, rs, rb); + ande.set_decoder(opcd=31, xog=28, rc=0); + ande.set_cycles(1); + + ande_.set_asm("and. %reg, %reg, %reg", ra, rs, rb); + ande_.set_decoder(opcd=31, xog=28, rc=1); + ande_.set_cycles(1); + + andc.set_asm("andc %reg, %reg, %reg", ra, rs, rb); + andc.set_decoder(opcd=31, xog=60, rc=0); + andc.set_cycles(1); + + andc_.set_asm("andc. %reg, %reg, %reg", ra, rs, rb); + andc_.set_decoder(opcd=31, xog=60, rc=1); + andc_.set_cycles(1); + + andi_.set_asm("andi. %reg, %reg, %imm", ra, rs, ui); + andi_.set_decoder(opcd=28); + andi_.set_cycles(1); + + andis_.set_asm("andis. %reg, %reg, %imm", ra, rs, ui); + andis_.set_decoder(opcd=29); + andis_.set_cycles(1); + +/* Unconditional, I-form */ + b.set_asm("b %addr(pcrel)", li); + b.set_decoder(opcd=18, aa=0, lk=0); + b.set_cycles(1); + + ba.set_asm("ba %exp", li); + ba.set_decoder(opcd=18, aa=1, lk=0); + ba.set_cycles(1); + + bl.set_asm("bl %addr(pcrel)", li); + bl.set_decoder(opcd=18, aa=0, lk=1); + bl.set_cycles(1); + + bla.set_asm("bla %exp", li); + bla.set_decoder(opcd=18, aa=1, lk=1); + bla.set_cycles(1); + + bc.set_asm("bc%[lk]%[aa] %imm, %exp, %addr(pcrel)", lk, aa, bo, bi_cb+bi_cf, bd); + bc.set_decoder(opcd=16); + bc.set_cycles(1); + + bcctr.set_asm("bctr", bo=0x14, bi=0, bh=0); + bcctr.set_asm("bcctr %reg, %reg, %reg", bo, bi, bh); + bcctr.set_decoder(opcd=19, xog=528, lk=0); + bcctr.set_cycles(1); + + bcctrl.set_asm("bctrl", bo=0x14, bi=0, bh=0); + bcctrl.set_asm("bcctrl %reg, %reg, %reg", bo, bi, bh); + bcctrl.set_decoder(opcd=19, xog=528, lk=1); + bcctrl.set_cycles(1); + + bclr.set_asm("blr", bo=0x14, bi=0, bh=0); + bclr.set_asm("bclr %reg, %reg, %reg", bo, bi, bh); + bclr.set_decoder(opcd=19, xog=16, lk=0); + bclr.set_cycles(1); + + bclrl.set_asm("bclrl %reg, %reg, %reg", bo, bi, bh); + bclrl.set_decoder(opcd=19, xog=16, lk=1); + bclrl.set_cycles(1); + + cmp.set_asm("cmpw %imm, %imm, %imm", bf, ra, rb, l=0); + cmp.set_asm("cmp %imm, %imm, %reg, %reg", bf, l, ra, rb); + cmp.set_decoder(opcd=31, xog=0); + cmp.set_cycles(1); + + cmpi.set_asm("cmpwi %imm, %reg, %imm", bf, ra, si, l=0); + cmpi.set_asm("cmpi %reg, %imm, %reg, %imm", bf, l, ra, si); + cmpi.set_decoder(opcd=11, l=0); + cmpi.set_cycles(1); + + cmpl.set_asm("cmplw %reg, %reg, %reg", bf, ra, rb, l=0); + cmpl.set_asm("cmpl %imm, %imm, %reg, %reg", bf, l, ra, rb); + cmpl.set_decoder(opcd=31, l=0, xog=32); + cmpl.set_cycles(1); + + cmpli.set_asm("cmplwi %reg, %reg, %imm", bf, ra, ui, l=0); + cmpli.set_asm("cmpli %reg, %imm, %reg, %imm", bf, l, ra, ui); + cmpli.set_decoder(opcd=10, l=0); + cmpli.set_cycles(1); + cntlzw.set_asm("cntlzw %reg, %reg", ra, rs); + + cntlzw.set_decoder(opcd=31, xog=26, rc=0); + cntlzw.set_cycles(1); + cntlzw_.set_asm("cntlzw. %reg, %reg", ra, rs); + cntlzw_.set_decoder(opcd=31, xog=26, rc=1); + cntlzw_.set_cycles(1); + + crand.set_asm("crand %reg, %reg, %reg", bt, ba, bb); + crand.set_decoder(opcd=19, xog=257); + crand.set_cycles(1); + + crandc.set_asm("crandc %reg, %reg, %reg", bt, ba, bb); + crandc.set_decoder(opcd=19, xog=129); + crandc.set_cycles(1); + + creqv.set_asm("creqv %reg, %reg, %reg", bt, ba, bb); + creqv.set_decoder(opcd=19, xog=289); + creqv.set_cycles(1); + + crnand.set_asm("crnand %reg, %reg, %reg", bt, ba, bb); + crnand.set_decoder(opcd=19, xog=225); + crnand.set_cycles(1); + + crnor.set_asm("crnor %reg, %reg, %reg", bt, ba, bb); + crnor.set_decoder(opcd=19, xog=33); + crnor.set_cycles(1); + + cror.set_asm("cror %reg, %reg, %reg", bt, ba, bb); + cror.set_decoder(opcd=19, xog=449); + cror.set_cycles(1); + + crorc.set_asm("crorc %reg, %reg, %reg", bt, ba, bb); + crorc.set_decoder(opcd=19, xog=417); + crorc.set_cycles(1); + + crxor.set_asm("crxor %reg, %reg, %reg", bt, ba, bb); + crxor.set_decoder(opcd=19, xog=193); + crxor.set_cycles(1); + + divw.set_asm("divw %reg, %reg, %reg", rt, ra, rb); + divw.set_decoder(opcd=31, xos=491, oe=0, rc=0); + divw.set_cycles(1); + + divw_.set_asm("divw. %reg, %reg, %reg", rt, ra, rb); + divw_.set_decoder(opcd=31, xos=491, oe=0, rc=1); + divw_.set_cycles(1); + + divwo.set_asm("divwo %reg, %reg, %reg", rt, ra, rb); + divwo.set_decoder(opcd=31, xos=491, oe=1, rc=0); + divwo.set_cycles(1); + + divwo_.set_asm("divwo. %reg, %reg, %reg", rt, ra, rb); + divwo_.set_decoder(opcd=31, xos=491, oe=1, rc=1); + divwo_.set_cycles(1); + + divwu.set_asm("divwu %reg, %reg, %reg", rt, ra, rb); + divwu.set_decoder(opcd=31, xos=459, oe=0, rc=0); + divwu.set_cycles(1); + + divwu_.set_asm("divwu. %reg, %reg, %reg", rt, ra, rb); + divwu_.set_decoder(opcd=31, xos=459, oe=0, rc=1); + divwu_.set_cycles(1); + + divwou.set_asm("divwou %reg, %reg, %reg", rt, ra, rb); + divwou.set_decoder(opcd=31, xos=459, oe=1, rc=0); + divwou.set_cycles(1); + + divwou_.set_asm("divwou. %reg, %reg, %reg", rt, ra, rb); + divwou_.set_decoder(opcd=31, xos=459, oe=1, rc=1); + divwou_.set_cycles(1); + + eqv.set_asm("eqv %reg, %reg, %reg", ra, rs, rb); + eqv.set_decoder(opcd=31, xog=284, rc=0); + eqv.set_cycles(1); + + eqv_.set_asm("eqv. %reg, %reg, %reg", ra, rs, rb); + eqv_.set_decoder(opcd=31, xog=284, rc=1); + eqv_.set_cycles(1); + + extsb.set_asm("extsb %reg, %reg", ra, rs); + extsb.set_decoder(opcd=31, xog=954, rc=0); + extsb.set_cycles(1); + + extsb_.set_asm("extsb. %reg, %reg", ra, rs); + extsb_.set_decoder(opcd=31, xog=954, rc=1); + extsb_.set_cycles(1); + + extsh.set_asm("extsh %reg, %reg", ra, rs); + extsh.set_decoder(opcd=31, xog=922, rc=0); + extsh.set_cycles(1); + + extsh_.set_asm("extsh. %reg, %reg", ra, rs); + extsh_.set_decoder(opcd=31, xog=922, rc=1); + extsh_.set_cycles(1); + + lbz.set_asm("lbz %reg, %imm (%reg)", rt, d, ra); + lbz.set_asm("lbz %reg, %exp@l(%reg)", rt, d, ra); + lbz.set_decoder(opcd=34); + lbz.set_cycles(1); + + lbzu.set_asm("lbzu %reg, %imm (%reg)", rt, d, ra); + lbzu.set_asm("lbzu %reg, %exp@l(%reg)", rt, d, ra); + lbzu.set_decoder(opcd=35); + lbzu.set_cycles(1); + + lbzux.set_asm("lbzux %reg, %reg, %reg", rt, ra, rb); + lbzux.set_decoder(opcd=31, xog=119); + lbzux.set_cycles(1); + + lbzx.set_asm("lbzx %reg, %reg, %reg", rt, ra, rb); + lbzx.set_decoder(opcd=31, xog=87); + lbzx.set_cycles(1); + + lha.set_asm("lha %reg, %imm (%reg)", rt, d, ra); + lha.set_asm("lha %reg, %exp@l(%reg)", rt, d, ra); + lha.set_decoder(opcd=42); + lha.set_cycles(1); + + lhau.set_asm("lhau %reg, %imm (%reg)", rt, d, ra); + lhau.set_asm("lhau %reg, %exp@l(%reg)", rt, d, ra); + lhau.set_decoder(opcd=43); + lhau.set_cycles(1); + + lhaux.set_asm("lhaux %reg, %reg, %reg", rt, ra, rb); + lhaux.set_decoder(opcd=31, xog=375); + lhaux.set_cycles(1); + + lhax.set_asm("lhax %reg, %reg, %reg", rt, ra, rb); + lhax.set_decoder(opcd=31, xog=343); + lhax.set_cycles(1); + + lhbrx.set_asm("lhbrx %reg, %reg, %reg", rt, ra, rb); + lhbrx.set_decoder(opcd=31, xog=790); + lhbrx.set_cycles(1); + + lhz.set_asm("lhz %reg, %imm (%reg)", rt, d, ra); + lhz.set_asm("lhz %reg, %exp@l(%reg)", rt, d, ra); + lhz.set_decoder(opcd=40); + lhz.set_cycles(1); + + lhzu.set_asm("lhzu %reg, %imm (%reg)", rt, d, ra); + lhzu.set_asm("lhzu %reg, %exp@l(%reg)", rt, d, ra); + lhzu.set_decoder(opcd=41); + lhzu.set_cycles(1); + + lhzux.set_asm("lhzux %reg, %reg, %reg", rt, ra, rb); + lhzux.set_decoder(opcd=31, xog=311); + lhzux.set_cycles(1); + + lhzx.set_asm("lhzx %reg, %reg, %reg", rt, ra, rb); + lhzx.set_decoder(opcd=31, xog=279); + lhzx.set_cycles(1); + + lmw.set_asm("lmw %reg, %imm (%reg)", rt, d, ra); + lmw.set_asm("lmw %reg, %exp@l(%reg)", rt, d, ra); + lmw.set_decoder(opcd=46); + lmw.set_cycles(1); + + lswi.set_asm("lswi %imm, %imm, %imm", rt, ra, nb); + lswi.set_decoder(opcd=31, xog=597); + lswi.set_cycles(1); + + lswx.set_asm("lswx %reg, %reg, %reg", rt, ra, rb); + lswx.set_decoder(opcd=31, xog=533); + lswx.set_cycles(1); + + lwbrx.set_asm("lwbrx %reg, %reg, %reg", rt, ra, rb); + lwbrx.set_decoder(opcd=31, xog=534); + lwbrx.set_cycles(1); + + lwz.set_asm("lwz %reg, %exp (%reg)", rt, d, ra); + //lwz.set_asm("lba.set_cycles(1); wz %imm, %exp@l(%imm)", rt, d, ra); + lwz.set_decoder(opcd=32); + lwz.set_cycles(1); + + lwzu.set_asm("lwzu %reg, %imm (%reg)", rt, d, ra); + lwzu.set_asm("lwzu %reg, %exp@l(%reg)", rt, d, ra); + lwzu.set_decoder(opcd=33); + lwzu.set_cycles(1); + + lwzux.set_asm("lwzux %reg, %reg, %reg", rt, ra, rb); + lwzux.set_decoder(opcd=31, xog=55); + lwzux.set_cycles(1); + + lwzx.set_asm("lwzx %reg, %reg, %reg", rt, ra, rb); + lwzx.set_decoder(opcd=31, xog=23); + lwzx.set_cycles(1); + + /* BEGIN NOT IMPLEMENTED! 405 Family! */ +// macchw.set_asm("macchw %rt, %ra, %rb"); +// macchw.set_decoder(opcd=4, xos=172, oe=0, rc=0); + +// macchw_.set_asm("macchw_ %rt, %ra, %rb"); +// macchw_.set_decoder(opcd=4, xos=172, oe=0, rc=1); + +// macchwo.set_asm("macchwo %rt, %ra, %rb"); +// macchwo.set_decoder(opcd=4, xos=172, oe=1, rc=0); + +// macchwo_.set_asm("macchwo_ %rt, %ra, %rb"); +// macchwo_.set_decoder(opcd=4, xos=172, oe=1, rc=1); + +// macchws.set_asm("macchws %rt, %ra, %rb"); +// macchws.set_decoder(opcd=4, xos=236, oe=0, rc=0); + +// macchws_.set_asm("macchws_ %rt, %ra, %rb"); +// macchws_.set_decoder(opcd=4, xos=236, oe=0, rc=1); + +// macchwso.set_asm("macchwso %rt, %ra, %rb"); +// macchwso.set_decoder(opcd=4, xos=236, oe=1, rc=0); + +// macchwso_.set_asm("macchwso_ %rt, %ra, %rb"); +// macchwso_.set_decoder(opcd=4, xos=236, oe=1, rc=1); + +// macchwsu.set_asm("macchwsu %rt, %ra, %rb"); +// macchwsu.set_decoder(opcd=4, xos=204, oe=0, rc=0); + +// macchwsu_.set_asm("macchwsu_ %rt, %ra, %rb"); +// macchwsu_.set_decoder(opcd=4, xos=204, oe=0, rc=1); + +// macchwsuo.set_asm("macchwsuo %rt, %ra, %rb"); +// macchwsuo.set_decoder(opcd=4, xos=204, oe=1, rc=0); + +// macchwsuo_.set_asm("macchwsuo_ %rt, %ra, %rb"); +// macchwsuo_.set_decoder(opcd=4, xos=204, oe=1, rc=1); + +// macchwu.set_asm("macchwu %rt, %ra, %rb"); +// macchwu.set_decoder(opcd=4, xos=140, oe=0, rc=0); + +// macchwu_.set_asm("macchwu_ %rt, %ra, %rb"); +// macchwu_.set_decoder(opcd=4, xos=140, oe=0, rc=1); + +// macchwuo.set_asm("macchwuo %rt, %ra, %rb"); +// macchwuo.set_decoder(opcd=4, xos=140, oe=1, rc=0); + +// macchwuo_.set_asm("macchwuo_ %rt, %ra, %rb"); +// macchwuo_.set_decoder(opcd=4, xos=140, oe=1, rc=1); + +// machhw.set_asm("machhw %rt, %ra, %rb"); +// machhw.set_decoder(opcd=4, xos=44, oe=0, rc=0); + +// machhw_.set_asm("machhw_ %rt, %ra, %rb"); +// machhw_.set_decoder(opcd=4, xos=44, oe=0, rc=1); + +// machhwo.set_asm("machhwo %rt, %ra, %rb"); +// machhwo.set_decoder(opcd=4, xos=44, oe=1, rc=0); + +// machhwo_.set_asm("machhwo_ %rt, %ra, %rb"); +// machhwo_.set_decoder(opcd=4, xos=44, oe=1, rc=1); + +// machhws.set_asm("machhws %rt, %ra, %rb"); +// machhws.set_decoder(opcd=4, xos=108, oe=0, rc=0); + +// machhws_.set_asm("machhws_ %rt, %ra, %rb"); +// machhws_.set_decoder(opcd=4, xos=108, oe=0, rc=1); + +// machhwso.set_asm("machhwso %rt, %ra, %rb"); +// machhwso.set_decoder(opcd=4, xos=108, oe=1, rc=0); + +// machhwso_.set_asm("machhwso_ %rt, %ra, %rb"); +// machhwso_.set_decoder(opcd=4, xos=108, oe=1, rc=1); + +// machhwsu.set_asm("machhwsu %rt, %ra, %rb"); +// machhwsu.set_decoder(opcd=4, xos=76, oe=0, rc=0); + +// machhwsu_.set_asm("machhwsu_ %rt, %ra, %rb"); +// machhwsu_.set_decoder(opcd=4, xos=76, oe=0, rc=1); + +// machhwsuo.set_asm("machhwsuo %rt, %ra, %rb"); +// machhwsuo.set_decoder(opcd=4, xos=76, oe=1, rc=0); + +// machhwsuo_.set_asm("machhwsuo_ %rt, %ra, %rb"); +// machhwsuo_.set_decoder(opcd=4, xos=76, oe=1, rc=1); + +// machhwu.set_asm("machhwu %rt, %ra, %rb"); +// machhwu.set_decoder(opcd=4, xos=12, oe=0, rc=0); + +// machhwu_.set_asm("machhwu_ %rt, %ra, %rb"); +// machhwu_.set_decoder(opcd=4, xos=12, oe=0, rc=1); + +// machhwuo.set_asm("machhwuo %rt, %ra, %rb"); +// machhwuo.set_decoder(opcd=4, xos=12, oe=1, rc=0); + +// machhwuo_.set_asm("machhwuo_ %rt, %ra, %rb"); +// machhwuo_.set_decoder(opcd=4, xos=12, oe=1, rc=1); + +// maclhw.set_asm("maclhw %rt, %ra, %rb"); +// maclhw.set_decoder(opcd=4, xos=428, oe=0, rc=0); + +// maclhw_.set_asm("maclhw_ %rt, %ra, %rb"); +// maclhw_.set_decoder(opcd=4, xos=428, oe=0, rc=1); + +// maclhwo.set_asm("maclhwo %rt, %ra, %rb"); +// maclhwo.set_decoder(opcd=4, xos=428, oe=1, rc=0); + +// maclhwo_.set_asm("maclhwo_ %rt, %ra, %rb"); +// maclhwo_.set_decoder(opcd=4, xos=428, oe=1, rc=1); + +// maclhws.set_asm("maclhws %rt, %ra, %rb"); +// maclhws.set_decoder(opcd=4, xos=492, oe=0, rc=0); + +// maclhws_.set_asm("maclhws_ %rt, %ra, %rb"); +// maclhws_.set_decoder(opcd=4, xos=492, oe=0, rc=1); + +// maclhwso.set_asm("maclhwso %rt, %ra, %rb"); +// maclhwso.set_decoder(opcd=4, xos=492, oe=1, rc=0); + +// maclhwso_.set_asm("maclhwso_ %rt, %ra, %rb"); +// maclhwso_.set_decoder(opcd=4, xos=492, oe=1, rc=1); + +// maclhwsu.set_asm("maclhwsu %rt, %ra, %rb"); +// maclhwsu.set_decoder(opcd=4, xos=460, oe=0, rc=0); + +// maclhwsu_.set_asm("maclhwsu_ %rt, %ra, %rb"); +// maclhwsu_.set_decoder(opcd=4, xos=460, oe=0, rc=1); + +// maclhwsuo.set_asm("maclhwsuo %rt, %ra, %rb"); +// maclhwsuo.set_decoder(opcd=4, xos=460, oe=1, rc=0); + +// maclhwsuo_.set_asm("maclhwsuo_ %rt, %ra, %rb"); +// maclhwsuo_.set_decoder(opcd=4, xos=460, oe=1, rc=1); + +// maclhwu.set_asm("maclhwu %rt, %ra, %rb"); +// maclhwu.set_decoder(opcd=4, xos=396, oe=0, rc=0); + +// maclhwu_.set_asm("maclhwu_ %rt, %ra, %rb"); +// maclhwu_.set_decoder(opcd=4, xos=396, oe=0, rc=1); + +// maclhwuo.set_asm("maclhwuo %rt, %ra, %rb"); +// maclhwuo.set_decoder(opcd=4, xos=396, oe=1, rc=0); + +// maclhwuo_.set_asm("maclhwuo_ %rt, %ra, %rb"); +// maclhwuo_.set_decoder(opcd=4, xos=396, oe=1, rc=1); + /* END NOT IMPLEMENTED! 405 Family! */ + + + mcrf.set_asm("mcrf %imm, %imm", bf, bfa); + mcrf.set_decoder(opcd=19, xog=0); + mcrf.set_cycles(1); + + mcrxr.set_asm("mcrxr %imm", bf); + mcrxr.set_decoder(opcd=31, xog=512); + mcrxr.set_cycles(1); + + mfcr.set_asm("mfcr %imm", rt); + mfcr.set_decoder(opcd=31, xog=19); + mfcr.set_cycles(1); + + mfmsr.set_asm("mfmsr %reg", rt); + mfmsr.set_decoder(opcd=31, xog=83); + mfmsr.set_cycles(1); + + /* INCOMPLETE IMPLEMENTATION! */ + mfspr.set_asm("mfctr %imm", rt, sprf=0x120); + mfspr.set_asm("mflr %imm", rt, sprf=0x100); + mfspr.set_asm("mfspr %imm, %imm", rt, sprf); + mfspr.set_decoder(opcd=31, xog=339); + mfspr.set_cycles(1); + + mtcrf.set_asm("mtcrf %imm, %imm", xfm, rs); + mtcrf.set_decoder(opcd=31, xog=144); + mtcrf.set_cycles(1); + + mtmsr.set_asm("mtmsr %reg", rs); + mtmsr.set_decoder(opcd=31, xog=146); + mtmsr.set_cycles(1); + + /* INCOMPLETE IMPLEMENTATION! */ + mtspr.set_asm("mtctr %imm", rs, sprf=0x120); + mtspr.set_asm("mtlr %imm", rs, sprf=0x100); + mtspr.set_asm("mtxer %imm", rs, sprf=0x20); + mtspr.set_asm("mtspr %imm, %imm", sprf, rs); + mtspr.set_decoder(opcd=31, xog=467); + + mulhw.set_asm("mulhw %reg, %reg, %reg", rt, ra, rb); + mulhw.set_decoder(opcd=31, xos=75, rc=0); + + mulhw_.set_asm("mulhw. %reg, %reg, %reg", rt, ra, rb); + mulhw_.set_decoder(opcd=31, xos=75, rc=1); + + mulhwu.set_asm("mulhwu %reg, %reg, %reg", rt, ra, rb); + mulhwu.set_decoder(opcd=31, xos=11, rc=0); + + mulhwu_.set_asm("mulhwu. %reg, %reg, %reg", rt, ra, rb); + mulhwu_.set_decoder(opcd=31, xos=11, rc=1); + + mullhw.set_asm("mullhw %reg, %reg, %reg", rt, ra, rb); + mullhw.set_decoder(opcd=4, xog=424, rc=0); + + mullhw_.set_asm("mullhw. %reg, %reg, %reg", rt, ra, rb); + mullhw_.set_decoder(opcd=4, xog=424, rc=1); + + mullhwu.set_asm("mullhwu %reg, %reg, %reg", rt, ra, rb); + mullhwu.set_decoder(opcd=4, xog=392, rc=0); + + mullhwu_.set_asm("mullhwu. %reg, %reg, %reg", rt, ra, rb); + mullhwu_.set_decoder(opcd=4, xog=392, rc=1); + + mulli.set_asm("mulli %reg, %reg, %exp", rt, ra, d); + mulli.set_decoder(opcd=7); + + mullw.set_asm("mullw %reg, %reg, %reg", rt, ra, rb); + mullw.set_decoder(opcd=31,oe=0,xos=235,rc=0); + + mullw_.set_asm("mullw. %reg, %reg, %reg", rt, ra, rb); + mullw_.set_decoder(opcd=31,oe=0,xos=235,rc=1); + + mullwo.set_asm("mullwo %reg, %reg, %reg", rt, ra, rb); + mullwo.set_decoder(opcd=31,oe=1,xos=235,rc=0); + + mullwo_.set_asm("mullw %reg, %reg, %reg", rt, ra, rb); + mullwo_.set_decoder(opcd=31,oe=1,xos=235,rc=1); + + nand.set_asm("nand %reg, %reg, %reg", ra, rs, rb); + nand.set_decoder(opcd=31, xog=476, rc=0); + + nand_.set_asm("nand. %reg, %reg, %reg", ra, rs, rb); + nand_.set_decoder(opcd=31, xog=476, rc=1); + + neg.set_asm("neg %reg, %reg", rt, ra); + neg.set_decoder(opcd=31, xos=104, oe=0, rc=0); + + neg_.set_asm("neg. %reg, %reg", rt, ra); + neg_.set_decoder(opcd=31, xos=104, oe=0, rc=1); + + nego.set_asm("nego %reg, %reg", rt, ra); + nego.set_decoder(opcd=31, xos=104, oe=1, rc=0); + + nego_.set_asm("nego. %reg, %reg", rt, ra); + nego_.set_decoder(opcd=31, xos=104, oe=1, rc=1); + + + /* BEGIN NOT IMPLEMENTED! 405 Family! */ +// nmacchw.set_asm("nmacchw %rt, %ra, %rb"); +// nmacchw.set_decoder(opcd=4, xos=174, oe=0, rc=0); + +// nmacchw_.set_asm("nmacchw_ %rt, %ra, %rb"); +// nmacchw_.set_decoder(opcd=4, xos=174, oe=0, rc=1); + +// nmacchwo.set_asm("nmacchwo %rt, %ra, %rb"); +// nmacchwo.set_decoder(opcd=4, xos=174, oe=1, rc=0); + +// nmacchwo_.set_asm("nmacchwo_ %rt, %ra, %rb"); +// nmacchwo_.set_decoder(opcd=4, xos=174, oe=1, rc=1); + +// nmacchws.set_asm("nmacchws %rt, %ra, %rb"); +// nmacchws.set_decoder(opcd=4, xos=238, oe=0, rc=0); + +// nmacchws_.set_asm("nmacchws_ %rt, %ra, %rb"); +// nmacchws_.set_decoder(opcd=4, xos=238, oe=0, rc=1); + +// nmacchwso.set_asm("nmacchwso %rt, %ra, %rb"); +// nmacchwso.set_decoder(opcd=4, xos=238, oe=1, rc=0); + +// nmacchwso_.set_asm("nmacchwso_ %rt, %ra, %rb"); +// nmacchwso_.set_decoder(opcd=4, xos=238, oe=1, rc=1); + +// nmachhw.set_asm("nmachhw %rt, %ra, %rb"); +// nmachhw.set_decoder(opcd=4, xos=46, oe=0, rc=0); + +// nmachhw_.set_asm("nmachhw_ %rt, %ra, %rb"); +// nmachhw_.set_decoder(opcd=4, xos=46, oe=0, rc=1); + +// nmachhwo.set_asm("nmachhwo %rt, %ra, %rb"); +// nmachhwo.set_decoder(opcd=4, xos=46, oe=1, rc=0); + +// nmachhwo_.set_asm("nmachhwo_ %rt, %ra, %rb"); +// nmachhwo_.set_decoder(opcd=4, xos=46, oe=1, rc=1); + +// nmachhws.set_asm("nmachhws %rt, %ra, %rb"); +// nmachhws.set_decoder(opcd=4, xos=110, oe=0, rc=0); + +// nmachhws_.set_asm("nmachhws_ %rt, %ra, %rb"); +// nmachhws_.set_decoder(opcd=4, xos=110, oe=0, rc=1); + +// nmachhwso.set_asm("nmachhwso %rt, %ra, %rb"); +// nmachhwso.set_decoder(opcd=4, xos=110, oe=1, rc=0); + +// nmachhwso_.set_asm("nmachhwso_ %rt, %ra, %rb"); +// nmachhwso_.set_decoder(opcd=4, xos=110, oe=1, rc=1); + +// nmaclhw.set_asm("nmaclhw %rt, %ra, %rb"); +// nmaclhw.set_decoder(opcd=4, xos=430, oe=0, rc=0); + +// nmaclhw_.set_asm("nmaclhw_ %rt, %ra, %rb"); +// nmaclhw_.set_decoder(opcd=4, xos=430, oe=0, rc=1); + +// nmaclhwo.set_asm("nmaclhwo %rt, %ra, %rb"); +// nmaclhwo.set_decoder(opcd=4, xos=430, oe=1, rc=0); + +// nmaclhwo_.set_asm("nmaclhwo_ %rt, %ra, %rb"); +// nmaclhwo_.set_decoder(opcd=4, xos=430, oe=1, rc=1); + +// nmaclhws.set_asm("nmaclhws %rt, %ra, %rb"); +// nmaclhws.set_decoder(opcd=4, xos=494, oe=0, rc=0); + +// nmaclhws_.set_asm("nmaclhws_ %rt, %ra, %rb"); +// nmaclhws_.set_decoder(opcd=4, xos=494, oe=0, rc=1); + +// nmaclhwso.set_asm("nmaclhwso %rt, %ra, %rb"); +// nmaclhwso.set_decoder(opcd=4, xos=494, oe=1, rc=0); + +// nmaclhwso_.set_asm("nmaclhwso_ %rt, %ra, %rb"); +// nmaclhwso_.set_decoder(opcd=4, xos=494, oe=1, rc=1); + /* END NOT IMPLEMENTED! 405 Family! */ + + nor.set_asm("nor %reg, %reg, %reg", ra, rs, rb); + nor.set_decoder(opcd=31, xog=124, rc=0); + nor.set_cycles(1); + + nor_.set_asm("nor. %reg, %reg, %reg", ra, rs, rb); + nor_.set_decoder(opcd=31, xog=124, rc=1); + nor_.set_cycles(1); + + ore.set_asm("or %reg, %reg, %reg", ra, rs, rb); + ore.set_asm("nop", ra=0, rs=0, rb=0); + ore.set_decoder(opcd=31, xog=444, rc=0); + ore.set_cycles(1); + + ore_.set_asm("or. %reg, %reg, %reg", ra, rs, rb); + ore_.set_decoder(opcd=31, xog=444, rc=1); + ore_.set_cycles(1); + + orc.set_asm("orc %reg, %reg, %reg", ra, rs, rb); + orc.set_decoder(opcd=31, xog=412, rc=0); + orc.set_cycles(1); + + orc_.set_asm("orc. %reg, %reg, %reg", ra, rs, rb); + orc_.set_decoder(opcd=31, xog=412, rc=1); + orc_.set_cycles(1); + + ori.set_asm("ori %reg, %reg, %imm", ra, rs, ui); + ori.set_decoder(opcd=24); + ori.set_cycles(1); + + oris.set_asm("oris %reg, %reg, %imm", ra, rs, ui); + oris.set_decoder(opcd=25); + oris.set_cycles(1); + + rlwimi.set_asm("rlwimi %reg, %reg, %exp, %imm, %exp", ra, rs, sh, mb, me); + rlwimi.set_decoder(opcd=20, rc=0); + rlwimi.set_cycles(1); + + rlwimi_.set_asm("rlwimi. %reg, %reg, %exp, %imm, %exp", ra, rs, sh, mb, me); + rlwimi_.set_decoder(opcd=20,rc=1); + rlwimi_.set_cycles(1); + + rlwinm.set_asm("rlwinm %reg, %reg, %exp, %imm, %exp", ra, rs, sh, mb, me); + rlwinm.set_decoder(opcd=21, rc=0); + rlwinm.set_cycles(1); + + rlwinm_.set_asm("rlwinm. %reg, %reg, %exp, %imm, %exp", ra, rs, sh, mb, me); + rlwinm_.set_decoder(opcd=21,rc=1); + rlwinm_.set_cycles(1); + + rlwnm.set_asm("rlwnm %imm, %imm, %imm, %imm, %imm", ra, rs, rb, mb, me); + rlwnm.set_decoder(opcd=23, rc=0); + rlwnm.set_cycles(1); + + rlwnm_.set_asm("rlwnm. %imm, %imm, %imm, %imm, %imm", ra, rs, rb, mb, me); + rlwnm_.set_decoder(opcd=23,rc=1); + rlwnm_.set_cycles(1); + + sc.set_asm("sc %imm", lev); + sc.set_asm("sc", lev=0); + sc.set_decoder(opcd=17); + sc.set_cycles(1); + + slw.set_asm("slw %reg, %reg, %reg", ra, rs, rb); + slw.set_decoder(opcd=31, xog=24, rc=0); + slw.set_cycles(1); + + slw_.set_asm("slw. %reg, %reg, %reg", ra, rs, rb); + slw_.set_decoder(opcd=31, xog=24, rc=1); + slw_.set_cycles(1); + + sraw.set_asm("sraw %reg, %reg, %reg", ra, rs, rb); + sraw.set_decoder(opcd=31, xog=792, rc=0); + sraw.set_cycles(1); + + sraw_.set_asm("sraw. %reg, %reg, %reg", ra, rs, rb); + sraw_.set_decoder(opcd=31, xog=792, rc=1); + sraw_.set_cycles(1); + + srawi.set_asm("srawi %reg, %reg, %reg", ra, rs, sh); + srawi.set_decoder(opcd=31, xog=824, rc=0); + srawi.set_cycles(1); + + srawi_.set_asm("srawi. %reg, %reg, %reg", ra, rs, sh); + srawi_.set_decoder(opcd=31, xog=824, rc=1); + srawi_.set_cycles(1); + + srw.set_asm("srw %reg, %reg, %reg", ra, rs, rb); + srw.set_decoder(opcd=31, xog=536, rc=0); + srw.set_cycles(1); + + srw_.set_asm("srw. %reg, %reg, %reg", ra, rs, rb); + srw_.set_decoder(opcd=31, xog=536, rc=1); + srw_.set_cycles(1); + + stb.set_asm("stb %reg, %imm (%reg)", rs, d, ra); + stb.set_asm("stb %reg, %exp@l(%reg)", rs, d, ra); + stb.set_decoder(opcd=38); + stb.set_cycles(1); + + stbu.set_asm("stbu %reg, %imm (%reg)", rs, d, ra); + stbu.set_asm("stbu %reg, %exp@l(%reg)", rs, d, ra); + stbu.set_decoder(opcd=39); + stbu.set_cycles(1); + + stbux.set_asm("stbux %reg, %reg, %reg", rs, ra, rb); + stbux.set_decoder(opcd=31, xog=247); + stbux.set_cycles(1); + + stbx.set_asm("stbx %reg, %reg, %reg", rs, ra, rb); + stbx.set_decoder(opcd=31, xog=215); + stbx.set_cycles(1); + + sth.set_asm("sth %reg, %imm (%reg)", rs, d, ra); + sth.set_asm("sth %reg, %exp@l(%reg)", rs, d, ra); + sth.set_decoder(opcd=44); + sth.set_cycles(1); + + sthbrx.set_asm("sthbrx %reg, %reg, %reg", rs, ra, rb); + sthbrx.set_decoder(opcd=31, xog=918); + sthbrx.set_cycles(1); + + sthu.set_asm("sthu %reg, %imm (%reg)", rs, d, ra); + sthu.set_asm("sthu %reg, %exp@l(%reg)", rs, d, ra); + sthu.set_decoder(opcd=45); + sthu.set_cycles(1); + + sthux.set_asm("sthux %reg, %reg, %reg", rs, ra, rb); + sthux.set_decoder(opcd=31, xog=439); + sthux.set_cycles(1); + + sthx.set_asm("sthx %reg, %reg, %reg", rs, ra, rb); + sthx.set_decoder(opcd=31, xog=407); + sthx.set_cycles(1); + + stmw.set_asm("stmw %reg, %imm (%reg)", rs, d, ra); + stmw.set_asm("stmw %reg, %exp@l(%reg)", rs, d, ra); + stmw.set_decoder(opcd=47); + stmw.set_cycles(1); + + stswi.set_asm("stswi %reg, %reg, %reg", rs, ra, nb); + stswi.set_decoder(opcd=31, xog=725); + stswi.set_cycles(1); + + stswx.set_asm("stswx %reg, %reg, %reg", rs, ra, rb); + stswx.set_decoder(opcd=31, xog=661); + stswx.set_cycles(1); + + stw.set_asm("stw %reg, %exp (%reg)", rs, d, ra); + stw.set_asm("stw %reg, %exp@l(%reg)", rs, d, ra); + stw.set_decoder(opcd=36); + stw.set_cycles(1); + + stwbrx.set_asm("stwbrx %reg, %reg, %reg", rs, ra, rb); + stwbrx.set_decoder(opcd=31, xog=662); + stwbrx.set_cycles(1); + + stwu.set_asm("stwu %reg, %imm (%reg)", rs, d, ra); + stwu.set_asm("stwu %reg, %imm (%reg)", rs, d, ra); + stwu.set_decoder(opcd=37); + stwu.set_cycles(1); + + stwux.set_asm("stwux %reg, %reg, %reg", rs, ra, rb); + stwux.set_decoder(opcd=31, xog=183); + stwux.set_cycles(1); + + stwx.set_asm("stwx %reg, %reg, %reg", rs, ra, rb); + stwx.set_decoder(opcd=31, xog=151); + stwx.set_cycles(1); + + subf.set_asm("subf %reg, %reg, %reg", rt, ra, rb); + subf.set_decoder(opcd=31, oe=0, xos=40, rc=0); + subf.set_cycles(1); + + subf_.set_asm("subf. %reg, %reg, %reg", rt, ra, rb); + subf_.set_decoder(opcd=31, oe=0, xos=40, rc=1); + subf_.set_cycles(1); + + subfo.set_asm("subfo %reg, %reg, %reg", rt, ra, rb); + subfo.set_decoder(opcd=31, oe=1, xos=40, rc=0); + subfo.set_cycles(1); + + subfo_.set_asm("subfo. %reg, %reg, %reg", rt, ra, rb); + subfo_.set_decoder(opcd=31, oe=1, xos=40, rc=1); + subfo_.set_cycles(1); + + subfc.set_asm("subfc %reg, %reg, %reg", rt, ra, rb); + subfc.set_decoder(opcd=31, oe=0, xos=8, rc=0); + subfc.set_cycles(1); + + subfc_.set_asm("subfc. %reg, %reg, %reg", rt, ra, rb); + subfc_.set_decoder(opcd=31, oe=0, xos=8, rc=1); + subfc_.set_cycles(1); + + subfco.set_asm("subfco %reg, %reg, %reg", rt, ra, rb); + subfco.set_decoder(opcd=31, oe=1, xos=8, rc=0); + subfco.set_cycles(1); + + subfco_.set_asm("subfco. %reg, %reg, %reg", rt, ra, rb); + subfco_.set_decoder(opcd=31, oe=1, xos=8, rc=1); + subfco_.set_cycles(1); + + subfe.set_asm("subfe %reg, %reg, %reg", rt, ra, rb); + subfe.set_decoder(opcd=31, oe=0, xos=136, rc=0); + subfe.set_cycles(1); + + subfe_.set_asm("subfe. %reg, %reg, %reg", rt, ra, rb); + subfe_.set_decoder(opcd=31, oe=0, xos=136, rc=1); + subfe_.set_cycles(1); + + subfeo.set_asm("subfeo %reg, %reg, %reg", rt, ra, rb); + subfeo.set_decoder(opcd=31, oe=1, xos=136, rc=0); + subfeo.set_cycles(1); + + subfeo_.set_asm("subfeo. %reg, %reg, %reg", rt, ra, rb); + subfeo_.set_decoder(opcd=31, oe=1, xos=136, rc=1); + subfeo_.set_cycles(1); + + subfic.set_asm("subfic %reg, %reg, %exp", rt, ra, d); + subfic.set_decoder(opcd=8); + subfic.set_cycles(1); + + subfme.set_asm("subfme %reg, %reg", rt, ra); + subfme.set_decoder(opcd=31, oe=0, xos=232, rc=0); + subfme.set_cycles(1); + + + subfme_.set_asm("subfme. %reg, %reg", rt, ra); + subfme_.set_decoder(opcd=31, oe=0, xos=232, rc=1); + subfme_.set_cycles(1); + + subfmeo.set_asm("subfmeo %reg, %reg", rt, ra); + subfmeo.set_decoder(opcd=31, oe=1, xos=232, rc=0); + subfmeo.set_cycles(1); + + subfmeo_.set_asm("subfmeo. %reg, %reg", rt, ra); + subfmeo_.set_decoder(opcd=31, oe=1, xos=232, rc=1); + subfmeo_.set_cycles(1); + + subfze.set_asm("subfze %reg, %reg", rt, ra); + subfze.set_decoder(opcd=31, oe=0, xos=200, rc=0); + subfze.set_cycles(1); + + subfze_.set_asm("subfze. %reg, %reg", rt, ra); + subfze_.set_decoder(opcd=31, oe=0, xos=200, rc=1); + subfze_.set_cycles(1); + + subfzeo.set_asm("subfzeo %reg, %reg", rt, ra); + subfzeo.set_decoder(opcd=31, oe=1, xos=200, rc=0); + subfzeo.set_cycles(1); + + subfzeo_.set_decoder(opcd=31, oe=1, xos=200, rc=1); + subfzeo_.set_asm("subfzeo. %reg, %reg", rt, ra); + subfzeo_.set_cycles(1); + + xxor.set_asm("xor %reg, %reg, %reg", ra, rs, rb); + xxor.set_decoder(opcd=31, xog=316, rc=0); + xxor.set_cycles(1); + + xxor_.set_asm("xor. %reg, %reg, %reg", ra, rs, rb); + xxor_.set_decoder(opcd=31, xog=316, rc=1); + xxor_.set_cycles(1); + + xori.set_asm("xori %reg, %reg, %imm", ra, rs, ui); + xori.set_decoder(opcd=26); + xori.set_cycles(1); + + xoris.set_asm("xoris %reg, %reg, %imm", ra, rs, ui); + xoris.set_decoder(opcd=27); + xoris.set_cycles(1); + + tw.set_asm("tw %imm, %reg, %reg", to, ra, rb); + tw.set_asm("tw%[trapcond] %reg, %reg", to, ra, rb); + tw.set_asm("trap", to=31, ra=0, rb=0); + tw.set_decoder(opcd=31, xog=4); + tw.set_cycles(1); + + twi.set_asm("twi %imm, %reg, %imm", to, ra, si); + twi.set_asm("tw%[trapcond]i %reg, %imm", to, ra, si); + twi.set_decoder(opcd=3); + twi.set_cycles(1); + + /* + * See Power ISA Version 3.1B, sections: + * - C.2.3 Branch Mnemonics Incorporating Conditions + * - 2.3.1 Condition Register + * + * Condition bits (bi_cg bitfield): + * + * 0...LT (The result is negative) + * 1...GT (The result is positive) + * 2...EQ (The result is zero) + * 3...SO (Summary Overflow) + * + * Condition under which is branch taken (bo bitfield) + * + * 0000z Decrement the CTR, then branch if the decremented CTRM:63!=0 and CRBI=0 + * 0001z Decrement the CTR, then branch if the decremented CTRM:63=0 and CRBI=0 + * 001at =0x4 Branch if CRBI=0 + * 0100z Decrement the CTR, then branch if the decremented CTRM:63!=0 and CRBI=1 + * 0101z Decrement the CTR, then branch if the decremented CTRM:63=0 and CRBI=1 + * 011at =0xC Branch if CRBI=1 + * 1a00t Decrement the CTR, then branch if the decremented CTRM:63≠0 + * 1a01t Decrement the CTR, then branch if the decremented CTRM:63=0 + * 1z1zz Branch always + * + * at=00 means no hint given + * z=0 should be ignored but some code expect it to be zero. + */ + + bc.set_asm("blt%[lk]%[aa] %addr(pcrel)", lk, aa, bd, bi_cf=0, bi_cb=0, bo=0xC); + bc.set_asm("blt%[lk]%[aa] %ccr, %addr(pcrel)", lk, aa, bi_cf, bd, bi_cb=0, bo=0xC); + + bc.set_asm("ble%[lk]%[aa] %addr(pcrel)", lk, aa, bd, bi_cf=0, bi_cb=1, bo=0x4); + bc.set_asm("ble%[lk]%[aa] %ccr, %addr(pcrel)", lk, aa, bi_cf, bd, bi_cb=1, bo=0x4); + + bc.set_asm("beq%[lk]%[aa] %addr(pcrel)", lk, aa, bd, bi_cf=0, bi_cb=2, bo=0xC); + bc.set_asm("beq%[lk]%[aa] %ccr, %addr(pcrel)", lk, aa, bi_cf, bd, bi_cb=2, bo=0xC); + + bc.set_asm("bge%[lk]%[aa] %addr(pcrel)", lk, aa, bd, bi_cf=0, bi_cb=0, bo=0x4); + bc.set_asm("bge%[lk]%[aa] %ccr, %addr(pcrel)", lk, aa, bi_cf, bd, bi_cb=0, bo=0x4); + + bc.set_asm("bgt%[lk]%[aa] %addr(pcrel)", lk, aa, bd, bi_cf=0, bi_cb=1, bo=0xC); + bc.set_asm("bgt%[lk]%[aa] %ccr, %addr(pcrel)", lk, aa, bi_cf, bd, bi_cb=1, bo=0xC); + + /* Following are here for completeness but commented out + * as in disassembly we prefer `bge` over `bnl`. + */ + //bc.set_asm("bnl%[lk]%[aa] %addr(pcrel)", lk, aa, bd, bi_cf=0, bi_cb=0, bo=0x4); + //bc.set_asm("bnl%[lk]%[aa] %ccr, %addr(pcrel)", lk, aa, bi_cf, bd, bi_cb=0, bo=0x4); + + bc.set_asm("bne%[lk]%[aa] %addr(pcrel)", lk, aa, bd, bi_cf=0, bi_cb=2, bo=0x4); + bc.set_asm("bne%[lk]%[aa] %ccr, %addr(pcrel)", lk, aa, bi_cf, bd, bi_cb=2, bo=0x4); + + /* Following are here for completeness but commented out + * as in disassembly we prefer `ble` over `bng`. + */ + //bc.set_asm("bng%[lk]%[aa] %addr(pcrel)", lk, aa, bd, bi_cf=0, bi_cb=1, bo=0x4); + //bc.set_asm("bng%[lk]%[aa] %ccr, %addr(pcrel)", lk, aa, bi_cf, bd, bi_cb=1, bo=0x4); + + bc.set_asm("bso%[lk]%[aa] %addr(pcrel)", lk, aa, bd, bi_cf=0, bi_cb=3, bo=0xC); + bc.set_asm("bso%[lk]%[aa] %ccr, %addr(pcrel)", lk, aa, bi_cf, bd, bi_cb=3, bo=0xC); + + bc.set_asm("bns%[lk]%[aa] %addr(pcrel)", lk, aa, bd, bi_cf=0, bi_cb=3, bo=0x4); + bc.set_asm("bns%[lk]%[aa] %ccr, %addr(pcrel)", lk, aa, bi_cf, bd, bi_cb=3, bo=0x4); + +/*******************************************************/ +/* Optional properties to optimize compiled simulation */ +/*******************************************************/ + + b.is_jump(ac_pc+(li<<2)); + + ba.is_jump(li<<2); + + bl.is_jump(ac_pc+(li<<2)); + bl.behavior(LR.write(ac_pc+4);); + + bla.is_jump(li<<2); + bla.behavior(LR.write(ac_pc+4);); + + + bc.is_branch(ac_pc+(bd<<2)); + bc.cond(test_Branch_Cond(CR,CTR,bo,bi)); + + bcctr.is_branch(CTR.read() & 0xFFFFFFFC); + bcctr.cond(test_Branch_Cond(CR,CTR,bo,bi)); + + bcctrl.is_branch(CTR.read() & 0xFFFFFFFC); + bcctrl.cond(test_Branch_Cond(CR,CTR,bo,bi)); + bcctrl.behavior(LR.write(ac_pc+4);); + + + bclr.is_branch(LR.read() & 0xFFFFFFFC); + bclr.cond(test_Branch_Cond(CR,CTR,bo,bi)); + + bclrl.is_branch(LR.read() & 0xFFFFFFFC); + bclrl.cond(test_Branch_Cond(CR,CTR,bo,bi)); + bclrl.behavior(LR.write(ac_pc+4);); + +/************************/ +/* Book II Instructions */ +/************************/ + + isync.set_asm("isync"); + isync.set_decoder(opcd=19, xog=150); + isync.set_cycles(1); + + sync.set_asm("sync %imm", l); + sync.set_asm("sync", l=0); + sync.set_asm("hwsync", l=0); + sync.set_asm("lwsync", l=1); + sync.set_decoder(opcd=31, xog=598); + sync.set_cycles(1); + +/***************************************/ +/* Synthetic Instructions */ +/***************************************/ + + pseudo_instr("mr %reg, %reg") { + "or %0, %1, %1"; + } + + pseudo_instr("subi %reg, %reg, %imm") { + "addi %0, %1, -%2"; + } + + pseudo_instr("subis %reg, %reg, %imm") { + "addis %0, %1, -%2"; + } + + pseudo_instr("srwi %reg, %reg, %imm") { + "rlwinm %0, %1, 32-%2, %2, 31"; + } + + pseudo_instr("crnot %reg, %reg") { + "crnor %0, %1, %1"; + } + + pseudo_instr("insrwi %reg, %reg, %imm, %imm") { + "rlwimi %0, %1, 32-%3-%2, %3, %3+%2-1"; + } + + pseudo_instr("slwi %reg, %reg, %imm") { + "rlwinm %0, %1, %2, 0, 31-%2"; + } + }; + +}; diff --git a/pdl/powerpc/powerpc_isa.cpp b/pdl/powerpc/powerpc_isa.cpp new file mode 100644 index 0000000..67acc47 --- /dev/null +++ b/pdl/powerpc/powerpc_isa.cpp @@ -0,0 +1,3357 @@ +/** + * @file powerpc_isa.cpp + * @author Bruno Corsi dos Santos + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:50:48 -0300 + * + * @brief The ArchC POWERPC functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +//IMPLEMENTATION NOTES: +// PowerPC 32 bits family. +// The PowerPC 405 instruction family are not implemented. +// Based on IBM and Xilinx manuals of PowerPC 405. +// mtspr and mfspr instructions not completely implemented. +// sc instruction not completely implemented and never used. + +#include "powerpc_isa.H" +#include "powerpc_isa_init.cpp" +#include "powerpc_bhv_macros.H" + +//If you want debug information for this model, uncomment next line +//#define DEBUG_MODEL +#include "ac_debug_model.H" + +#define DEFAULT_STACK_SIZE (512 * 1024) +static int processors_started = 0; + +using namespace powerpc_parms; + +#ifdef SLEEP_AWAKE_MODE +/*********************************************************************************/ +/* SLEEP / AWAKE mode control */ +/* INTR_REG may store 1 (AWAKE MODE) or 0 (SLEEP MODE) */ +/* if intr_reg == 0, the simulator will be suspended until it receives a */ +/* interruption 1 */ +/*********************************************************************************/ +#define test_sleep() { if (intr_reg.read() == 0) ac_wait(); } +#else +#define test_sleep() {} +#endif + +//Compute CR0 fields LT, GT, EQ, SO +//XER.SO must be updated by instruction before the use of this routine! +//Arguments: +//int result -> The result register +inline void CR0_update(ac_reg &CR, ac_reg &XER, unsigned int result) { + + /* LT field */ + if((result & 0x80000000) >> 31) + CR.write(CR.read() | 0x80000000); /* 1 */ + else + CR.write(CR.read() & 0x7FFFFFFF); /* 0 */ + + /* GT field */ + if(((~result & 0x80000000) >> 31) && (result!=0)) + CR.write(CR.read() | 0x40000000); /* 1 */ + else + CR.write(CR.read() & 0xBFFFFFFF); /* 0 */ + + /* EQ field */ + if(result==0) + CR.write(CR.read() | 0x20000000); /* 1 */ + else + CR.write(CR.read() & 0xDFFFFFFF); /* 0 */ + + /* SO field */ + if(XER.read() & 0x80000000) + CR.write(CR.read() | 0x10000000); /* 1 */ + else + CR.write(CR.read() & 0xEFFFFFFF); /* 0 */ +} + + +//Compute XER overflow fields SO, OV +//Arguments: +//int result -> The result register +//int s1 -> Source 1 +//int s2 -> Source 2 +//int s3 -> Source 3 (if only two sources, use 0) +inline void add_XER_OV_SO_update(ac_reg &XER, int result,int s1,int s2,int s3) { + + long long int longresult = + (long long int)(int)s1 + (long long int)(int)s2 + (long long int)(int)s3; + + if(longresult != (long long int)(int)result) { + XER.write(XER.read() | 0x40000000); /* Write 1 to bit 1 OV */ + XER.write(XER.read() | 0x80000000); /* Write 1 to bit 0 SO */ + } + else { + XER.write(XER.read() & 0xBFFFFFFF); /* Write 0 to bit 1 OV */ + } +} + + +//Compute XER carry field CA +//Arguments: +//int result -> The result register +//int s1 -> Source 1 +//int s2 -> Source 2 +//int s3 -> Source 3 (if only two sources, use 0) +inline void add_XER_CA_update(ac_reg &XER, int result,int s1,int s2,int s3) { + + unsigned long long int longresult = + (unsigned long long int)(unsigned int)s1 + + (unsigned long long int)(unsigned int)s2 + + (unsigned long long int)(unsigned int)s3; + + if(longresult > 0xFFFFFFFF) + XER.write(XER.read() | 0x20000000); /* Write 1 to bit 2 CA */ + else + XER.write(XER.read() & 0xDFFFFFFF); /* Write 0 to bit 2 CA */ + +} + +//Compute XER overflow fields SO, OV +//Arguments: +//int result -> The result register +//int s1 -> Source 1 +//int s2 -> Source 2 +inline void divws_XER_OV_SO_update(ac_reg &XER, int result,int s1,int s2) { + + long long int longresult = + (long long int)(int)s1 / (long long int)(int)s2; + + if(longresult != (long long int)(int)result) { + XER.write(XER.read() | 0x40000000); /* Write 1 to bit 1 OV */ + XER.write(XER.read() | 0x80000000); /* Write 1 to bit 0 SO */ + } + else + XER.write(XER.read() & 0xBFFFFFFF); /* Write 0 to bit 1 OV */ + +} + + +//Compute XER overflow fields SO, OV +//Arguments: +//int result -> The result register +//int s1 -> Source 1 +//int s2 -> Source 2 +inline void divwu_XER_OV_SO_update(ac_reg &XER, int result,int s1,int s2) { + + unsigned long long int longresult = + (unsigned long long int)(unsigned int)s1 / + (unsigned long long int)(unsigned int)s2; + + if(longresult != (unsigned long long int)(unsigned int)result) { + XER.write(XER.read() | 0x40000000); /* Write 1 to bit 1 OV */ + XER.write(XER.read() | 0x80000000); /* Write 1 to bit 0 SO */ + } + else + XER.write(XER.read() & 0xBFFFFFFF); /* Write 0 to bit 1 OV */ + +} + + +//Function to do_branch +inline void do_Branch(ac_reg &ac_pc, ac_reg &LR, signed int ili,unsigned int iaa,unsigned int ilk) { + + int displacement; + unsigned int nia; + + ac_pc-=4; /* Because pre-increment */ + + if(iaa==1) { + displacement=ili<<2; + nia=displacement; + } + else { /* iaa=0 */ + displacement=ili<<2; + nia=ac_pc+displacement; + } + + if(ilk==1) + LR.write(ac_pc+4); + + ac_pc=nia; + +} + +//Function to do conditional branch +inline void do_Branch_Cond(ac_reg &ac_pc, ac_reg &LR, ac_reg &CR, ac_reg &CTR, unsigned int ibo,unsigned int ibi, + signed int ibd,unsigned int iaa, + unsigned int ilk) { + + int displacement; + unsigned int nia; + unsigned int masc; + + masc=0x80000000; + masc=masc>>ibi; + + ac_pc-=4; /* Because pre-increment */ + + if((ibo & 0x04) == 0x00) { + CTR.write(CTR.read()-1); + } + + if(((ibo & 0x04) || /* Branch */ + ((CTR.read()==0) && (ibo & 0x02)) || + (!(CTR.read()==0) && !(ibo & 0x02))) + && + ((ibo & 0x10) || + (((CR.read() & masc) && (ibo & 0x08)) || + (!(CR.read() & masc) && !(ibo & 0x08))))) { + + if(iaa == 1) { + displacement=ibd<<2; + nia=displacement; + } + else { + displacement=ibd<<2; + nia=ac_pc+displacement; + } + } + else { /* No branch */ + nia=ac_pc+4; + } + + if(ilk==1) + LR.write(ac_pc+4); + + ac_pc=nia; + +} + +//Function to do conditional branch to count register +inline void do_Branch_Cond_Count_Reg(ac_reg &ac_pc, ac_reg &LR, ac_reg &CR, ac_reg &CTR, unsigned int ibo, unsigned int ibi, + unsigned int ilk) { + + unsigned int nia; + unsigned int masc; + + masc=0x80000000; + masc=masc>>ibi; + + ac_pc-=4; /* Because pre-increment */ + + if((ibo & 0x04) == 0x00) + CTR.write(CTR.read()-1); + + if(((ibo & 0x04) || /* Branch */ + ((CTR.read()==0) && (ibo & 0x02)) || + (!(CTR.read()==0) && !(ibo & 0x02))) + && + ((ibo & 0x10) || + (((CR.read() & masc) && (ibo & 0x08)) || + (!(CR.read() & masc) && !(ibo & 0x08))))) { + + nia=CTR.read() & 0xFFFFFFFC; + + } + else { /* No Branch */ + nia=ac_pc+4; + } + + if(ilk==1) + LR.write(ac_pc+4); + + ac_pc=nia; + +} + +//Function to do conditional branch to link register +inline void do_Branch_Cond_Link_Reg(ac_reg &ac_pc, ac_reg &LR, ac_reg &CR, ac_reg &CTR,unsigned int ibo,unsigned int ibi, + unsigned int ilk) { + + unsigned int nia; + unsigned int masc; + + masc=0x80000000; + masc=masc>>ibi; + + ac_pc-=4; /* Because pre-increment */ + + if((ibo & 0x04) == 0x00) + CTR.write(CTR.read()-1); + + if(((ibo & 0x04) || /* Branch */ + ((CTR.read()==0) && (ibo & 0x02)) || + (!(CTR.read()==0) && !(ibo & 0x02))) + && + ((ibo & 0x10) || + (((CR.read() & masc) && (ibo & 0x08)) || + (!(CR.read() & masc) && !(ibo & 0x08))))) { + + nia=LR.read() & 0xFFFFFFFC; + + } + else { /* No Branch */ + nia=ac_pc+4; + } + + if(ilk==1) + LR.write(ac_pc+4); + + ac_pc=nia; + +} + +#ifdef AC_COMPSIM +//Function to test if conditional branch is taken +int test_Branch_Cond(ac_reg &CR, ac_reg &CTR, unsigned int ibo, unsigned int ibi) { + + unsigned int masc; + unsigned int test; + + masc=0x80000000; + masc=masc>>ibi; + + if((ibo & 0x04) == 0x00) + CTR.write(CTR.read()-1); + + if(((ibo & 0x04) || /* Branch */ + ((CTR.read()==0) && (ibo & 0x02)) || + (!(CTR.read()==0) && !(ibo & 0x02))) + && + ((ibo & 0x10) || + (((CR.read() & masc) && (ibo & 0x08)) || + (!(CR.read() & masc) && !(ibo & 0x08))))) + return 1; + + else /* No Branch */ + return 0; +} +#endif + +//Ceil function +inline int ceil(int value, int divisor) { + int res; + if ((value % divisor)!=0) + res=int(value/divisor)+1; + else res=value/divisor; + return res; +} + +//Rotl function +inline unsigned int rotl(unsigned int reg,unsigned int n) { + unsigned int tmp1=reg; + unsigned int tmp2=reg; + unsigned int rotated=(tmp1 << n) | (tmp2 >> 32-n); + + return(rotated); +} + +//Mask32rlw function +inline unsigned int mask32rlw(unsigned int i,unsigned int f) { + + unsigned int maski,maskf; + + if(i<=f) { + maski=(0xFFFFFFFF>>i); + maskf=(0xFFFFFFFF<<(31-f)); + return(maski & maskf); + } + else { + maski=(0xFFFFFFFF>>f); + maski=maski>>1; + maskf=(0xFFFFFFFF<<(31-i)); + maskf=maskf<<1; + return(~(maski & maskf)); + } + +} + + +//Function dump General Purpose Registers +inline void dumpGPR(ac_regbank<32, ac_word, ac_Dword> &GPR) { + int i; + for(i=0 ; i<32 ; i++) + dbg_printf("r%d -> %#x \n",i,GPR.read(i)); +} + +//Function that returns the value of XER TBC +inline unsigned int XER_TBC_read(ac_reg &XER) { + return(XER.read() & 0x0000007F); +} + + +//Function that returns the value of XER OV +inline unsigned int XER_OV_read(ac_reg &XER) { + if(XER.read() & 0x40000000) + return 1; + else + return 0; +} + +//Function that returns the value of XER SO +inline unsigned int XER_SO_read(ac_reg &XER) { + if(XER.read() & 0x80000000) + return 1; + else + return 0; +} + +//Function that returns the value of XER CA +inline unsigned int XER_CA_read(ac_reg &XER) { + if(XER.read() & 0x20000000) + return 1; + else + return 0; +} + + +//Function dump various registers +inline void dumpREG(ac_reg &XER, ac_reg &CR, ac_reg &LR, ac_reg &CTR) { + dbg_printf("XER.OV = %d\n",XER_OV_read(XER)); + dbg_printf("XER.SO = %d\n",XER_SO_read(XER)); + dbg_printf("XER.CA = %d\n",XER_CA_read(XER)); + dbg_printf("CR = %#x\n",CR.read()); + dbg_printf("LR = %#x\n",LR.read()); + dbg_printf("CTR = %#x\n",CTR.read()); +} + + + +//!Generic instruction behavior method. +void ac_behavior( instruction ) +{ + + test_sleep(); + + dbg_printf("\n program counter=%#x\n",(int)ac_pc); + ac_pc+=4; + //dumpGPR(); + //dumpREG(); +} + +//!Generic begin behavior method. +void ac_behavior( begin ) +{ + dbg_printf("Starting simulator...\n"); + + /* Here the stack is started in a */ + // GPR.write(1,AC_RAM_END - 1024); + GPR.write(1, AC_RAM_END - 1024 - processors_started++ * DEFAULT_STACK_SIZE); + /* Make a jump out of DC_portory if it doesn't have an abi */ + LR.write(0xFFFFFFFF); + +} + +void ac_behavior(end) +{ + dbg_printf("@@@ end behavior @@@\n"); +} + +//! Instruction Format behavior methods. +void ac_behavior( I1 ){} +void ac_behavior( B1 ){} +void ac_behavior( SC1 ){} +void ac_behavior( D1 ){} +void ac_behavior( D2 ){} +void ac_behavior( D3 ){} +void ac_behavior( D4 ){} +void ac_behavior( D5 ){} +void ac_behavior( D6 ){} +void ac_behavior( D7 ){} +void ac_behavior( X1 ){} +void ac_behavior( X2 ){} +void ac_behavior( X3 ){} +void ac_behavior( X4 ){} +void ac_behavior( X5 ){} +void ac_behavior( X6 ){} +void ac_behavior( X7 ){} +void ac_behavior( X8 ){} +void ac_behavior( X9 ){} +void ac_behavior( X10 ){} +void ac_behavior( X11 ){} +void ac_behavior( X12 ){} +void ac_behavior( X13 ){} +void ac_behavior( X14 ){} +void ac_behavior( X15 ){} +void ac_behavior( X16 ){} +void ac_behavior( X17 ){} +void ac_behavior( X18 ){} +void ac_behavior( X19 ){} +void ac_behavior( X20 ){} +void ac_behavior( X21 ){} +void ac_behavior( X22 ){} +void ac_behavior( X23 ){} +void ac_behavior( X24 ){} +void ac_behavior( X25 ){} +void ac_behavior( XL1 ){} +void ac_behavior( XL2 ){} +void ac_behavior( XL3 ){} +void ac_behavior( XL4 ){} +void ac_behavior( XFX1 ){} +void ac_behavior( XFX2 ){} +void ac_behavior( XFX3 ){} +void ac_behavior( XFX4 ){} +void ac_behavior( XFX5 ){} +void ac_behavior( XO1 ){} +void ac_behavior( XO2 ){} +void ac_behavior( XO3 ){} +void ac_behavior( M1 ){} +void ac_behavior( M2 ){} + + +//!Instruction add behavior method. +void ac_behavior( add ) +{ + dbg_printf(" add r%d, r%d, r%d\n\n",rt,ra,rb); + GPR.write(rt,GPR.read(ra) + GPR.read(rb)); + +}; + +//!Instruction add_ behavior method. +void ac_behavior( add_ ) +{ + dbg_printf(" add. r%d, r%d, r%d\n\n",rt,ra,rb); + int result=GPR.read(ra) + GPR.read(rb); + + CR0_update(CR, XER, result); + GPR.write(rt,result); + +}; + +//!Instruction addo behavior method. +void ac_behavior( addo ) +{ + dbg_printf(" addo r%d, r%d, r%d\n\n",rt,ra,rb); + int result=GPR.read(ra) + GPR.read(rb); + + add_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb),0); + + GPR.write(rt,result); + +}; + +//!Instruction addo_ behavior method. +void ac_behavior( addo_ ) +{ + dbg_printf(" addo. r%d, r%d, r%d\n\n",rt,ra,rb); + int result=GPR.read(ra) + GPR.read(rb); + + /* Note: XER_OV_SO_update before CR0_update */ + add_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb),0); + CR0_update(CR, XER, result); + GPR.write(rt,result); + +}; + +//!Instruction addc behavior method. +void ac_behavior( addc ) +{ + dbg_printf(" addc r%d, r%d, r%d\n\n",rt,ra,rb); + int result=GPR.read(ra) + GPR.read(rb); + + add_XER_CA_update(XER, result,GPR.read(ra),GPR.read(rb),0); + GPR.write(rt,result); + +}; + +//!Instruction addc_ behavior method. +void ac_behavior( addc_ ) +{ + dbg_printf(" addc. r%d, r%d, r%d\n\n",rt,ra,rb); + int result=GPR.read(ra) + GPR.read(rb); + + add_XER_CA_update(XER, result,GPR.read(ra),GPR.read(rb),0); + + CR0_update(CR, XER, result); + +}; + +//!Instruction addco behavior method. +void ac_behavior( addco ) +{ + dbg_printf(" addco r%d, r%d, r%d\n\n",rt,ra,rb); + int result=GPR.read(ra) + GPR.read(rb); + + add_XER_CA_update(XER, result,GPR.read(ra),GPR.read(rb),0); + + add_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb),0); + + GPR.write(rt,result); + +}; + +//!Instruction addco_ behavior method. +void ac_behavior( addco_ ) +{ + dbg_printf(" addco. r%d, r%d, r%d\n\n",rt,ra,rb); + int result=GPR.read(ra) + GPR.read(rb); + + add_XER_CA_update(XER, result,GPR.read(ra),GPR.read(rb),0); + + /* Note: XER_OV_SO_update before CR0_update */ + add_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb),0); + CR0_update(CR, XER, result); + + GPR.write(rt,result); + +}; + +//!Instruction adde behavior method. +void ac_behavior( adde ) +{ + dbg_printf(" adde r%d, r%d, r%d\n\n",rt,ra,rb); + + int result=GPR.read(ra) + GPR.read(rb) + XER_CA_read(XER); + + add_XER_CA_update(XER, result,GPR.read(ra),GPR.read(rb),XER_CA_read(XER)); + + GPR.write(rt,result); + +}; + +//!Instruction adde_ behavior method. +void ac_behavior( adde_ ) +{ + dbg_printf(" adde. r%d, r%d, r%d\n\n",rt,ra,rb); + + int result=GPR.read(ra) + GPR.read(rb) + XER_CA_read(XER); + + add_XER_CA_update(XER, result,GPR.read(ra),GPR.read(rb),XER_CA_read(XER)); + + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction addeo behavior method. +void ac_behavior( addeo ) +{ + dbg_printf(" addeo r%d, r%d, r%d\n\n",rt,ra,rb); + + int result=GPR.read(ra) + GPR.read(rb) + XER_CA_read(XER); + + add_XER_CA_update(XER, result,GPR.read(ra),GPR.read(rb),XER_CA_read(XER)); + + add_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb),XER_CA_read(XER)); + + GPR.write(rt,result); +}; + +//!Instruction addeo_ behavior method. +void ac_behavior( addeo_ ) +{ + dbg_printf(" addeo. r%d, r%d, r%d\n\n",rt,ra,rb); + + int result=GPR.read(ra) + GPR.read(rb) + XER_CA_read(XER); + + add_XER_CA_update(XER, GPR.read(rt),GPR.read(ra),GPR.read(rb),XER_CA_read(XER)); + + /* Note: XER_OV_SO_update before CR0_update */ + add_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb),XER_CA_read(XER)); + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction addi behavior method. +void ac_behavior( addi ) +{ + dbg_printf(" addi r%d, r%d, %d\n\n",rt,ra,d); + + int ime32=d; + + if(ra == 0) + GPR.write(rt,ime32); + else + GPR.write(rt,GPR.read(ra)+ime32); + +}; + +//!Instruction addic behavior method. +void ac_behavior( addic ) +{ + dbg_printf(" addic r%d, r%d, %d\n\n",rt,ra,d); + int ime32=d; + int result=GPR.read(ra)+ime32; + + add_XER_CA_update(XER, result,GPR.read(ra),ime32,0); + + GPR.write(rt,result); +}; + +//!Instruction addic_ behavior method. +void ac_behavior( addic_ ) +{ + dbg_printf(" addic. r%d, r%d, %d\n\n",rt,ra,d); + /* Do not have rc field and update CR0 */ + int ime32=d; + int result=GPR.read(ra)+ime32; + + add_XER_CA_update(XER, result,GPR.read(ra),ime32,0); + + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction addis behavior method. +void ac_behavior( addis ) +{ + dbg_printf(" addis r%d, r%d, %d\n\n",rt,ra,d); + int ime32=d; + ime32=ime32<<16; + + if(ra == 0) + GPR.write(rt,ime32); + else + GPR.write(rt,GPR.read(ra)+ime32); + +}; + +//!Instruction addme behavior method. +void ac_behavior( addme ) +{ + dbg_printf(" addme r%d, r%d\n\n",rt,ra); + int result=GPR.read(ra)+XER_CA_read(XER)+(-1); + + add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),-1); + + GPR.write(rt,result); +}; + +//!Instruction addme_ behavior method. +void ac_behavior( addme_ ) +{ + dbg_printf(" addme. r%d, r%d\n\n",rt,ra); + int result=GPR.read(ra)+XER_CA_read(XER)+(-1); + + add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),-1); + + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction addmeo behavior method. +void ac_behavior( addmeo ) +{ + dbg_printf(" addmeo r%d, r%d\n\n",rt,ra); + int result=GPR.read(ra)+XER_CA_read(XER)+(-1); + + add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),-1); + + add_XER_OV_SO_update(XER, result,GPR.read(ra),XER_CA_read(XER),-1); + + GPR.write(rt,result); +}; + +//!Instruction addmeo_ behavior method. +void ac_behavior( addmeo_ ) +{ + dbg_printf(" addmeo. r%d, r%d\n\n",rt,ra); + int result=GPR.read(ra)+XER_CA_read(XER)+(-1); + + add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),-1); + + /* Note: XER_OV_SO_update before CR0_update */ + add_XER_OV_SO_update(XER, result,GPR.read(ra),XER_CA_read(XER),-1); + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction addze behavior method. +void ac_behavior( addze ) +{ + dbg_printf(" addze r%d, r%d\n\n",rt,ra); + int result=GPR.read(ra)+XER_CA_read(XER); + + add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),0); + + GPR.write(rt,result); +}; + +//!Instruction addze_ behavior method. +void ac_behavior( addze_ ) +{ + dbg_printf(" addze. %d, %d\n\n",rt,ra); + int result=GPR.read(ra)+XER_CA_read(XER); + + add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),0); + + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction addzeo behavior method. +void ac_behavior( addzeo ) +{ + dbg_printf(" addzeo r%d, r%d\n\n",rt,ra); + int result=GPR.read(ra)+XER_CA_read(XER); + + add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),0); + + add_XER_OV_SO_update(XER, result,GPR.read(ra),XER_CA_read(XER),0); + + GPR.write(rt,result); +}; + +//!Instruction addzeo_ behavior method. +void ac_behavior( addzeo_ ) +{ + dbg_printf(" addzeo. r%d, r%d\n\n",rt,ra); + int result=GPR.read(ra)+XER_CA_read(XER); + + add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),0); + + /* Note: XER_OV_SO_update before CR0_update */ + add_XER_OV_SO_update(XER, result,GPR.read(ra),XER_CA_read(XER),0); + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction ande behavior method. +void ac_behavior( ande ) +{ + dbg_printf(" and r%d, r%d, r%d\n\n",ra,rs,rb); + GPR.write(ra,GPR.read(rs) & GPR.read(rb)); + +}; + +//!Instruction ande_ behavior method. +void ac_behavior( ande_ ) +{ + dbg_printf(" and. r%d, r%d, r%d\n\n",ra,rs,rb); + int result=GPR.read(rs) & GPR.read(rb); + + CR0_update(CR, XER, result); + + GPR.write(ra,result); +}; + +//!Instruction andc behavior method. +void ac_behavior( andc ) +{ + dbg_printf(" andc r%d, r%d, r%d\n\n",ra,rs,rb); + GPR.write(ra,GPR.read(rs) & ~GPR.read(rb)); + +}; + +//!Instruction ande_ behavior method. +void ac_behavior( andc_ ) +{ + dbg_printf(" andc. r%d, r%d, r%d\n\n",ra,rs,rb); + int result=GPR.read(rs) & ~GPR.read(rb); + + CR0_update(CR, XER, result); + + GPR.write(ra,result); +}; + +//!Instruction andi_ behavior method. +void ac_behavior( andi_ ) +{ + dbg_printf(" andi. r%d, r%d, %d\n\n",ra,rs,ui); + unsigned int ime32=(unsigned short int)ui; + int result=GPR.read(rs) & ime32; + + CR0_update(CR, XER, result); + + GPR.write(ra,result); +}; + +//!Instruction andis_ behavior method. +void ac_behavior( andis_ ) +{ + dbg_printf(" andis. r%d, r%d, %d\n\n",ra,rs,ui); + unsigned int ime32=(unsigned short int)ui; + + ime32=ime32<<16; + int result=GPR.read(rs) & ime32; + + CR0_update(CR, XER, result); + + GPR.write(ra,result); +}; + +//!Instruction b behavior method. +void ac_behavior( b ) +{ + dbg_printf(" b %d\n\n",li); + do_Branch(ac_pc, LR, li,aa,lk); + +}; + +//!Instruction ba behavior method. +void ac_behavior( ba ) +{ + dbg_printf(" ba %d\n\n",li); + do_Branch(ac_pc, LR, li,aa,lk); + +}; + +//!Instruction bl behavior method. +void ac_behavior( bl ) +{ + dbg_printf(" bl %d\n\n",li); + do_Branch(ac_pc, LR, li,aa,lk); + +}; + +//!Instruction bla behavior method. +void ac_behavior( bla ) +{ + dbg_printf(" bla %d\n\n",li); + do_Branch(ac_pc, LR, li,aa,lk); + +}; + +//!Instruction bc behavior method. +void ac_behavior( bc ) +{ + dbg_printf(" bc %d, %d, %d\n\n",bo,bi,bd); + do_Branch_Cond(ac_pc, LR, CR, CTR, bo,bi,bd,aa,lk); + +}; + +//!Instruction bca behavior method. +void ac_behavior( bca ) +{ + dbg_printf(" bca %d, %d, %d\n\n",bo,bi,bd); + do_Branch_Cond(ac_pc, LR, CR, CTR, bo,bi,bd,aa,lk); + +}; + +//!Instruction bcl behavior method. +void ac_behavior( bcl ) +{ + dbg_printf(" bcl %d, %d, %d\n\n",bo,bi,bd); + do_Branch_Cond(ac_pc, LR, CR, CTR, bo,bi,bd,aa,lk); + +}; + +//!Instruction bcla behavior method. +void ac_behavior( bcla ) +{ + dbg_printf(" bcla %d, %d, %d\n\n",bo,bi,bd); + do_Branch_Cond(ac_pc, LR, CR, CTR, bo,bi,bd,aa,lk); + +}; + +//!Instruction bcctr behavior method. +void ac_behavior( bcctr ) +{ + dbg_printf(" bcctr %d, %d\n\n",bo,bi); + do_Branch_Cond_Count_Reg(ac_pc, LR, CR, CTR,bo,bi,lk); + +}; + +//!Instruction bcctrl behavior method. +void ac_behavior( bcctrl ) +{ + dbg_printf(" bcctrl %d, %d\n\n",bo,bi); + do_Branch_Cond_Count_Reg(ac_pc, LR, CR, CTR,bo,bi,lk); + +}; + +//!Instruction bclr behavior method. +void ac_behavior( bclr ) +{ + dbg_printf(" bclr %d, %d\n\n",bo,bi); + do_Branch_Cond_Link_Reg(ac_pc, LR, CR, CTR,bo,bi,lk); + +}; + +//!Instruction bclrl behavior method. +void ac_behavior( bclrl ) +{ + dbg_printf(" bclrl %d, %d\n\n",bo,bi); + do_Branch_Cond_Link_Reg(ac_pc, LR, CR, CTR,bo,bi,lk); + +}; + +//!Instruction cmp behavior method. +void ac_behavior( cmp ) +{ + dbg_printf(" cmp crf%d, 0, r%d, r%d\n\n",bf,ra,rb); + unsigned int c=0x00; + unsigned int n=bf; + unsigned int masc=0xF0000000; + + if((int)GPR.read(ra) < (int)GPR.read(rb)) + c = c | 0x80000000; + if((int)GPR.read(ra) > (int)GPR.read(rb)) + c = c | 0x40000000; + if((int)GPR.read(ra) == (int)GPR.read(rb)) + c = c | 0x20000000; + if(XER_SO_read(XER)==1) + c = c | 0x10000000; + + c = c >> (n*4); + masc = ~(masc >> (n*4)); + + CR.write((CR.read() & masc) | c); + +}; + +//!Instruction cmpi behavior method. +void ac_behavior( cmpi ) +{ + dbg_printf(" cmpi crf%d, 0, r%d, %d\n\n",bf,ra,si); + unsigned int c=0x00; + unsigned int n=bf; + unsigned int masc=0xF0000000; + + int ime32=(short int)(si); + + if((int)GPR.read(ra) < ime32) + c = c | 0x80000000; + if((int)GPR.read(ra) > ime32) + c = c | 0x40000000; + if((int)GPR.read(ra) == ime32) + c = c | 0x20000000; + if(XER_SO_read(XER)==1) + c = c | 0x10000000; + + c = c >> (n*4); + masc = ~(masc >> (n*4)); + + CR.write((CR.read() & masc) | c); + +}; + +//!Instruction cmpl behavior method. +void ac_behavior( cmpl ) +{ + dbg_printf(" cmpl crf%d, 0, r%d, r%d\n\n",bf,ra,rb); + unsigned int c=0x00; + unsigned int n=bf; + unsigned int masc=0xF0000000; + + unsigned int uintra=GPR.read(ra); + unsigned int uintrb=GPR.read(rb); + + if(uintra < uintrb) + c = c | 0x80000000; + if(uintra > uintrb) + c = c | 0x40000000; + if(uintra == uintrb) + c = c | 0x20000000; + if(XER_SO_read(XER)==1) + c = c | 0x10000000; + + c = c >> (n*4); + masc = ~(masc >> (n*4)); + + CR.write((CR.read() & masc) | c); + +}; + +//!Instruction cmpli behavior method. +void ac_behavior( cmpli ) +{ + dbg_printf(" cmpli crf%d, 0, r%d, %d\n\n",bf,ra,ui); + unsigned int c=0x00; + unsigned int n=bf; + unsigned int masc=0xF0000000; + + unsigned int ime32=(unsigned short int)(ui); + + if(GPR.read(ra) < ime32) + c = c | 0x80000000; + if(GPR.read(ra) > ime32) + c = c | 0x40000000; + if(GPR.read(ra) == ime32) + c = c | 0x20000000; + if(XER_SO_read(XER)==1) + c = c | 0x10000000; + + c = c >> (n*4); + masc = ~(masc >> (n*4)); + + CR.write((CR.read() & masc) | c); + +}; + +//!Instruction cntlzw behavior method. +void ac_behavior( cntlzw ) +{ + dbg_printf(" cntlzw r%d, r%d\n\n",ra,rs); + + unsigned int urs=GPR.read(rs); + unsigned int masc=0x80000000; + unsigned int n=0; + + while(n < 32) { + if(urs & masc) + break; + n++; + masc=masc>>1; + } + + GPR.write(ra,n); + +}; + +//!Instruction cntlzw_ behavior method. +void ac_behavior( cntlzw_ ) +{ + dbg_printf(" cntlzw. r%d, r%d\n\n",ra,rs); + + unsigned int urs=GPR.read(rs); + unsigned int masc=0x80000000; + unsigned int n=0; + + while(n < 32) { + if(urs & masc) + break; + n++; + masc=masc>>1; + } + + GPR.write(ra,n); + CR0_update(CR, XER, n); + +}; + +//!Instruction crand behavior method. +void ac_behavior( crand ) +{ + dbg_printf(" crand %d, %d, %d\n\n",bt,ba,bb); + + unsigned int CRbt; + unsigned int CRba; + unsigned int CRbb; + + CRba=CR.read(); + CRbb=CR.read(); + + /* Shift source bit to first position and zero another */ + CRba=(CRba<>bt; + + if(CRbt) + CR.write(CR.read() | CRbt); + else + CR.write(CR.read() & ~(0x80000000 >> bt)); + +}; + +//!Instruction crandc behavior method. +void ac_behavior( crandc ) +{ + dbg_printf(" crandc %d, %d, %d\n\n",bt,ba,bb); + + unsigned int CRbt; + unsigned int CRba; + unsigned int CRbb; + + CRba=CR.read(); + CRbb=CR.read(); + + /* Shift source bit to first position and zero another */ + CRba=(CRba<>bt; + + if(CRbt) + CR.write(CR.read() | CRbt); + else + CR.write(CR.read() & ~(0x80000000 >> bt)); + +}; + +//!Instruction creqv behavior method. +void ac_behavior( creqv ) +{ + dbg_printf(" creqv %d, %d, %d\n\n",bt,ba,bb); + + unsigned int CRbt; + unsigned int CRba; + unsigned int CRbb; + + CRba=CR.read(); + CRbb=CR.read(); + + /* Shift source bit to first position and zero another */ + CRba=(CRba<>bt; + + if(CRbt) + CR.write(CR.read() | CRbt); + else + CR.write(CR.read() & ~(0x80000000 >> bt)); + +}; + +//!Instruction crnand behavior method. +void ac_behavior( crnand ) +{ + dbg_printf(" crnand %d, %d, %d\n\n",bt,ba,bb); + + unsigned int CRbt; + unsigned int CRba; + unsigned int CRbb; + + CRba=CR.read(); + CRbb=CR.read(); + + /* Shift source bit to first position and zero another */ + CRba=(CRba<>bt; + + if(CRbt) + CR.write(CR.read() | CRbt); + else + CR.write(CR.read() & ~(0x80000000 >> bt)); + +}; + +//!Instruction crnor behavior method. +void ac_behavior( crnor ) +{ + dbg_printf(" crnor %d, %d, %d\n\n",bt,ba,bb); + + unsigned int CRbt; + unsigned int CRba; + unsigned int CRbb; + + CRba=CR.read(); + CRbb=CR.read(); + + /* Shift source bit to first position and zero another */ + CRba=(CRba<>bt; + + if(CRbt) + CR.write(CR.read() | CRbt); + else + CR.write(CR.read() & ~(0x80000000 >> bt)); + +}; + +//!Instruction cror behavior method. +void ac_behavior( cror ) +{ + dbg_printf(" cror %d, %d, %d\n\n",bt,ba,bb); + + unsigned int CRbt; + unsigned int CRba; + unsigned int CRbb; + + CRba=CR.read(); + CRbb=CR.read(); + + /* Shift source bit to first position and zero another */ + CRba=(CRba<>bt; + + if(CRbt) + CR.write(CR.read() | CRbt); + else + CR.write(CR.read() & ~(0x80000000 >> bt)); + +}; + +//!Instruction crorc behavior method. +void ac_behavior( crorc ) +{ + dbg_printf(" crorc %d, %d, %d\n\n",bt,ba,bb); + + unsigned int CRbt; + unsigned int CRba; + unsigned int CRbb; + + CRba=CR.read(); + CRbb=CR.read(); + + /* Shift source bit to first position and zero another */ + CRba=(CRba<>bt; + + if(CRbt) + CR.write(CR.read() | CRbt); + else + CR.write(CR.read() & ~(0x80000000 >> bt)); + +}; + +//!Instruction crxor behavior method. +void ac_behavior( crxor ) +{ + dbg_printf(" crxor %d, %d, %d\n\n",bt,ba,bb); + + unsigned int CRbt; + unsigned int CRba; + unsigned int CRbb; + + CRba=CR.read(); + CRbb=CR.read(); + + /* Shift source bit to first position and zero another */ + CRba=(CRba<>bt; + + if(CRbt) + CR.write(CR.read() | CRbt); + else + CR.write(CR.read() & ~(0x80000000 >> bt)); + +}; + +//!Instruction divw behavior method. +void ac_behavior( divw ) +{ + dbg_printf(" divw r%d, r%d, r%d\n\n",rt,ra,rb); + + GPR.write(rt,(int)GPR.read(ra)/(int)GPR.read(rb)); + +}; + +//!Instruction divw_ behavior method. +void ac_behavior( divw_ ) +{ + dbg_printf(" divw. r%d, r%d, r%d\n\n",rt,ra,rb); + int result=(int)GPR.read(ra)/(int)GPR.read(rb); + + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction divwo behavior method. +void ac_behavior( divwo ) +{ + dbg_printf(" divwo r%d, r%d, r%d\n\n",rt,ra,rb); + int result=(int)GPR.read(ra)/(int)GPR.read(rb); + + divws_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb)); + + GPR.write(rt,result); +}; + +//!Instruction divwo_ behavior method. +void ac_behavior( divwo_ ) +{ + dbg_printf(" divwo_ r%d, r%d, r%d\n\n",rt,ra,rb); + + int result=(int)GPR.read(ra)/(int)GPR.read(rb); + + /* Note: XER_OV_SO_update before CR0_update */ + divws_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb)); + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction divw behavior method. +void ac_behavior( divwu ) +{ + dbg_printf(" divwu r%d, r%d, r%d\n\n",rt,ra,rb); + + GPR.write(rt,(unsigned int)GPR.read(ra)/(unsigned int)GPR.read(rb)); + +}; + +//!Instruction divwu_ behavior method. +void ac_behavior( divwu_ ) +{ + dbg_printf(" divwu. r%d, r%d, r%d\n\n",rt,ra,rb); + + unsigned int result=(unsigned int)GPR.read(ra)/(unsigned int)GPR.read(rb); + + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction divwou behavior method. +void ac_behavior( divwou ) +{ + dbg_printf(" divwou r%d, r%d, r%d\n\n",rt,ra,rb); + + unsigned int result=(unsigned int)GPR.read(ra)/(unsigned int)GPR.read(rb); + + divwu_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb)); + + GPR.write(rt,result); +}; + +//!Instruction divwou_ behavior method. +void ac_behavior( divwou_ ) +{ + dbg_printf(" divwou_ r%d, r%d, r%d\n\n",rt,ra,rb); + + unsigned int result=(unsigned int)GPR.read(ra)/(unsigned int)GPR.read(rb); + + /* Note: XER_OV_SO_update before CR0_update */ + divwu_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb)); + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction eqv behavior method. +void ac_behavior( eqv ) +{ + dbg_printf(" eqv r%d, r%d, r%d\n\n",ra,rs,rb); + + GPR.write(ra,~(GPR.read(rs)^GPR.read(rb))); +}; + +//!Instruction eqv_ behavior method. +void ac_behavior( eqv_ ) +{ + dbg_printf(" eqv. r%d, r%d, r%d\n\n",ra,rs,rb); + + GPR.write(ra,~(GPR.read(rs)^GPR.read(rb))); + + CR0_update(CR, XER, GPR.read(ra)); +}; + +//!Instruction extsb behavior method. +void ac_behavior( extsb ) +{ + dbg_printf(" extsb r%d, r%d\n\n",ra,rs); + + GPR.write(ra,(char)(GPR.read(rs))); + +}; + +//!Instruction extsb_ behavior method. +void ac_behavior( extsb_ ) +{ + dbg_printf(" extsb. r%d, r%d\n\n",ra,rs); + + GPR.write(ra,(char)(GPR.read(rs))); + + CR0_update(CR, XER, GPR.read(ra)); +}; + +//!Instruction extsh behavior method. +void ac_behavior( extsh ) +{ + dbg_printf(" extsh r%d, r%d\n\n",ra,rs); + + GPR.write(ra,(short int)(GPR.read(rs))); + +}; + +//!Instruction extsh_ behavior method. +void ac_behavior( extsh_ ) +{ + dbg_printf(" extsh. r%d, r%d\n\n",ra,rs); + + GPR.write(ra,(short int)(GPR.read(rs))); + + CR0_update(CR, XER, GPR.read(ra)); + +}; + + +//!Instruction lbz behavior method. +void ac_behavior( lbz ) +{ + dbg_printf(" lbz r%d, %d(r%d)\n\n",rt,d,ra); + + int ea; + + if(ra!=0) + ea=GPR.read(ra)+(short int)d; + else + ea=(short int)d; + + GPR.write(rt,(unsigned int)DATA_PORT->read_byte(ea)); + +}; + +//!Instruction lbzu behavior method. +void ac_behavior( lbzu ) +{ + dbg_printf(" lbzu r%d, %d(r%d)\n\n",rt,d,ra); + + int ea; + + ea=GPR.read(ra)+(short int)d; + + GPR.write(ra,ea); + GPR.write(rt,(unsigned int)DATA_PORT->read_byte(ea)); + +}; + +//!Instruction lbzux behavior method. +void ac_behavior( lbzux ) +{ + dbg_printf(" lbzux r%d, r%d, r%d\n\n",rt,ra,rb); + + int ea; + + ea=GPR.read(ra)+GPR.read(rb); + + GPR.write(ra,ea); + GPR.write(rt,(unsigned int)DATA_PORT->read_byte(ea)); + +}; + +//!Instruction lbzx behavior method. +void ac_behavior( lbzx ) +{ + dbg_printf(" lbzx r%d, r%d, r%d\n\n",rt,ra,rb); + + int ea; + + if(ra!=0) + ea=GPR.read(ra)+GPR.read(rb); + else + ea=GPR.read(rb); + + GPR.write(rt,(unsigned int)DATA_PORT->read_byte(ea)); + +}; + +//!Instruction lha behavior method. +void ac_behavior( lha ) +{ + dbg_printf(" lha r%d, %d(r%d)\n\n",rt,d,ra); + + int ea; + + if(ra!=0) + ea=GPR.read(ra)+(short int)d; + else + ea=(short int)d; + + GPR.write(rt,(short int)DATA_PORT->read_half(ea)); + +}; + +//!Instruction lhau behavior method. +void ac_behavior( lhau ) +{ + dbg_printf(" lhau r%d, %d(r%d)\n\n",rt,d,ra); + + int ea=GPR.read(ra)+(short int)d; + + GPR.write(ra,ea); + GPR.write(rt,(short int)DATA_PORT->read_half(ea)); + +}; + +//!Instruction lhaux behavior method. +void ac_behavior( lhaux ) +{ + dbg_printf(" lhaux r%d, r%d, r%d\n\n",rt,ra,rb); + + int ea=GPR.read(ra)+GPR.read(rb); + + GPR.write(ra,ea); + GPR.write(rt,(short int)DATA_PORT->read_half(ea)); + +}; + +//!Instruction lhax behavior method. +void ac_behavior( lhax ) +{ + dbg_printf(" lhax r%d, r%d, r%d\n\n",rt,ra,rb); + + int ea; + + if(ra !=0) + ea=GPR.read(ra)+GPR.read(rb); + else + ea=GPR.read(rb); + + GPR.write(rt,(short int)DATA_PORT->read_half(ea)); + +}; + +//!Instruction lhbrx behavior method. +void ac_behavior( lhbrx ) +{ + dbg_printf(" lhbrx r%d, r%d, r%d\n\n",rt,ra,rb); + + int ea; + + if(ra !=0) + ea=GPR.read(ra)+GPR.read(rb); + else + ea=GPR.read(rb); + + GPR.write(rt,(((int)(DATA_PORT->read_byte(ea+1)) & 0x000000FF)<<8) | ((int)(DATA_PORT->read_byte(ea)) & 0x000000FF)); + +}; + +//!Instruction lhz behavior method. +void ac_behavior( lhz ) +{ + dbg_printf(" lhz r%d, %d(r%d)\n\n",rt,d,ra); + + int ea; + + if(ra !=0) + ea=GPR.read(ra)+(short int)d; + else + ea=(short int)d; + + GPR.write(rt,(unsigned short int)DATA_PORT->read_half(ea)); + +}; + +//!Instruction lhzu behavior method. +void ac_behavior( lhzu ) +{ + dbg_printf(" lhzu r%d, %d(%d)\n\n",rt,d,ra); + + int ea=GPR.read(ra)+(short int)d; + + GPR.write(ra,ea); + GPR.write(rt,(unsigned short int)DATA_PORT->read_half(ea)); + +}; + +//!Instruction lhzux behavior method. +void ac_behavior( lhzux ) +{ + dbg_printf(" lhzux r%d, r%d, r%d\n\n",rt,ra,rb); + + int ea=GPR.read(ra)+GPR.read(rb); + + GPR.write(ra,ea); + GPR.write(rt,(unsigned short int)DATA_PORT->read_half(ea)); + +}; + +//!Instruction lhzx behavior method. +void ac_behavior( lhzx ) +{ + dbg_printf(" lhzx r%d, r%d, r%d\n\n",rt,ra,rb); + + int ea; + + if(ra !=0) + ea=GPR.read(ra)+GPR.read(rb); + else + ea=GPR.read(rb); + + GPR.write(rt,(unsigned short int)DATA_PORT->read_half(ea)); + +}; + +//!Instruction lmw behavior method. +void ac_behavior( lmw ) +{ + dbg_printf(" lmw r%d, %d(r%d)\n\n",rt,d,ra); + + int ea; + unsigned int r; + + if(ra !=0) + ea=GPR.read(ra)+(short int)d; + else + ea=(short int)d; + + r=rt; + + while(r<=31) { + if((r!=ra)||(r==31)) + GPR.write(r,DATA_PORT->read(ea)); + r=r+1; + ea=ea+4; + } + +}; + +//!Instruction lswi behavior method. +void ac_behavior( lswi ) +{ + dbg_printf(" lswi r%d, r%d, %d\n\n",rt,ra,nb); + + int ea; + unsigned int cnt,n; + unsigned int rfinal,r; + unsigned int i,masc; + + if(ra!=0) + ea=GPR.read(ra); + else + ea=0; + + if(nb==0) + cnt=32; + else + cnt=nb; + + n=cnt; + rfinal=((rt + ceil(cnt,4) - 1) % 32); + r=rt-1; + i=0; + + while(n>0) { + if(i==0) { + r=r+1; + if(r==32) + r=0; + if((r!=ra)||(r==rfinal)) + GPR.write(r,0); + } + if((r!=ra)||(r==rfinal)) { + masc=0xFF000000>>i; + masc=~masc; + GPR.write(r,(GPR.read(r) & masc)); + GPR.write(r,(((unsigned int)DATA_PORT->read_byte(ea)) << (24-i)) | GPR.read(r)); + } + i=i+8; + if(i==32) + i=0; + ea=ea+1; + n=n-1; + } + +}; + +//!Instruction lswx behavior method. +void ac_behavior( lswx ) +{ + dbg_printf(" lswx r%d, r%d, r%d\n\n",rt,ra,rb); + + int ea; + unsigned int cnt,n; + unsigned int rfinal,r; + unsigned int i,masc; + + if(ra!=0) + ea=GPR.read(ra)+GPR.read(rb); + else + ea=GPR.read(rb); + + cnt=XER_TBC_read(XER); + n=cnt; + rfinal=((rt + ceil(cnt,4) - 1) % 32); + r=rt-1; + i=0; + + while(n>0) { + if(i==0) { + r=r+1; + if(r==32) + r=0; + if(((r!=ra) && (r!=rb)) || (r==rfinal)) + GPR.write(r,0); + } + if(((r!=ra) && (r!=rb)) || (r==rfinal)) { + masc=0xFF000000>>i; + masc=~masc; + GPR.write(r,(GPR.read(r) & masc)); + GPR.write(r,(((unsigned int)DATA_PORT->read_byte(ea)) << (24-i)) | GPR.read(r)); + } + i=i+8; + if(i==32) + i=0; + ea=ea+1; + n=n-1; + } + +}; + + +//!Instruction lwbrx behavior method. +void ac_behavior( lwbrx ) +{ + dbg_printf(" lwbrx r%d, r%d, r%d\n\n",rt,ra,rb); + + int ea; + + if(ra!=0) + ea=GPR.read(ra)+GPR.read(rb); + else + ea=GPR.read(rb); + + GPR.write(rt,(((unsigned int)DATA_PORT->read_byte(ea+3) & 0x000000FF) << 24) | + (((unsigned int)DATA_PORT->read_byte(ea+2) & 0x000000FF) << 16) | + (((unsigned int)DATA_PORT->read_byte(ea+1) & 0x000000FF) << 8) | + ((unsigned int)DATA_PORT->read_byte(ea) & 0x000000FF)); + +}; + +//!Instruction lwz behavior method. +void ac_behavior( lwz ) +{ + dbg_printf(" lwz r%d, %d(r%d)\n\n",rt,d,ra); + + int ea; + + if(ra !=0) + ea=GPR.read(ra)+(short int)d; + else + ea=(short int)d; + + GPR.write(rt,DATA_PORT->read(ea)); + +}; + +//!Instruction lwzu behavior method. +void ac_behavior( lwzu ) +{ + dbg_printf(" lwzu r%d, %d(r%d)\n\n",rt,d,ra); + + int ea=GPR.read(ra)+(short int)d; + + GPR.write(ra,ea); + GPR.write(rt,DATA_PORT->read(ea)); + +}; + +//!Instruction lwzux behavior method. +void ac_behavior( lwzux ) +{ + dbg_printf(" lwzux r%d, r%d, r%d\n\n",rt,ra,rb); + + int ea=GPR.read(ra)+GPR.read(rb); + + GPR.write(ra,ea); + GPR.write(rt,DATA_PORT->read(ea)); + +}; + +//!Instruction lwzx behavior method. +void ac_behavior( lwzx ) +{ + dbg_printf(" lwzx %d, %d, %d\n\n",rt,ra,rb); + + int ea; + + if(ra !=0) + ea=GPR.read(ra)+GPR.read(rb); + else + ea=GPR.read(rb); + + GPR.write(rt,DATA_PORT->read(ea)); + +}; + +//!Instruction mcrf behavior method. +void ac_behavior( mcrf ) +{ + dbg_printf(" mcrf %d, %d\n\n",bf,bfa); + + unsigned int m=bfa; + unsigned int n=bf; + unsigned int tmp,i; + unsigned int masc; + /* n <- m */ + + /* Clean all bits except m-bits in tmp */ + masc=0xF0000000; + for(i=0 ; i>4; + tmp=CR.read(); + tmp=tmp & masc; + + /* Put m-bits in n position */ + if(nm) /* Else nothing */ + for(i=0 ; i < n-m ; i++) + tmp=tmp>>4; + + /* Clean all bits of n-bits and make an or with tmp */ + masc=0xF0000000; + for(i=0 ; i>4; + masc=~masc; + CR.write((CR.read() & masc)|tmp); + +}; + +//!Instruction mcrxr behavior method. +void ac_behavior( mcrxr ) +{ + dbg_printf(" mcrxr %d\n\n",bf); + + unsigned int n=bf; + unsigned int i; + unsigned int tmp=0x00; + + /* Calculate tmp bits by XER */ + if(XER_SO_read(XER)) + tmp=tmp | 0x80000000; + if(XER_OV_read(XER)) + tmp=tmp | 0x40000000; + if(XER_CA_read(XER)) + tmp=tmp | 0x20000000; + + /* Move altered bits to correct CR field */ + for(i=0 ; i>4; + CR.write(tmp); + + /* Clean XER bits */ + XER.write(XER.read() & 0xBFFFFFFF); /* Write 0 to bit 1 OV */ + XER.write(XER.read() & 0x7FFFFFFF); /* Write 0 to bit 0 SO */ + XER.write(XER.read() & 0xDFFFFFFF); /* Write 0 to bit 2 CA */ +}; + +//!Instruction mfcr behavior method. +void ac_behavior( mfcr ) +{ + dbg_printf(" mfcr r%d\n\n",rt); + GPR.write(rt,CR.read()); + +}; + +//!Instruction mfspr behavior method. +void ac_behavior( mfspr ) +{ + /* This instruction is a fix, other implementations can be better */ + dbg_printf(" mfspr r%d,%d\n\n",rt,sprf); + unsigned int spvalue=sprf; + spvalue=((spvalue>>5) & 0x0000001f ) | + ((spvalue<<5) & 0x000003e0 ); + + + switch(spvalue) { + + /* LR */ + case 0x008: + GPR.write(rt,LR.read()); + break; + + /* CTR */ + case 0x009: + GPR.write(rt,CTR.read()); + break; + + /* USPRG0 */ + case 0x100: + GPR.write(rt,USPRG0.read()); + break; + + /* SPRG4 */ + case 0x104: + GPR.write(rt,SPRG4.read()); + break; + + /* SPRG5 */ + case 0x105: + GPR.write(rt,SPRG5.read()); + break; + + /* SPRG6 */ + case 0x106: + GPR.write(rt,SPRG6.read()); + break; + + /* SPRG7 */ + case 0x107: + GPR.write(rt,SPRG7.read()); + break; + + + + /* Not implemented yet! */ + default: + dbg_printf("\nERROR!\n"); + exit(-1); + break; + + + } +}; + + +//!Instruction mtcrf behavior method. +void ac_behavior( mtcrf ) { + dbg_printf(" mtcrf %d, r%d\n\n",xfm,rs); + + unsigned int tmpop,tmpmask; + unsigned int mask; + unsigned int i; + unsigned int crm=xfm; + + tmpmask=0xF0000000; + tmpop=0x80; + mask=0; + for(i=0;i<8;i++) { + if(crm & tmpop) + mask=mask | tmpmask; + tmpmask=tmpmask>>4; + tmpop=tmpop>>1; + } + + CR.write((GPR.read(rs) & mask) | (CR.read() & ~mask)); + +}; + + + +//!Instruction mtspr behavior method. +void ac_behavior( mtspr ) +{ + /* This instruction is a fix, other implementations can be better */ + dbg_printf(" mtspr %d,r%d\n\n",sprf,rs); + unsigned int spvalue=sprf; + spvalue=((spvalue>>5) & 0x0000001f ) | + ((spvalue<<5) & 0x000003e0 ); + + switch(spvalue) { + + /* LR */ + case 0x008: + LR.write(GPR.read(rs)); + break; + + /* CTR */ + case 0x009: + CTR.write(GPR.read(rs)); + break; + + /* USPRG0 */ + case 0x100: + USPRG0.write(GPR.read(rs)); + break; + + /* SPRG4 */ + case 0x104: + SPRG4.write(GPR.read(rs)); + break; + + /* SPRG5 */ + case 0x105: + SPRG5.write(GPR.read(rs)); + break; + + /* SPRG6 */ + case 0x106: + SPRG6.write(GPR.read(rs)); + break; + + /* SPRG7 */ + case 0x107: + SPRG7.write(GPR.read(rs)); + break; + + + /* Not implemented yet! */ + default: + dbg_printf("\nERROR!\n"); + exit(-1); + break; + + } + + +}; + + +//!Instruction mulhw behavior method. +void ac_behavior( mulhw ) +{ + dbg_printf(" mulhw r%d, r%d, r%d\n\n",rt,ra,rb); + + int high; + long long int prod = + (long long int)(int)GPR.read(ra)*(long long int)(int)GPR.read(rb); + + unsigned long long int shprod=prod; + shprod=shprod>>32; + high=shprod; + + GPR.write(rt,high); + +}; + + +//!Instruction mulhw_ behavior method. +void ac_behavior( mulhw_ ) +{ + dbg_printf(" mulhw. r%d, r%d, r%d\n\n",rt,ra,rb); + + int high; + long long int prod = + (long long int)(int)GPR.read(ra)*(long long int)(int)GPR.read(rb); + + unsigned long long int shprod=prod; + shprod=shprod>>32; + high=shprod; + + GPR.write(rt,high); + CR0_update(CR, XER, high); +}; + +//!Instruction mulhwu behavior method. +void ac_behavior( mulhwu ) +{ + dbg_printf(" mulhwu r%d, r%d, r%d\n\n",rt,ra,rb); + + unsigned int high; + unsigned long long int prod = + (unsigned long long int)(unsigned int)GPR.read(ra)* + (unsigned long long int)(unsigned int)GPR.read(rb); + + prod=prod>>32; + high=prod; + + GPR.write(rt,high); + +}; + +//!Instruction mulhwu_ behavior method. +void ac_behavior( mulhwu_ ) +{ + dbg_printf(" mulhwu. r%d, r%d, r%d\n\n",rt,ra,rb); + + unsigned int high; + unsigned long long int prod = + (unsigned long long int)(unsigned int)GPR.read(ra)* + (unsigned long long int)(unsigned int)GPR.read(rb); + + prod=prod>>32; + high=prod; + + GPR.write(rt,high); + CR0_update(CR, XER, high); +}; + +//!Instruction mullhw behavior method. +void ac_behavior( mullhw ) +{ + dbg_printf(" mullhw r%d, r%d, r%d\n\n",rt,ra,rb); + + int prod = + (int)(short int)(GPR.read(ra) & 0x0000FFFF)* + (int)(short int)(GPR.read(rb) & 0x0000FFFF); + + GPR.write(rt,prod); + +}; + +//!Instruction mullhw_ behavior method. +void ac_behavior( mullhw_ ) +{ + dbg_printf(" mullhw. r%d, r%d, r%d\n\n",rt,ra,rb); + + int prod = + (int)(short int)(GPR.read(ra) & 0x0000FFFF)* + (int)(short int)(GPR.read(rb) & 0x0000FFFF); + + GPR.write(rt,prod); + CR0_update(CR, XER, prod); +}; + +//!Instruction mullhwu behavior method. +void ac_behavior( mullhwu ) +{ + dbg_printf(" mullhwu r%d, r%d, r%d\n\n",rt,ra,rb); + + unsigned int prod = + (unsigned int)(unsigned short int)(GPR.read(ra) & 0x0000FFFF)* + (unsigned int)(unsigned short int)(GPR.read(rb) & 0x0000FFFF); + + GPR.write(rt,prod); + +}; + +//!Instruction mullhwu_ behavior method. +void ac_behavior( mullhwu_ ) +{ + dbg_printf(" mullhwu. r%d, r%d, r%d\n\n",rt,ra,rb); + + unsigned int prod = + (unsigned int)(unsigned short int)(GPR.read(ra) & 0x0000FFFF)* + (unsigned int)(unsigned short int)(GPR.read(rb) & 0x0000FFFF); + + GPR.write(rt,prod); + CR0_update(CR, XER, prod); +}; + +//!Instruction mulli behavior method. +void ac_behavior( mulli ) +{ + dbg_printf(" mulli r%d, r%d, %d\n\n",rt,ra,d); + + long long int prod = + (long long int)(int)GPR.read(ra) * (long long int)(short int)(d); + + int low; + low=prod; + + GPR.write(rt,low); + +}; + +//!Instruction mullw behavior method. +void ac_behavior( mullw ) +{ + dbg_printf(" mullw r%d, r%d, r%d\n\n",rt,ra,rb); + + int low; + long long int prod = + (long long int)(int)GPR.read(ra)*(long long int)(int)GPR.read(rb); + + low=prod; + + GPR.write(rt,low); + +}; + +//!Instruction mullw_ behavior method. +void ac_behavior( mullw_ ) +{ + dbg_printf(" mullw. r%d, r%d, r%d\n\n",rt,ra,rb); + + int low; + long long int prod = + (long long int)(int)GPR.read(ra)*(long long int)(int)GPR.read(rb); + + low=prod; + + GPR.write(rt,low); + CR0_update(CR, XER, low); + +}; + +//!Instruction mullwo behavior method. +void ac_behavior( mullwo ) +{ + dbg_printf(" mullwo r%d, r%d, r%d\n\n",rt,ra,rb); + + int low; + long long int prod = + (long long int)(int)GPR.read(ra)*(long long int)(int)GPR.read(rb); + + low=prod; + + if(prod != (long long int)(int)low) { + XER.write(XER.read() | 0x40000000); /* Write 1 to bit 1 OV */ + XER.write(XER.read() | 0x80000000); /* Write 1 to bit 0 SO */ + } + else + XER.write(XER.read() & 0xBFFFFFFF); /* Write 0 to bit 1 OV */ + + + GPR.write(rt,low); + +}; + +//!Instruction mullw behavior method. +void ac_behavior( mullwo_ ) +{ + dbg_printf(" mullwo_ r%d, r%d, r%d\n\n",rt,ra,rb); + + int low; + long long int prod = + (long long int)(int)GPR.read(ra)*(long long int)(int)GPR.read(rb); + + low=prod; + + GPR.write(rt,low); + + if(prod != (long long int)(int)low) { + XER.write(XER.read() | 0x40000000); /* Write 1 to bit 1 OV */ + XER.write(XER.read() | 0x80000000); /* Write 1 to bit 0 SO */ + } + else + XER.write(XER.read() & 0xBFFFFFFF); /* Write 0 to bit 1 OV */ + + CR0_update(CR, XER, low); +}; + +//!Instruction nand behavior method. +void ac_behavior( nand ) +{ + dbg_printf(" nand r%d, r%d, r%d\n\n",ra,rs,rb); + GPR.write(ra,~(GPR.read(rs) & GPR.read(rb))); + +}; + +//!Instruction nand_ behavior method. +void ac_behavior( nand_ ) +{ + dbg_printf(" nand. r%d, r%d, r%d\n\n",ra,rs,rb); + int result=~(GPR.read(rs) & GPR.read(rb)); + + GPR.write(ra,result); + CR0_update(CR, XER, result); + +}; + +//!Instruction neg behavior method. +void ac_behavior( neg ) +{ + dbg_printf(" neg r%d, r%d\n\n",rt,ra); + + GPR.write(rt,~(GPR.read(ra))+1); +}; + +//!Instruction neg_ behavior method. +void ac_behavior( neg_ ) +{ + dbg_printf(" neg. r%d, r%d\n\n",rt,ra); + + int result=~(GPR.read(ra))+1; + GPR.write(rt,result); + CR0_update(CR, XER, result); +}; + +//!Instruction nego behavior method. +void ac_behavior( nego ) +{ + dbg_printf(" nego r%d, r%d\n\n",rt,ra); + + long long int longresult=~((unsigned int)GPR.read(ra))+1; + int result=~(GPR.read(ra))+1; + + if(longresult != (long long int)result) { + XER.write(XER.read() | 0x40000000); /* Write 1 to bit 1 OV */ + XER.write(XER.read() | 0x80000000); /* Write 1 to bit 0 SO */ + } + else + XER.write(XER.read() & 0xBFFFFFFF); /* Write 0 to bit 1 OV */ + + GPR.write(rt,result); +}; + +//!Instruction nego_ behavior method. +void ac_behavior( nego_ ) +{ + dbg_printf(" nego. r%d, r%d\n\n",rt,ra); + + long long int longresult=~((unsigned int)GPR.read(ra))+1; + int result=~(GPR.read(ra))+1; + + if(longresult != (long long int)result) { + XER.write(XER.read() | 0x40000000); /* Write 1 to bit 1 OV */ + XER.write(XER.read() | 0x80000000); /* Write 1 to bit 0 SO */ + } + else + XER.write(XER.read() & 0xBFFFFFFF); /* Write 0 to bit 1 OV */ + + GPR.write(rt,result); + CR0_update(CR, XER, result); + +}; + +//!Instruction nor behavior method. +void ac_behavior( nor ) +{ + dbg_printf(" nor r%d, r%d, r%d\n\n",ra,rs,rb); + GPR.write(ra,~(GPR.read(rs) | GPR.read(rb))); + +}; + +//!Instruction nor_ behavior method. +void ac_behavior( nor_ ) +{ + dbg_printf(" nor. r%d, r%d, r%d\n\n",ra,rs,rb); + int result=~(GPR.read(rs) | GPR.read(rb)); + + GPR.write(ra,result); + CR0_update(CR, XER, result); + +}; + +//!Instruction ore behavior method. +void ac_behavior( ore ) +{ + dbg_printf(" or r%d, r%d, r%d\n\n",ra,rs,rb); + GPR.write(ra,GPR.read(rs) | GPR.read(rb)); + +}; + +//!Instruction ore_ behavior method. +void ac_behavior( ore_ ) +{ + dbg_printf(" or. r%d, r%d, r%d\n\n",ra,rs,rb); + int result=GPR.read(rs) | GPR.read(rb); + + GPR.write(ra,result); + CR0_update(CR, XER, result); + +}; + +//!Instruction orc behavior method. +void ac_behavior( orc ) +{ + dbg_printf(" orc r%d, r%d, r%d\n\n",ra,rs,rb); + GPR.write(ra,GPR.read(rs) | ~GPR.read(rb)); + +}; + +//!Instruction orc_ behavior method. +void ac_behavior( orc_ ) +{ + dbg_printf(" orc. r%d, r%d, r%d\n\n",ra,rs,rb); + int result=GPR.read(rs) | ~GPR.read(rb); + + GPR.write(ra,result); + CR0_update(CR, XER, result); + +}; + +//!Instruction ori behavior method. +void ac_behavior( ori ) +{ + dbg_printf(" ori r%d, r%d, %d\n\n",ra,rs,ui); + + GPR.write(ra,GPR.read(rs) | (int)((unsigned short int)ui)); +}; + +//!Instruction oris behavior method. +void ac_behavior( oris ) +{ + dbg_printf(" oris r%d, r%d, r%d\n\n",ra,rs,ui); + + GPR.write(ra,GPR.read(rs) | (((int)((unsigned short int)ui)) << 16)); +}; + +//!Instruction rlwimi behavior method. +void ac_behavior( rlwimi ) +{ + dbg_printf(" rlwimi r%d, r%d, %d, %d, %d\n\n",ra,rs,sh,mb,me); + + unsigned int r=rotl(GPR.read(rs),sh); + unsigned int m=mask32rlw(mb,me); + + GPR.write(ra,(r & m) | (GPR.read(ra) & ~m)); + +}; + +//!Instruction rlwimi_ behavior method. +void ac_behavior( rlwimi_ ) +{ + dbg_printf(" rlwimi. r%d, r%d, %d, %d, %d\n\n",ra,rs,sh,mb,me); + + unsigned int r=rotl(GPR.read(rs),sh); + unsigned int m=mask32rlw(mb,me); + + GPR.write(ra,(r & m) | (GPR.read(ra) & ~m)); + + CR0_update(CR, XER, GPR.read(ra)); + +}; + +//!Instruction rlwinm behavior method. +void ac_behavior( rlwinm ) +{ + dbg_printf(" rlwinm r%d, r%d, %d, %d, %d\n\n",ra,rs,sh,mb,me); + + unsigned int r=rotl(GPR.read(rs),sh); + unsigned int m=mask32rlw(mb,me); + + GPR.write(ra,(r & m)); + +}; + +//!Instruction rlwinm_ behavior method. +void ac_behavior( rlwinm_ ) +{ + dbg_printf(" rlwinm. r%d, r%d, %d, %d, %d\n\n",ra,rs,sh,mb,me); + + unsigned int r=rotl(GPR.read(rs),sh); + unsigned int m=mask32rlw(mb,me); + + GPR.write(ra,(r & m)); + + CR0_update(CR, XER, GPR.read(ra)); + +}; + +//!Instruction rlwnm behavior method. +void ac_behavior( rlwnm ) +{ + dbg_printf(" rlwnm r%d, r%d, %d, %d, %d\n\n",ra,rs,rb,mb,me); + + unsigned int r=rotl(GPR.read(rs),(GPR.read(rb) | 0x0000001F)); + unsigned int m=mask32rlw(mb,me); + + GPR.write(ra,(r & m)); + +}; + +//!Instruction rlwnm_ behavior method. +void ac_behavior( rlwnm_ ) +{ + dbg_printf(" rlwnm. r%d, r%d, %d, %d, %d\n\n",ra,rs,rb,mb,me); + + unsigned int r=rotl(GPR.read(rs),(GPR.read(rb) | 0x0000001F)); + unsigned int m=mask32rlw(mb,me); + + GPR.write(ra,(r & m)); + + CR0_update(CR, XER, GPR.read(ra)); + +}; + +//!Instruction sc behavior method. +/* The registers used in this intruction may be defined better */ +void ac_behavior( sc ) +{ + dbg_printf(" sc\n\n"); + + SRR1.write(MSR.read()); /* It uses a function to join MSR fields */ + + /* Write WE, EE, PR, DR and IR as 0 in MSR */ + MSR.write(MSR.read() | 0xFFFB3FCF); + + SRR0.write((ac_pc-4)+4); /* Only to understand pre-increment */ + + ac_pc=((EVPR.read() & 0xFFFF0000) | 0x00000C00); + +}; + +//!Instruction slw behavior method. +void ac_behavior( slw ) +{ + dbg_printf(" slw r%d, r%d, r%d\n\n",ra,rs,rb); + + unsigned int n=(GPR.read(rb) & 0x0000001F); + unsigned int r=rotl(GPR.read(rs),n); + unsigned int m; + + if((GPR.read(rb) & 0x00000020)==0x00) /* Check bit 26 */ + m=mask32rlw(0,31-n); + else + m=0; + + GPR.write(ra,r & m); + +}; + +//!Instruction slw_ behavior method. +void ac_behavior( slw_ ) +{ + dbg_printf(" slw. r%d, r%d, r%d\n\n",ra,rs,rb); + + unsigned int n=(GPR.read(rb) & 0x0000001F); + unsigned int r=rotl(GPR.read(rs),n); + unsigned int m; + + if((GPR.read(rb) & 0x00000020)==0x00) /* Check bit 26 */ + m=mask32rlw(0,31-n); + else + m=0; + + int result=r & m; + GPR.write(ra,result); + + CR0_update(CR, XER, result); + +}; + +//!Instruction sraw behavior method. +void ac_behavior( sraw ) +{ + dbg_printf(" sraw r%d, r%d, r%d\n\n",ra,rs,rb); + + unsigned int n=(GPR.read(rb) & 0x0000001F); + unsigned int r=rotl(GPR.read(rs),32-n); + unsigned int m; + unsigned int s; + + if((GPR.read(rb) & 0x00000020)==0x00) /* Check bit 26 */ + m=mask32rlw(n,31); + else + m=0; + + s=(GPR.read(rs) & 0x80000000); + if(s!=0) + s=0xFFFFFFFF; + + int result=(r & m) | (s & ~m); + + /* Write ra */ + GPR.write(ra,result); + + /* Update XER CA */ + if(s && ((r & ~m)!=0)) + XER.write(XER.read() | 0x20000000); /* Write 1 to bit 2 CA */ + else + XER.write(XER.read() & 0xDFFFFFFF); /* Write 0 to bit 2 CA */ + +}; + +//!Instruction sraw_ behavior method. +void ac_behavior( sraw_ ) +{ + dbg_printf(" sraw. r%d, r%d, r%d\n\n",ra,rs,rb); + + unsigned int n=(GPR.read(rb) & 0x0000001F); + unsigned int r=rotl(GPR.read(rs),32-n); + unsigned int m; + unsigned int s; + + if((GPR.read(rb) & 0x00000020)==0x00) /* Check bit 26 */ + m=mask32rlw(n,31); + else + m=0; + + s=(GPR.read(rs) & 0x80000000); + if(s!=0) + s=0xFFFFFFFF; + + /* Write ra */ + int result=(r & m) | (s & ~m); + + GPR.write(ra,result); + + /* Update XER CA */ + if(s && ((r & ~m)!=0)) + XER.write(XER.read() | 0x20000000); /* Write 1 to bit 2 CA */ + else + XER.write(XER.read() & 0xDFFFFFFF); /* Write 0 to bit 2 CA */ + + /* Update CR register */ + CR0_update(CR, XER, result); + +}; + +//!Instruction srawi behavior method. +void ac_behavior( srawi ) +{ + dbg_printf(" srawi r%d, r%d, %d\n\n",ra,rs,sh); + + unsigned int n=sh; + unsigned int r=rotl(GPR.read(rs),32-n); + unsigned int m=mask32rlw(n,31); + unsigned int s=(GPR.read(rs) & 0x80000000); + + if(s!=0) + s=0xFFFFFFFF; + + int result=(r & m) | (s & ~m); + + GPR.write(ra,result); + + /* Update XER CA */ + if(s && ((r & ~m)!=0)) + XER.write(XER.read() | 0x20000000); /* Write 1 to bit 2 CA */ + else + XER.write(XER.read() & 0xDFFFFFFF); /* Write 0 to bit 2 CA */ + +}; + +//!Instruction srawi_ behavior method. +void ac_behavior( srawi_ ) +{ + dbg_printf(" srawi. r%d, r%d, %d\n\n",ra,rs,sh); + + unsigned int n=sh; + unsigned int r=rotl(GPR.read(rs),32-n);; + unsigned int m=mask32rlw(n,31); + unsigned int s=(GPR.read(rs) & 0x80000000); + if(s!=0) + s=0xFFFFFFFF; + + /* Write ra */ + int result=(r & m) | (s & ~m); + GPR.write(ra,result); + + /* Update XER CA */ + if(s && ((r & ~m)!=0)) + XER.write(XER.read() | 0x20000000); /* Write 1 to bit 2 CA */ + else + XER.write(XER.read() & 0xDFFFFFFF); /* Write 0 to bit 2 CA */ + + /* Update CR register */ + CR0_update(CR, XER, result); +}; + +//!Instruction srw behavior method. +void ac_behavior( srw ) +{ + dbg_printf(" srw r%d, r%d, r%d\n\n",ra,rs,rb); + + unsigned int n=(GPR.read(rb) & 0x0000001F); + unsigned int r=rotl(GPR.read(rs),32-n); + unsigned int m; + + if((GPR.read(rb) & 0x00000020)==0x00) /* Check bit 26 */ + m=mask32rlw(n,31); + else + m=0; + + GPR.write(ra,r & m); + +}; + +//!Instruction srw_ behavior method. +void ac_behavior( srw_ ) +{ + dbg_printf(" srw. r%d, r%d, r%d\n\n",ra,rs,rb); + + unsigned int n=(GPR.read(rb) & 0x0000001F); + unsigned int r=rotl(GPR.read(rs),32-n); + unsigned int m; + + if((GPR.read(rb) & 0x00000020)==0x00) /* Check bit 26 */ + m=mask32rlw(n,31); + else + m=0; + + int result=r & m; + + GPR.write(ra,result); + + CR0_update(CR, XER, result); + +}; + +//!Instruction stb behavior method. +void ac_behavior( stb ) +{ + dbg_printf(" stb r%d, %d(r%d)\n\n",rs,d,ra); + + int ea; + + if(ra!=0) + ea=GPR.read(ra)+(short int)d; + else + ea=(short int)d; + + DATA_PORT->write_byte(ea,(unsigned char)GPR.read(rs)); + +}; + +//!Instruction stbu behavior method. +void ac_behavior( stbu ) +{ + dbg_printf(" stbu r%d, %d(r%d)\n\n",rs,d,ra); + + int ea=GPR.read(ra)+(short int)d; + + DATA_PORT->write_byte(ea,(unsigned char)GPR.read(rs)); + GPR.write(ra,ea); + +}; + +//!Instruction stbux behavior method. +void ac_behavior( stbux ) +{ + dbg_printf(" stbux r%d, r%d, r%d\n\n",rs,ra,rb); + + int ea=GPR.read(ra)+GPR.read(rb); + + DATA_PORT->write_byte(ea,(unsigned char)GPR.read(rs)); + GPR.write(ra,ea); + +}; + +//!Instruction stbx behavior method. +void ac_behavior( stbx ) +{ + dbg_printf(" stbx r%d, r%d, r%d\n\n",rs,ra,rb); + + int ea; + + if(ra!=0) + ea=GPR.read(ra)+GPR.read(rb); + else + ea=GPR.read(rb); + + DATA_PORT->write_byte(ea,(unsigned char)GPR.read(rs)); + +}; + +//!Instruction sth behavior method. +void ac_behavior( sth ) +{ + dbg_printf(" sth r%d, %d(r%d)\n\n",rs,d,ra); + + int ea; + + if(ra!=0) + ea=GPR.read(ra)+(short int)d; + else + ea=(short int)d; + + DATA_PORT->write_half(ea,(unsigned short int)GPR.read(rs)); + +}; + +//!Instruction sthbrx behavior method. +void ac_behavior( sthbrx ) +{ + dbg_printf(" sthbrx r%d, r%d, r%d\n\n",rs,ra,rb); + + int ea; + + if(ra!=0) + ea=GPR.read(ra)+GPR.read(rb); + else + ea=GPR.read(rb); + + DATA_PORT->write_half(ea,(unsigned short int) + ( ((GPR.read(rs) & 0x000000FF) << 8) | + ((GPR.read(rs) & 0x0000FF00) >> 8) )); + +} + +//!Instruction sthu behavior method. +void ac_behavior( sthu ) +{ + dbg_printf(" sthu r%d, %d(r%d)\n\n",rs,d,ra); + + int ea=GPR.read(ra)+(short int)d; + + DATA_PORT->write_half(ea,(unsigned short int)GPR.read(rs)); + GPR.write(ra,ea); + +}; + +//!Instruction sthux behavior method. +void ac_behavior( sthux ) +{ + dbg_printf("sthux r%d, r%d, r%d\n\n",rs,ra,rb); + + int ea=GPR.read(ra)+GPR.read(rb); + + DATA_PORT->write_half(ea,(unsigned short int)GPR.read(rs)); + GPR.write(ra,ea); + +}; + +//!Instruction sthx behavior method. +void ac_behavior( sthx ) +{ + dbg_printf(" shhx r%d, r%d, r%d\n\n",rs,ra,rb); + + int ea; + + if(ra!=0) + ea=GPR.read(ra)+GPR.read(rb); + else + ea=GPR.read(rb); + + DATA_PORT->write_half(ea,(unsigned short int)GPR.read(rs)); + +}; + +//!Instruction stmw behavior method. +void ac_behavior( stmw ) +{ + dbg_printf(" stmw r%d, %d(r%d)\n\n",rs,d,ra); + + int ea; + unsigned int r; + + if(ra!=0) + ea=GPR.read(ra)+(short int)d; + else + ea=(short int)d; + + r=rs; + + while(r<=31) { + DATA_PORT->write(ea,GPR.read(r)); + r+=1; + ea+=4; + } + +}; + +//!Instruction stswi behavior method. +void ac_behavior( stswi ) +{ + dbg_printf(" stswi r%d, r%d, %d\n\n",rs,ra,nb); + + int ea; + unsigned int n; + unsigned int r; + unsigned int i,masc; + + if(ra!=0) + ea=GPR.read(ra); + else + ea=0; + + if(nb==0) + n=32; + else + n=nb; + + r=rs-1; + i=0; + + while(n>0) { + if(i==0) + r=r+1; + if(r==32) + r=0; + masc=mask32rlw(i,i+7); + DATA_PORT->write_byte(ea,(unsigned char)((GPR.read(r) & masc) >> (24-i))); + i=i+8; + if(i==32) + i=0; + ea=ea+1; + n=n-1; + } + +}; + +//!Instruction stswx behavior method. +void ac_behavior( stswx ) +{ + dbg_printf(" stswx r%d, r%d, r%d\n\n",rs,ra,rb); + + int ea; + unsigned int n; + unsigned int r; + unsigned int i,masc; + + if(ra!=0) + ea=GPR.read(ra)+GPR.read(rb); + else + ea=GPR.read(rb); + + n=XER_TBC_read(XER); + + r=rs-1; + i=0; + + while(n>0) { + if(i==0) + r=r+1; + if(r==32) + r=0; + masc=mask32rlw(i,i+7); + DATA_PORT->write_byte(ea,(unsigned char)((GPR.read(r) & masc) >> (24-i))); + i=i+8; + if(i==32) + i=0; + ea=ea+1; + n=n-1; + } + +}; + +//!Instruction stw behavior method. +void ac_behavior( stw ) +{ + dbg_printf(" stw r%d, %d(r%d)\n\n",rs,d,ra); + + int ea; + + if(ra!=0) + ea=GPR.read(ra)+(short int)d; + else + ea=(short int)d; + + DATA_PORT->write(ea,(unsigned int)GPR.read(rs)); + +}; + +//!Instruction stwbrx behavior method. +void ac_behavior( stwbrx ) +{ + dbg_printf(" stwbrx r%d, r%d, r%d\n\n",rs,ra,rb); + + int ea; + + if(ra!=0) + ea=GPR.read(ra)+GPR.read(rb); + else + ea=GPR.read(rb); + + DATA_PORT->write(ea,(((GPR.read(rs) & 0x000000FF) << 24) | + ((GPR.read(rs) & 0x0000FF00) << 16 ) | + ((GPR.read(rs) & 0x00FF0000) << 8 ) | + (GPR.read(rs) & 0xFF000000))); + +}; + + +//!Instruction stwu behavior method. +void ac_behavior( stwu ) +{ + dbg_printf(" stwu r%d, %d(r%d)\n\n",rs,d,ra); + + int ea=GPR.read(ra)+(short int)d; + + DATA_PORT->write(ea,(unsigned int)GPR.read(rs)); + GPR.write(ra,ea); + +}; + +//!Instruction stwux behavior method. +void ac_behavior( stwux ) +{ + dbg_printf("stwux r%d, r%d, r%d\n\n",rs,ra,rb); + + int ea=GPR.read(ra)+GPR.read(rb); + + DATA_PORT->write(ea,GPR.read(rs)); + GPR.write(ra,ea); + +}; + +//!Instruction stwx behavior method. +void ac_behavior( stwx ) +{ + dbg_printf(" stwx r%d, r%d, r%d\n\n",rs,ra,rb); + + int ea; + + if(ra!=0) + ea=GPR.read(ra)+GPR.read(rb); + else + ea=GPR.read(rb); + + DATA_PORT->write(ea,(unsigned int)GPR.read(rs)); + +}; + + + + + + + +//!Instruction subf behavior method. +void ac_behavior( subf ) +{ + dbg_printf(" subf r%d, r%d, r%d\n\n",rt,ra,rb); + + GPR.write(rt,~GPR.read(ra) + GPR.read(rb) + 1); + +}; + +//!Instruction subf_ behavior method. +void ac_behavior( subf_ ) +{ + dbg_printf(" subf. r%d, r%d, r%d\n\n",rt,ra,rb); + int result=~GPR.read(ra) + GPR.read(rb) + 1; + + GPR.write(rt,result); + CR0_update(CR, XER, result); + +}; + +//!Instruction subfo behavior method. +void ac_behavior( subfo ) +{ + dbg_printf(" subfo r%d, r%d, r%d\n\n",rt,ra,rb); + int result=~GPR.read(ra) + GPR.read(rb) + 1; + + add_XER_OV_SO_update(XER, result,~GPR.read(ra),GPR.read(rb),1); + GPR.write(rt,result); +}; + +//!Instruction subfo_ behavior method. +void ac_behavior( subfo_ ) +{ + dbg_printf(" subfo. r%d, r%d, r%d\n\n",rt,ra,rb); + int result=~GPR.read(ra) + GPR.read(rb) + 1; + + /* Note: XER_OV_SO_update before CR0_update */ + add_XER_OV_SO_update(XER, result,~GPR.read(ra),GPR.read(rb),1); + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction subfc behavior method. +void ac_behavior( subfc ) +{ + dbg_printf(" subfc r%d, r%d, r%d\n\n",rt,ra,rb); + int result=~GPR.read(ra) + GPR.read(rb) + 1; + + add_XER_CA_update(XER, result,~GPR.read(ra),GPR.read(rb),1); + + GPR.write(rt,result); +}; + +//!Instruction subfc_ behavior method. +void ac_behavior( subfc_ ) +{ + dbg_printf(" subfc. r%d, r%d, r%d\n\n",rt,ra,rb); + int result=~GPR.read(ra) + GPR.read(rb) + 1; + + add_XER_CA_update(XER, result,~GPR.read(ra),GPR.read(rb),1); + + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction subfco behavior method. +void ac_behavior( subfco ) +{ + dbg_printf(" subfco r%d, r%d, r%d\n\n",rt,ra,rb); + int result=~GPR.read(ra) + GPR.read(rb) + 1; + + add_XER_CA_update(XER, result,~GPR.read(ra),GPR.read(rb),1); + + add_XER_OV_SO_update(XER, result,~GPR.read(ra),GPR.read(rb),1); + + GPR.write(rt,result); +}; + +//!Instruction subfco_ behavior method. +void ac_behavior( subfco_ ) +{ + dbg_printf(" subfco. r%d, r%d, r%d\n\n",rt,ra,rb); + int result=~GPR.read(ra) + GPR.read(rb) + 1; + + add_XER_CA_update(XER, result,~GPR.read(ra),GPR.read(rb),1); + + /* Note: XER_OV_SO_update before CR0_update */ + add_XER_OV_SO_update(XER, result,~GPR.read(ra),GPR.read(rb),1); + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction subfe behavior method. +void ac_behavior( subfe ) +{ + dbg_printf(" subfe r%d, r%d, r%d\n\n",rt,ra,rb); + + int result=~GPR.read(ra) + GPR.read(rb) + XER_CA_read(XER); + + add_XER_CA_update(XER, result,~GPR.read(ra),GPR.read(rb),XER_CA_read(XER)); + + GPR.write(rt,result); +}; + +//!Instruction subfe_ behavior method. +void ac_behavior( subfe_ ) +{ + dbg_printf(" subfe. r%d, r%d, r%d\n\n",rt,ra,rb); + + int result=~GPR.read(ra) + GPR.read(rb) + XER_CA_read(XER); + + add_XER_CA_update(XER, result,~GPR.read(ra),GPR.read(rb),XER_CA_read(XER)); + + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction subfeo behavior method. +void ac_behavior( subfeo ) +{ + dbg_printf(" subfeo r%d, r%d, r%d\n\n",rt,ra,rb); + + int result=~GPR.read(ra) + GPR.read(rb) + XER_CA_read(XER); + + add_XER_CA_update(XER, result,~GPR.read(ra),GPR.read(rb),XER_CA_read(XER)); + + add_XER_OV_SO_update(XER, result,~GPR.read(ra),GPR.read(rb),XER_CA_read(XER)); + + GPR.write(rt,result); +}; + +//!Instruction subfeo_ behavior method. +void ac_behavior( subfeo_ ) +{ + dbg_printf(" subfeo. r%d, r%d, r%d\n\n",rt,ra,rb); + + int result=~GPR.read(ra) + GPR.read(rb) + XER_CA_read(XER); + + add_XER_CA_update(XER, result,~GPR.read(ra),GPR.read(rb),XER_CA_read(XER)); + + /* Note: XER_OV_SO_update before CR0_update */ + add_XER_OV_SO_update(XER, result,~GPR.read(ra),GPR.read(rb),XER_CA_read(XER)); + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction subfic behavior method. +void ac_behavior( subfic ) +{ + dbg_printf(" subfic r%d, r%d, %d\n\n",rt,ra,d); + int ime32=d; + int result=~GPR.read(ra)+ime32+1; + + add_XER_CA_update(XER, result,~GPR.read(ra),ime32,1); + + GPR.write(rt,result); +}; + +//!Instruction subfme behavior method. +void ac_behavior( subfme ) +{ + dbg_printf(" subfme r%d, r%d\n\n",rt,ra); + int result=~GPR.read(ra)+XER_CA_read(XER)+(-1); + + add_XER_CA_update(XER, result,~GPR.read(ra),XER_CA_read(XER),-1); + + GPR.write(rt,result); +}; + +//!Instruction subfme_ behavior method. +void ac_behavior( subfme_ ) +{ + dbg_printf(" subfme. r%d, r%d\n\n",rt,ra); + int result=~GPR.read(ra)+XER_CA_read(XER)+(-1); + + add_XER_CA_update(XER, result,~GPR.read(ra),XER_CA_read(XER),-1); + + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction subfmeo behavior method. +void ac_behavior( subfmeo ) +{ + dbg_printf(" subfmeo r%d, r%d\n\n",rt,ra); + int result=~GPR.read(ra)+XER_CA_read(XER)+(-1); + + add_XER_CA_update(XER, result,~GPR.read(ra),XER_CA_read(XER),-1); + + add_XER_OV_SO_update(XER, result,~GPR.read(ra),XER_CA_read(XER),-1); + + GPR.write(rt,result); +}; + +//!Instruction subfmeo_ behavior method. +void ac_behavior( subfmeo_ ) +{ + dbg_printf(" subfmeo. r%d, r%d\n\n",rt,ra); + int result=~GPR.read(ra)+XER_CA_read(XER)+(-1); + + add_XER_CA_update(XER, result,~GPR.read(ra),XER_CA_read(XER),-1); + + /* Note: XER_OV_SO_update before CR0_update */ + add_XER_OV_SO_update(XER, result,~GPR.read(ra),XER_CA_read(XER),-1); + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction subfze behavior method. +void ac_behavior( subfze ) +{ + dbg_printf(" subfze r%d, r%d\n\n",rt,ra); + int result=~GPR.read(ra)+XER_CA_read(XER); + + add_XER_CA_update(XER, result,~GPR.read(ra),XER_CA_read(XER),0); + + GPR.write(rt,result); +}; + +//!Instruction subfze_ behavior method. +void ac_behavior( subfze_ ) +{ + dbg_printf(" subfze. r%d, r%d\n\n",rt,ra); + int result=~GPR.read(ra)+XER_CA_read(XER); + + add_XER_CA_update(XER, result,~GPR.read(ra),XER_CA_read(XER),0); + + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction subfzeo behavior method. +void ac_behavior( subfzeo ) +{ + dbg_printf(" subfzeo r%d, r%d\n\n",rt,ra); + int result=~GPR.read(ra)+XER_CA_read(XER); + + add_XER_CA_update(XER, result,~GPR.read(ra),XER_CA_read(XER),0); + + add_XER_OV_SO_update(XER, result,~GPR.read(ra),XER_CA_read(XER),0); + + GPR.write(rt,result); +}; + +//!Instruction subfzeo_ behavior method. +void ac_behavior( subfzeo_ ) +{ + dbg_printf(" subfzeo. r%d, r%d\n\n",rt,ra); + int result=~GPR.read(ra)+XER_CA_read(XER); + + add_XER_CA_update(XER, result,~GPR.read(ra),XER_CA_read(XER),0); + + /* Note: XER_OV_SO_update before CR0_update */ + add_XER_OV_SO_update(XER, result,~GPR.read(ra),XER_CA_read(XER),0); + CR0_update(CR, XER, result); + + GPR.write(rt,result); +}; + +//!Instruction xor behavior method. +void ac_behavior( xxor ) +{ + dbg_printf(" xor r%d, r%d, r%d\n\n",ra,rs,rb); + GPR.write(ra,GPR.read(rs) ^ GPR.read(rb)); + +}; + +//!Instruction xor_ behavior method. +void ac_behavior( xxor_ ) +{ + dbg_printf(" xor. r%d, r%d, r%d\n\n",ra,rs,rb); + int result=GPR.read(rs) ^ GPR.read(rb); + + CR0_update(CR, XER, result); + + GPR.write(ra,result); +}; + +//!Instruction xori behavior method. +void ac_behavior( xori ) +{ + dbg_printf(" xori r%d, r%d, %d\n\n",ra,rs,ui); + + GPR.write(ra,GPR.read(rs) ^ (int)((unsigned short int)ui)); +}; + +//!Instruction xoris behavior method. +void ac_behavior( xoris ) +{ + dbg_printf(" xoris r%d, r%d, %d\n\n",ra,rs,ui); + + GPR.write(ra,GPR.read(rs) ^ (((int)((unsigned short int)ui)) << 16)); +}; diff --git a/pdl/powerpc/powerpc_nonblock.ac b/pdl/powerpc/powerpc_nonblock.ac new file mode 100644 index 0000000..805f508 --- /dev/null +++ b/pdl/powerpc/powerpc_nonblock.ac @@ -0,0 +1,77 @@ +/** + * @file powerpc.ac + * @author Bruno Corsi dos Santos + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Thu, 29 Jun 2006 14:49:05 -0300 + * + * @brief The ArchC POWERPC functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +AC_ARCH(powerpc) { + + ac_wordsize 32; + ac_fetchsize 32; + ac_tlm2_nb_port MEM:512M; + //ac_icache IC("2w", 128, 32, "wb", "fifo"); + //ac_dcache DC("2w", 512, 32, "wt", "fifo"); + + ac_icache IC("dm", 64, 8, "wt", "none"); + ac_dcache DC("dm", 64, 8, "wt", "none"); + + ac_regbank GPR:32; + + ac_reg SPRG4; + ac_reg SPRG5; + ac_reg SPRG6; + ac_reg SPRG7; + ac_reg USPRG0; + + ac_reg XER; + + ac_reg MSR; + ac_reg id; + + ac_tlm2_intr_port intr_port; + + // sc instruction not tested/used + ac_reg EVPR; + ac_reg SRR0; + ac_reg SRR1; + + ac_reg CR; + ac_reg LR; + ac_reg CTR; + + ARCH_CTOR(powerpc) { + ac_isa("powerpc_isa.ac"); + set_endian("big"); + IC.bindTo(MEM); + DC.bindTo(MEM); + }; + +}; diff --git a/pdl/powerpc/powerpc_syscall.cpp b/pdl/powerpc/powerpc_syscall.cpp new file mode 100644 index 0000000..f2ea879 --- /dev/null +++ b/pdl/powerpc/powerpc_syscall.cpp @@ -0,0 +1,118 @@ +/** + * @file powerpc_syscall.cpp + * @author Bruno Corsi dos Santos + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:50:48 -0300 + * + * @brief The ArchC POWERPC functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include "powerpc_syscall.H" + +using namespace powerpc_parms; + +void powerpc_syscall::get_buffer(int argn, unsigned char* buf, unsigned int size) +{ + unsigned int addr = GPR.read(3+argn); + + for (unsigned int i = 0; iread_byte(addr); + } +} + +void powerpc_syscall::set_buffer(int argn, unsigned char* buf, unsigned int size) +{ + unsigned int addr = GPR.read(3+argn); + + for (unsigned int i = 0; iwrite_byte(addr, buf[i]); + } +} + +void powerpc_syscall::set_buffer_noinvert(int argn, unsigned char* buf, unsigned int size) +{ + unsigned int addr = GPR.read(3+argn); + + for (unsigned int i = 0; iwrite(addr, *(unsigned int *) &buf[i]); + } +} + +int powerpc_syscall::get_int(int argn) +{ + return GPR.read(3+argn); +} + +void powerpc_syscall::set_int(int argn, int val) +{ + GPR.write(3+argn, val); +} + +void powerpc_syscall::return_from_syscall() +{ + unsigned int oldr1; + unsigned int oldr31; +// oldr1=MEM.read(GPR.read(1)); +// oldr31=MEM.read(GPR.read(1)+28); +// GPR.write(1,oldr1); +// GPR.write(31,oldr31); + ac_pc=LR.read(); +} + +void powerpc_syscall::set_prog_args(int argc, char **argv) +{ + int i, j, base; + + unsigned int ac_argv[30]; + char ac_argstr[512]; + + base = AC_RAM_END - 512; + for (i=0, j=0; ilibac_sysc folder and run make command +via terminal. + + - Step 2:. Copy the folder of the program you wish to test from +test/acstone-programs, test/automotive-IMA or test/acstone-FP to +the test folder. Enter that folder and run make. + +## Running the executable + +To run a test program on the simulator, use the following command +line: +````````` +./riscv.x -- .run +````````` + +## Future Work + +The following topics need further improvement: + + - Double-precision floating point instructions need testing. + + - GDB: The RISC-V toolchain creates executables using DWARF version 4. + Currently, ArchC is capable of retargeting GDB 6.4, which is + quite outdated and can only read DWARF version 2. Therefore, + acbingen at the official ArchC repo needs to be udpated in order + to allow GDB debugging in this model. + +## References + +I used the following as a reference for developing this model: + + - Mips processor model + [https://github.com/ArchC/mips/tree/mips32r2] + +## Code imported + +This model uses the following third-party code: + + - riscv_syscall.cpp and riscv_syscall.H from Dario Soares' github repo + [https://github.com/DarioSoares/riscv-archc] + - Framework for creating ArchC-compatible ELF binaries developed by + Dario Soares \ No newline at end of file diff --git a/pdl/riscv/compiler_info.ac b/pdl/riscv/compiler_info.ac new file mode 100644 index 0000000..c5251c4 --- /dev/null +++ b/pdl/riscv/compiler_info.ac @@ -0,0 +1,46 @@ +// RISC-V Instruction Semantic S-operator for Petrich PIG. +// Author: Boris G. Shingarov. +// Based on the AccGen grammar. + +//====================-- Machine specific rules --============================// + +//=====================-- Registers definitions --============================// + +define registers GPR:regs as ( + x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x17 x18 x19 x20 x21 + x22 x23 x24 x25 x26 x27 x28 x29 x30 x31 +); + +define operand spec as size 32 like int; + +//===========================-- ABI stuff --==================================// + +redefine operand tgtimm size to 12; + +define abi as ( +/* + define callee save registers as ($16 $17 $18 $19 $20 $21 $22 $23); + define reserved registers as ($0 $14 $15 $26 $27 $28 $29 $30 $31); + define auxiliar registers as ($14 $15); + //define calling convention for int as stack size 4 alignment 4; + define calling convention for int as ($4 $5 $6 $7); + define calling convention for int as stack size 4 alignment 4; + define return convention for int as ($2 $3); + //define programcounter register as PC; + define stackpointer register as $29; + define framepointer register as $30; + define return register as $31; + define stack grows down alignment 8; + define pcoffset -8; +*/ +); + +//==================-- Instruction semantic fragments --======================// + + + +//=======================-- Instructions definitions --=======================// + + + + diff --git a/pdl/riscv/defines_gdb b/pdl/riscv/defines_gdb new file mode 100644 index 0000000..8be90d9 --- /dev/null +++ b/pdl/riscv/defines_gdb @@ -0,0 +1,20 @@ +//Number of registers +#define NUM_REGISTERS 33 + +//Number stack pointer register +#define NUM_REGISTER_SP 2 + +//Number frame pointer register +#define NUM_REGISTER_FP 8 + +//Number program counter register +#define NUM_REGISTER_PC 32 + +//Number first return procedures register +#define NUM_REGISTER_RET1 1 + +//Number second return procedures register - only SPARC +#define NUM_REGISTER_RET2 -1 + +//Offset add in pc register - only SPARC +#define OFFSET 0 \ No newline at end of file diff --git a/pdl/riscv/riscv-opcodes b/pdl/riscv/riscv-opcodes new file mode 160000 index 0000000..7cdc041 --- /dev/null +++ b/pdl/riscv/riscv-opcodes @@ -0,0 +1 @@ +Subproject commit 7cdc0412849acbd5a4a041b24c9defb7e2f6d9bc diff --git a/pdl/riscv/riscv64.ac b/pdl/riscv/riscv64.ac new file mode 100644 index 0000000..83a9384 --- /dev/null +++ b/pdl/riscv/riscv64.ac @@ -0,0 +1,29 @@ +/* +* +* @file riscv_isa.cpp +* @version 1.0 +* +* +* @date May 2016 +* @brief The ArchC RISC-V functional model +* +* +*/ + + +AC_ARCH(riscv64) { + + ac_mem DM:512M; + ac_regbank GPRs:32; + + ac_regbank FPRs:32; + ac_reg fcsr; + + ac_wordsize 64; + + + ARCH_CTOR(riscv) { + ac_isa("riscv64_isa.ac"); + set_endian("little"); + }; +}; diff --git a/pdl/riscv/riscv64_isa.ac b/pdl/riscv/riscv64_isa.ac new file mode 100644 index 0000000..b2a21b4 --- /dev/null +++ b/pdl/riscv/riscv64_isa.ac @@ -0,0 +1,149 @@ +/* +* @file riscv_isa.cpp +* @version 1.0 +* @author Pavani Tripathi, Jan Vrany +* +* @date May 2016 +* @brief The ArchC RISC-V functional model +* +* @source http://people.eecs.berkeley.edu/~krste/papers/riscv-spec-2.0.pdf +* +* This file is has been refactored to use Pharo-ArchC [1] extensions to +* allow reading instructions from riscv-opcodes [2]. +* +* [1]: https://github.com/shingarov/Pharo-ArchC +* [2]: https://github.com/riscv/riscv-opcodes +*/ + +AC_ISA(riscv){ + + ac_helper { + #include "riscv_isa_helper.H" + }; + + ac_format Type_R = + "%funct7:7 %rs2:5 %rs1:5 %funct3:3 %rd:5 %opcode:7"; + + ac_format Type_R4 = + "%rs3:5 %funct2:2 %rs2:5 %rs1:5 %funct3:3 %rd:5 %opcode:7"; + + // For F and D extensions + ac_format Type_Rfd = + "%funct5:5 %fmt:2 %rs2:5 %rs1:5 %rm:3 %rd:5 %opcode:7"; + + // For A extension + ac_format Type_Ra = + "%funct5_h3:3 %funct5_l2:2 %aqrl:2 %rs2:5 %rs1:5 %funct3:3 %rd:5 %opcode:7"; + + // For F and D extensions + ac_format Type_R4fd = + "%rs3:5 %fmt:2 %rs2:5 %rs1:5 %rm:3 %rd:5 %opcode:7"; + + ac_format Type_I = + "%imm:12 %rs1:5 %funct3:3 %rd:5 %opcode:7"; + + ac_format Type_Ish = + "%shfun:6 %shamt:6 %rs1:5 %funct3:3 %rd:5 %opcode:7"; + + ac_format Type_Ishw = + "%shfunw:6 %zerobit:1 %shamtw:5 %rs1:5 %funct3:3 %rd:5 %opcode:7"; + + ac_format Type_Ifence = + "%fm:4 %pred:4 %succ:4 %rs1:5 %funct3:3 %rd:5 %opcode:7"; + + ac_format Type_S = + "%imm2:7 %rs2:5 %rs1:5 %funct3:3 %imm1:5 %opcode:7"; + + ac_format Type_B = + "%imm4:1 %imm2:6 %rs2:5 %rs1:5 %funct3:3 %imm1:4 %imm3:1 %opcode:7"; + + ac_format Type_U = + "%imm:20 %rd:5 %opcode:7"; + + ac_format Type_J = + "%imm4:1 %imm1:10 %imm2:1 %imm3:8 %rd:5 %opcode:7"; + + + ac_asm_map gpr { + /* + * RISC-V GPR architectural register names + */ + "x"[0..31] = [0..31]; + + /* + * RISC-V GPR "ABI" register names, see [1] + * + * [1]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc + */ + "zero" = 0; + "ra" = 1; + "sp" = 2; + "gp" = 3; + "tp" = 4; + "t"[0..2] = [5..7]; + "s"[0..1] = [8..9]; + "a"[0..7] = [10..17]; + "s"[2..11] = [18..27]; + "t"[3..6] = [28..31]; + } + + // Floating-point register names + ac_asm_map fpr { + /* + * RISC-V FPR architectural register names + */ + "f"[0..31] = [0..31]; + /* + * RISC-V FPR "ABI" register names, see [1] + */ + "ft"[0..7] = [0..7]; + "fs"[0..1] = [8..9]; + "fa"[0..7] = [10..17]; + "fs"[2..11] = [18..27]; + "ft"[8..11] = [28..31]; + } + + // Floating point rounding mode + // See RISC-V Unprivileged ISA, + // Section 11.2 Floating-Point Control and Status Register + ac_asm_map rm { + "rne" = 0; // Round to Nearest, ties to Even + "rtz" = 1; // Round towards Zero + "rdn" = 2; // Round Down (towards −Inf) + "rup" = 3; // Round Up (towards +Inf) + "rmm" = 4; // Round to Nearest, ties to Max Magnitude + "inv101" = 5; // Invalid, reserved. + "inv110" = 6; // Invalid, reserved. + "dyn" = 7; // In instruction’s rm field: selects dynamic rounding mode, + // In Rounding Mode register: invalid. + } + + // Ordering of atomic instructions + // See RISC-V Unprivileged ISA, + // Section 8.1 Specifying Ordering of Atomic Instructions + ac_asm_map aqrl { + "" = 0; // No additional ordering constraints imposed + ".rl" = 1; // Atomic memory operation is treated as a release access + ".aq" = 2; // Atomic memory operation is treated as an acquire access + ".aqrl" = 3; // The atomic memory operation is sequentially consistent + } + + /* + * RV64G is shorthand for the IMAFDZicsr Zifencei + */ + _ac_riscv_opcodes("riscv-opcodes/opcodes-system"); + _ac_riscv_opcodes("riscv-opcodes/opcodes-rv32i"); + _ac_riscv_opcodes("riscv-opcodes/opcodes-rv64i"); + + _ac_riscv_opcodes("riscv-opcodes/opcodes-rv32m"); + _ac_riscv_opcodes("riscv-opcodes/opcodes-rv64m"); + + _ac_riscv_opcodes("riscv-opcodes/opcodes-rv32f"); + _ac_riscv_opcodes("riscv-opcodes/opcodes-rv64f"); + + _ac_riscv_opcodes("riscv-opcodes/opcodes-rv32d"); + _ac_riscv_opcodes("riscv-opcodes/opcodes-rv64d"); + + _ac_riscv_opcodes("riscv-opcodes/opcodes-rv32a"); + _ac_riscv_opcodes("riscv-opcodes/opcodes-rv64a"); +}; diff --git a/pdl/riscv/riscv_gdb_funcs.cpp b/pdl/riscv/riscv_gdb_funcs.cpp new file mode 100644 index 0000000..7143511 --- /dev/null +++ b/pdl/riscv/riscv_gdb_funcs.cpp @@ -0,0 +1,39 @@ +/* +* +* @file riscv_isa.cpp +* @version 1.0 +* +* +* @date May 2016 +* @brief The ArchC RISC-V functional model +* +* +*/ + +#include "riscv.H" + +using namespace riscv_parms; + +int riscv::nRegs(void) { return 33; } + +ac_word riscv::reg_read(int reg) { + if ((reg >= 0) && (reg < 32)) + return RB.read(reg); + else if (reg == 32) + return ac_pc; +} + +void riscv::reg_write(int reg, ac_word value) { + if ((reg >= 0) && (reg < 32)) + RB.write(reg, value); + else if (reg == 32) + ac_pc = value; +} + +unsigned char riscv::mem_read(unsigned int address) { + return DATA_PORT->read_byte(address); +} + +void riscv::mem_write(unsigned int address, unsigned char byte) { + DATA_PORT->write_byte(address, byte); +} diff --git a/pdl/riscv/riscv_isa.cpp b/pdl/riscv/riscv_isa.cpp new file mode 100644 index 0000000..8b6b6db --- /dev/null +++ b/pdl/riscv/riscv_isa.cpp @@ -0,0 +1,1344 @@ +/* +* +* @file riscv_isa.cpp +* @version 1.0 +* @author Pavani Tripathi +* +* Thanks to Dario Soares for contributing his model at +* https://github.com/DarioSoares/riscv-archc +* +* @date Aug 2016 +* @brief The ArchC RISC-V functional model +* +* @Source http://people.eecs.berkeley.edu/~krste/papers/riscv-spec-2.0.pdf +* +*/ + +#include "riscv_isa.H" +#include "riscv_isa_init.cpp" +#include "riscv_bhv_macros.H" + +// Uncomment for debug Information +//#define DEBUG_MODEL +#include "ac_debug_model.H" + +#define Ra 1 +#define Sp 14 + +// For using all the RISC-V parameters +using namespace riscv_parms; + +static int processors_started = 0; +#define DEFAULT_STACK_SIZE (512 * 1024); + + +// Generic instruction behavior method +void ac_behavior(instruction) { + dbg_printf("---PC=%#x---%lld\n", (int)ac_pc, ac_instr_counter); + ac_pc = ac_pc + 4; +} + +// Instruction Format behavior methods +void ac_behavior(Type_R) {} +void ac_behavior(Type_R4) {} +void ac_behavior(Type_I) {} +void ac_behavior(Type_S) {} +void ac_behavior(Type_SB) {} +void ac_behavior(Type_U) {} +void ac_behavior(Type_UJ) {} + + +// Behavior called before starting simulation +void ac_behavior(begin) { + dbg_printf("@@@ begin behavior @@@\n"); + + for (int regNum = 0; regNum < 32; regNum++) + { + RB[regNum] = 0; + RBF[regNum] = 0; + RBF[regNum+32] = 0; + } + fcsr = 0; +} + + +// Behavior called after finishing simulation +void ac_behavior(end) { + dbg_printf("@@@ end behavior @@@\n"); +} + +// Instruction ADD behavior method. (no check for overflow) +void ac_behavior(ADD) { + dbg_printf("ADD r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + RB[rd] = RB[rs1] + RB[rs2]; + dbg_printf("Result = %d\n\n", RB[rd]); +} + +// Instruction SUB behavior method. (no check for overflow) +void ac_behavior(SUB) { + dbg_printf("SUB r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + RB[rd] = RB[rs1] - RB[rs2]; + dbg_printf("Result = %d\n\n", RB[rd]); +} + +// Instruction SLL behavior method. +void ac_behavior(SLL) { + dbg_printf("SLL r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = RB[rs1] << RB[rs2]; + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + dbg_printf("Result = %d\n\n", RB[rd]); +} + +// Instruction SLT behavior method. +void ac_behavior(SLT) { + dbg_printf("SLT r%d, r%d, r%d\n", rd, rs1, rs2); + if ((ac_Sword)RB[rs1] < (ac_Sword)RB[rs2]) + RB[rd] = 1; + else + RB[rd] = 0; + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + dbg_printf("Result = %d\n\n", RB[rd]); +} + +// Instruction SLTU behavior method. +void ac_behavior(SLTU) { + dbg_printf("SLTU r%d, r%d, r%d\n", rd, rs1, rs2); + if ((ac_Uword)RB[rs1] < (ac_Uword)RB[rs2]) + RB[rd] = 1; + else + RB[rd] = 0; + dbg_printf("RB[rs1] = %#x\n", RB[rs1]); + dbg_printf("RB[rs2] = %#x\n", RB[rs2]); + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction XOR behavior method. +void ac_behavior(XOR) { + dbg_printf("XOR r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = RB[rs1] ^ RB[rs2]; + dbg_printf("RB[rs1] = %#x\n", RB[rs1]); + dbg_printf("RB[rs2] = %#x\n", RB[rs2]); + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction SRL behavior method. +void ac_behavior(SRL) { + dbg_printf("SRL r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = RB[rs1] >> RB[rs2]; + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + dbg_printf("Result = %d\n\n", RB[rd]); +} + +// Instruction SRA behavior method. +void ac_behavior(SRA) { + dbg_printf("SRA r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = ((ac_Sword)RB[rs1]) >> RB[rs2]; + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + dbg_printf("Result = %d\n\n", RB[rd]); +} + +// Instruction OR behavior method. +void ac_behavior(OR) { + dbg_printf("OR r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = RB[rs1] | RB[rs2]; + dbg_printf("RB[rs1] = %#x\n", RB[rs1]); + dbg_printf("RB[rs2] = %#x\n", RB[rs2]); + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction AND behavior method. +void ac_behavior(AND) { + dbg_printf("AND r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = RB[rs1] & RB[rs2]; + dbg_printf("RB[rs1] = %#x\n", RB[rs1]); + dbg_printf("RB[rs2] = %#x\n", RB[rs2]); + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction LB behavior method. +void ac_behavior(LB) { + char byte; + int offset; + offset = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("LB r%d, r%d, %d\n", rd, rs1, offset); + int sign_ext; + sign_ext = sign_extend(offset, 12); + byte = DM.read_byte(RB[rs1] + sign_ext); + RB[rd] = sign_extend(byte, 7); + dbg_printf("RB[rs1] = %#x, byte = %#x\n", RB[rs1], byte); + dbg_printf("addr = %#x\n", RB[rs1] + sign_ext); + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction LH behavior method. +void ac_behavior(LH) { + short int half; + int offset; + offset = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("LH r%d, r%d, %d\n", rd, rs1, offset); + int sign_ext; + sign_ext = sign_extend(offset, 12); + half = DM.read_half(RB[rs1] + sign_ext); + RB[rd] = sign_extend(half, 16); + dbg_printf("RB[rs1] = %#x, half = %#x\n", RB[rs1], half); + dbg_printf("addr = %#x\n", RB[rs1] + sign_ext); + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction LW behavior method. +void ac_behavior(LW) { + int offset; + offset = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("LW r%d, r%d, %d\n", rd, rs1, offset); + int sign_ext; + sign_ext = sign_extend(offset, 12); + RB[rd] = DM.read(RB[rs1] + sign_ext); + dbg_printf("RB[rs1] = %#x\n", RB[rs1]); + dbg_printf("addr = %#x\n", RB[rs1] + sign_ext); + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction LBU behavior method. +void ac_behavior(LBU) { + int offset; + offset = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("LBU r%d, r%d, %d\n", rd, rs1, offset); + int sign_ext; + sign_ext = sign_extend(offset, 12); + RB[rd] = DM.read_byte(RB[rs1] + sign_ext); + dbg_printf("RB[rs1] = %#x\n", RB[rs1]); + dbg_printf("addr = %#x\n", RB[rs1] + sign_ext); + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction LHU behavior method. +void ac_behavior(LHU) { + int offset; + offset = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("LHU r%d, r%d, %d\n", rd, rs1, offset); + int sign_ext; + sign_ext = sign_extend(offset, 12); + RB[rd] = DM.read_half(RB[rs1] + sign_ext); + dbg_printf("RB[rs1] = %#x\n", RB[rs1]); + dbg_printf("addr = %#x\n", RB[rs1] + sign_ext); + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction ADDI behavior method. +void ac_behavior(ADDI) { + int imm; + imm = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("ADDI r%d, r%d, %d\n", rd, rs1, imm); + if ((rd == 0) && (rs1 == 0) && (imm == 0)) { + dbg_printf("NOP executed!"); + } else { + int sign_ext; + sign_ext = sign_extend(imm, 12); + RB[rd] = RB[rs1] + sign_ext; + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("imm = %d\n", sign_ext); + dbg_printf("Result = %d\n\n", RB[rd]); + } +} + +// Instruction SLTI behavior method. +void ac_behavior(SLTI) { + int imm; + imm = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("SLTI r%d, r%d, %d\n", rd, rs1, imm); + int sign_ext; + sign_ext = sign_extend(imm, 12); + if (RB[rs1] < sign_ext) + RB[rd] = 1; + else + RB[rd] = 0; + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("imm = %d\n", sign_ext); + dbg_printf("Result = %d\n\n", RB[rd]); +} + +// Instruction SLTIU behavior method. +void ac_behavior(SLTIU) { + int imm; + imm = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("SLTIU r%d, r%d, %d\n", rd, rs1, imm); + int sign_ext; + sign_ext = sign_extend(imm, 12); + if ((ac_Uword)RB[rs1] < (ac_Uword)sign_ext) + RB[rd] = 1; + else + RB[rd] = 0; + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction XORI behavior method. +void ac_behavior(XORI) { + int imm; + imm = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("XORI r%d, r%d, %d\n", rd, rs1, imm); + int sign_ext; + sign_ext = sign_extend(imm, 12); + RB[rd] = RB[rs1] ^ sign_ext; + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction ORI behavior method. +void ac_behavior(ORI) { + int imm; + imm = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("ORI r%d, r%d, %d\n", rd, rs1, imm); + int sign_ext; + sign_ext = sign_extend(imm, 12); + RB[rd] = RB[rs1] | sign_ext; + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction ANDI behavior method. +void ac_behavior(ANDI) { + int imm; + imm = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("ANDI r%d, r%d, %d\n", rd, rs1, imm); + int sign_ext; + sign_ext = sign_extend(imm, 12); + RB[rd] = RB[rs1] & sign_ext; + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction JALR behavior method. +void ac_behavior(JALR) { + int target_addr; + int imm; + imm = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("JALR r%d, r%d, %d\n", rd, rs1, imm); + int sign_ext; + sign_ext = sign_extend(imm, 12); + target_addr = RB[rs1] + sign_ext; + target_addr = target_addr >> 1; + target_addr = target_addr << 1; + if (rd != 0) + RB[rd] = ac_pc; + ac_pc = target_addr; + dbg_printf("Target = %#x\n", (ac_pc & 0xF0000000) | target_addr); + dbg_printf("Target = %#x\n", target_addr); + dbg_printf("Return = %#x\n\n", RB[rd]); +} + +// Instruction SLLI behavior method. +void ac_behavior(SLLI) { + short int shamt; + shamt = (imm2 << 1) | imm1; + dbg_printf("SLLI r%d, r%d, %d\n", rd, rs1, shamt); + RB[rd] = RB[rs1] << shamt; + dbg_printf("shamt = %d\n", shamt); + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction SRLI behavior method. +void ac_behavior(SRLI) { + short int shamt; + shamt = (imm2 << 1) | imm1; + dbg_printf("SRLI r%d, r%d, %d\n", rd, rs1, shamt); + RB[rd] = RB[rs1] >> shamt; + dbg_printf("shamt = %d\n", shamt); + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction SRAI behavior method. +void ac_behavior(SRAI) { + short int shamt; + shamt = (imm2 << 1) | imm1; + dbg_printf("SRAI r%d, r%d, %d\n", rd, rs1, shamt); + if ((RB[rs1] >> 31) == 1) + RB[rd] = (RB[rs1] >> shamt) | (0xFFFFFFFF << (32 - shamt)); + else + RB[rd] = RB[rs1] >> shamt; + dbg_printf("shamt = %d\n", shamt); + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction SCALL behavior method. +void ac_behavior(SCALL) { + dbg_printf("SCALL\n"); + printf("System Call\n\n"); + stop(); +} + +// Instruction SBREAK behavior method. +void ac_behavior(SBREAK) { + dbg_printf("SBREAK\n"); + printf("Breakpoint\n\n"); + stop(); +} + +// Instruction RDCYCLE behavior method. +void ac_behavior(RDCYCLE) { + dbg_printf("RDCYCLE r%d\n", rd); + RB[rd] = ac_pc; + dbg_printf("Result = %#x\n", RB[rd]); +} + +// Instruction RDCYCLEH behavior method. +void ac_behavior(RDCYCLEH) { dbg_printf("RDCYCLEH r%d\n", rd); } + +// Instruction RDTIME behavior method. +void ac_behavior(RDTIME) { dbg_printf("RDTIME r%d\n", rd); } + +// Instruction RDTIMEH behavior method. +void ac_behavior(RDTIMEH) { dbg_printf("RDTIMEH r%d\n", rd); } + +// Instruction RDINSTRET behavior method. +void ac_behavior(RDINSTRET) { dbg_printf("RDINSTRET r%d\n", rd); } + +// Instruction RDINSTRETH behavior method. +void ac_behavior(RDINSTRETH) { dbg_printf("RDINSTRETH r%d\n", rd); } + +// Instruction SB behavior method +void ac_behavior(SB) { + int imm; + imm = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("SB r%d, r%d, %d\n", rs1, rs2, imm); + unsigned char byte = RB[rs2] & 0xFF; + int sign_ext; + sign_ext = sign_extend(imm, 12); + DM.write_byte(RB[rs1] + sign_ext, byte); + dbg_printf("addr: %#x\n", RB[rs1] + sign_ext); + dbg_printf("Result: %#x\n\n\n", byte); +} + +// Instruction SH behavior method +void ac_behavior(SH) { + int imm; + imm = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("SH r%d, r%d, %d\n", rs1, rs2, imm); + int sign_ext; + sign_ext = sign_extend(imm, 12); + unsigned short int half = RB[rs2] & 0xFFFF; + DM.write_half(RB[rs1] + sign_ext, half); + dbg_printf("addr: %#x\n", RB[rs1] + sign_ext); + dbg_printf("Result: %#x\n\n\n", half); +} + +// Instruction SW behavior method +void ac_behavior(SW) { + int imm; + imm = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("SW r%d, r%d, %d\n", rs1, rs2, imm); + int sign_ext; + sign_ext = sign_extend(imm, 12); + DM.write(RB[rs1] + sign_ext, RB[rs2]); + dbg_printf("addr: %d\n\n", RB[rs1] + sign_ext); +} + +// Instruction BEQ behavior method +void ac_behavior(BEQ) { + int imm; + imm = (imm4 << 11) | (imm3 << 10) | (imm2 << 4) | imm1; + dbg_printf("BEQ r%d, r%d, %d\n", rs1, rs2, imm); + unsigned int addr; + if (imm4 == 1) + addr = ac_pc + ((imm << 1) | 0xFFFFF000) - 4; + else + addr = ac_pc + (imm << 1) - 4; + if (RB[rs1] == RB[rs2]) { + ac_pc = addr; + dbg_printf("---Branch Taken--- to %#x\n\n", addr); + } else + dbg_printf("---Branch not Taken---\n\n"); +} + +// Instruction BNE behavior method +void ac_behavior(BNE) { + int imm; + imm = (imm4 << 11) | (imm3 << 10) | (imm2 << 4) | imm1; + dbg_printf("BNE r%d, r%d, %d\n", rs1, rs2, imm); + unsigned int addr; + if (imm4 == 1) + addr = ac_pc + ((imm << 1) | 0xFFFFF000) - 4; + else + addr = ac_pc + (imm << 1) - 4; + if (RB[rs1] != RB[rs2]) { + ac_pc = addr; + dbg_printf("---Branch Taken---\n\n"); + } else + dbg_printf("---Branch not Taken---\n\n"); +} + +// Instruction BLT behavior method +void ac_behavior(BLT) { + int imm; + imm = (imm4 << 11) | (imm3 << 10) | (imm2 << 4) | imm1; + dbg_printf("BLT r%d, r%d, %d\n", rs1, rs2, imm); + unsigned int addr; + if (imm4 == 1) + addr = ac_pc + ((imm << 1) | 0xFFFFF000) - 4; + else + addr = ac_pc + (imm << 1) - 4; + dbg_printf("blt r%d, r%d, %#x\n", rs1, rs2, addr); + dbg_printf("addr = %#x\n", addr); + dbg_printf("rs1 = %#x\n", RB[rs1]); + dbg_printf("rs2 = %#x\n", RB[rs2]); + if ((ac_Sword)RB[rs1] < (ac_Sword)RB[rs2]) { + ac_pc = addr; + dbg_printf("---Branch Taken---\n\n"); + } else + dbg_printf("---Branch not Taken---\n\n"); +} + +// Instruction BGE behavior method +void ac_behavior(BGE) { + int imm; + imm = (imm4 << 11) | (imm3 << 10) | (imm2 << 4) | imm1; + dbg_printf("BGE r%d, r%d, %d\n", rs1, rs2, imm); + unsigned int addr; + if (imm4 == 1) + addr = ac_pc + ((imm << 1) | 0xFFFFF000) - 4; + else + addr = ac_pc + (imm << 1) - 4; + if ((ac_Sword)RB[rs1] >= (ac_Sword)RB[rs2]) { + ac_pc = addr; + dbg_printf("---Branch Taken---\n\n"); + } else + dbg_printf("---Branch not Taken---\n\n"); +} + +// Instruction BLTU behavior method +void ac_behavior(BLTU) { + int imm; + imm = (imm4 << 11) | (imm3 << 10) | (imm2 << 4) | imm1; + dbg_printf("BLTU r%d, r%d, %d\n", rs1, rs2, imm); + unsigned int addr; + if (imm4 == 1) + addr = ac_pc + ((imm << 1) | 0xFFFFF000) - 4; + else + addr = ac_pc + (imm << 1) - 4; + if ((ac_Uword)RB[rs1] < (ac_Uword)RB[rs2]) { + ac_pc = addr; + dbg_printf("---Branch Taken---\n\n"); + } else + dbg_printf("---Branch not Taken---\n\n"); +} + +// Instruction BGEU behavior method +void ac_behavior(BGEU) { + int imm; + imm = (imm4 << 11) | (imm3 << 10) | (imm2 << 4) | imm1; + dbg_printf("BGEU r%d, r%d, %d\n", rs1, rs2, imm); + int addr; + if (imm4 == 1) + addr = ac_pc + ((imm << 1) | 0xFFFFF000) - 4; + else + addr = ac_pc + (imm << 1) - 4; + if (((ac_Uword)RB[rs1] > (ac_Uword)RB[rs2]) || + ((ac_Uword)RB[rs1] == (ac_Uword)RB[rs2])) { + ac_pc = addr; + dbg_printf("---Branch Taken---\n\n"); + } else + dbg_printf("---Branch not Taken---\n\n"); +} + +// Instruction LUI behavior method +void ac_behavior(LUI) { + dbg_printf("LUI r%d, %d\n", rd, imm); + RB[rd] = imm << 12; + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction AUIPC behavior method +void ac_behavior(AUIPC) { + dbg_printf("AUIPC r%d, %d\n", rd, imm); + unsigned int offset; + offset = imm << 12; + RB[rd] = ac_pc + offset - 4; + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction JAL behavior method +void ac_behavior(JAL) { + int imm; + imm = (imm4 << 19) | (imm3 << 11) | (imm2 << 10) | imm1; + dbg_printf("JAL r%d, %d\n", rd, imm); + int addr; + if (imm4 == 1) + addr = ac_pc + ((imm << 1) | 0xFFF00000) - 4; + else + addr = ac_pc + (imm << 1) - 4; + if (rd != 0) + RB[rd] = ac_pc; + ac_pc = (ac_pc & 0xF0000000) | addr; + dbg_printf("--- Jump taken ---\n\n"); +} + +// Instruction MUL behavior method +void ac_behavior(MUL) { + dbg_printf("MUL r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + long long mult; + mult = (ac_Sword)RB[rs1]; + mult *= (ac_Sword)RB[rs2]; + int half; + half = mult; + RB[rd] = half; + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction MULH behavior method +void ac_behavior(MULH) { + dbg_printf("MULH r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + long long mult; + int half; + mult = (ac_Sword)RB[rs1]; + mult *= (ac_Sword)RB[rs2]; + half = mult >> 32; + RB[rd] = half; + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction MULHSU behavior method +void ac_behavior(MULHSU) { + dbg_printf("MULHSU r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + long long mult; + int half; + mult = RB[rs1]; + mult *= (ac_Uword)RB[rs2]; + half = mult >> 32; + RB[rd] = half; + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction MULHU behavior method +void ac_behavior(MULHU) { + dbg_printf("MULHU r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + unsigned long long mult; + unsigned int half; + mult = (ac_Uword)RB[rs1]; + mult *= (ac_Uword)RB[rs2]; + half = mult >> 32; + RB[rd] = half; + dbg_printf("Result = %d\n\n", RB[rd]); +} + +// Instruction DIV behavior method +void ac_behavior(DIV) { + dbg_printf("DIV r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("rs1 = %d\n", RB[rs1]); + dbg_printf("rs2 = %d\n", RB[rs2]); + if (RB[rs2] == 0) + RB[rd] = -1; + else if ((RB[rs1] == ((-2) ^ 31)) && (RB[rs2] == -1)) + RB[rd] = ((-2) ^ 31); + else + RB[rd] = (ac_Sword)RB[rs1] / (ac_Sword)RB[rs2]; + dbg_printf("Result = %d\n\n", RB[rd]); +} + +// Instruction DIVU behavior method +void ac_behavior(DIVU) { + dbg_printf("DIVU r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + if (RB[rs2] == 0) + RB[rd] = -1; + else if ((RB[rs1] == ((-2) ^ 31)) && (RB[rs2] == -1)) + dbg_printf("Wrong division exception!"); + else + RB[rd] = (ac_Uword)RB[rs1] / (ac_Uword)RB[rs2]; + dbg_printf("Result = %#x\n\n", (ac_Uword)RB[rd]); +} + +// Instruction REM behavior method +void ac_behavior(REM) { + dbg_printf("REM r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + if (RB[rs2] == 0) + RB[rd] = RB[rs1]; + else if ((RB[rs1] == ((-2) ^ 31)) && (RB[rs2] == -1)) + RB[rd] = 0; + else + RB[rd] = RB[rs1] % RB[rs2]; + dbg_printf("Result = %#x\n\n", RB[rd]); +} + +// Instruction REMU behavior method +void ac_behavior(REMU) { + dbg_printf("REMU r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RB[rs1] = %d\n", RB[rs1]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + if (RB[rs2] == 0) + RB[rd] = RB[rs1]; + else if ((RB[rs1] == ((-2) ^ 31)) && (RB[rs2] == -1)) + dbg_printf("Wrong division exception!"); + else + RB[rd] = (ac_Uword)RB[rs1] % (ac_Uword)RB[rs2]; + dbg_printf("Result = %#x\n\n", (ac_Uword)RB[rd]); +} + +// Instruction LR.W behavior method +void ac_behavior(LR_W) { RB[rd] = DM.read(RB[rs1]); } + +// Instruction SC.w behavior method +void ac_behavior(SC_W) { + DM.write(RB[rs1], RB[rs2]); + RB[rd] = 0; // indicating success +} + +// Instruction AMOSWAP.W behavior method +void ac_behavior(AMOSWAP_W) { + dbg_printf("AMOSWAP.W r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = DM.read(RB[rs1]); + dbg_printf("RB[rd] = %d\n", RB[rd]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + int temp; + temp = RB[rs2]; + RB[rs2] = RB[rd]; + RB[rd] = temp; + dbg_printf("After swapping RB[rd] = %d\n\n", RB[rd]); + DM.write(RB[rs1], RB[rd]); +} + +// Instruction AMOADD.W behavior method +void ac_behavior(AMOADD_W) { + dbg_printf("AMOADD.W r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = DM.read(RB[rs1]); + dbg_printf("RB[rd] = %d\n", RB[rd]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + DM.write(RB[rs1], (RB[rd] + RB[rs2])); + dbg_printf("Result = %d\n\n", RB[rd] + RB[rs2]); +} + +// Instruction AMOXOR.W behavior method +void ac_behavior(AMOXOR_W) { + dbg_printf("AMOXOR.W r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = DM.read(RB[rs1]); + dbg_printf("RB[rd] = %d\n", RB[rd]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + DM.write(RB[rs1], (RB[rd] ^ RB[rs2])); + dbg_printf("Result = %d\n\n", RB[rd] ^ RB[rs2]); +} + +// Instruction AMOAND.W behavior method +void ac_behavior(AMOAND_W) { + dbg_printf("AMOAND.W r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = DM.read(RB[rs1]); + dbg_printf("RB[rd] = %d\n", RB[rd]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + DM.write(RB[rs1], (RB[rd] & RB[rs2])); + dbg_printf("Result = %d\n\n", RB[rd] & RB[rs2]); +} + +// Instruction AMOOR.W behavior method +void ac_behavior(AMOOR_W) { + dbg_printf("AMOOR.W r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = DM.read(RB[rs1]); + dbg_printf("RB[rd] = %d\n", RB[rd]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + DM.write(RB[rs1], (RB[rd] | RB[rs2])); + dbg_printf("Result = %d\n\n", RB[rd] | RB[rs2]); +} + +// Instruction AMOMIN.W behavior method +void ac_behavior(AMOMIN_W) { + dbg_printf("AMOMIN.W r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = DM.read(RB[rs1]); + dbg_printf("RB[rd] = %d\n", RB[rd]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + if (RB[rd] < RB[rs2]) + DM.write(RB[rs1], RB[rd]); + else + DM.write(RB[rs1], RB[rs2]); +} + +// Instruction AMOMAX.W behavior method +void ac_behavior(AMOMAX_W) { + dbg_printf("AMOMAX.W r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = DM.read(RB[rs1]); + dbg_printf("RB[rd] = %d\n", RB[rd]); + dbg_printf("RB[rs2] = %d\n\n", RB[rs2]); + if (RB[rd] > RB[rs2]) + DM.write(RB[rs1], RB[rd]); + else + DM.write(RB[rs1], RB[rs2]); +} + +// Instruction AMOMINU.W behavior method +void ac_behavior(AMOMINU_W) { + dbg_printf("AMOMINU.W r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = DM.read(RB[rs1]); + dbg_printf("RB[rd] = %d\n", RB[rd]); + dbg_printf("RB[rs2] = %d\n\n", RB[rs2]); + if ((ac_Uword)RB[rd] < (ac_Uword)RB[rs2]) + DM.write(RB[rs1], RB[rd]); + else + DM.write(RB[rs1], RB[rs2]); +} + +// Instruction AMOMAXU.W behavior method +void ac_behavior(AMOMAXU_W) { + dbg_printf("AMOMAXU.W r%d, r%d, r%d\n", rd, rs1, rs2); + RB[rd] = DM.read(RB[rs1]); + dbg_printf("RB[rd] = %d\n", RB[rd]); + dbg_printf("RB[rs2] = %d\n", RB[rs2]); + if ((ac_Uword)RB[rd] > (ac_Uword)RB[rs2]) + DM.write(RB[rs1], RB[rd]); + else + DM.write(RB[rs1], RB[rs2]); +} + +// Instruction FLW behavior method +void ac_behavior(FLW) { + int offset; + offset = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("FLW r%d, r%d, %d\n", rd, rs1, offset); + int sign_ext; + sign_ext = sign_extend(offset, 12); + RBF[rd] = DM.read(RB[rs1] + sign_ext); + dbg_printf("RB[rs1] = %#x\n", RB[rs1]); + dbg_printf("addr = %#x\n", RB[rs1] + sign_ext); + dbg_printf("Result = %.3f\n\n", (float)RBF[rd]); +} + +// Instruction FSW behavior method +void ac_behavior(FSW) { + int imm; + imm = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("FSW r%d, r%d, %d\n", rs1, rs2, imm); + int sign_ext; + sign_ext = sign_extend(imm, 12); + DM.write(RB[rs1] + sign_ext, RBF[rs2]); + dbg_printf("addr: %d\n\n", RB[rs1] + sign_ext); +} + +// Instruction FADD.S behavior method +void ac_behavior(FADD_S) { + dbg_printf("FADD.S r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %.3f\n", load_float(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_float(rs2)); + float sum; + sum = load_float(rs1) + load_float(rs2); + save_float(sum, rd); + dbg_printf("Result = %.3f\n\n", sum); +} + +// Instruction FSUB.S behavior method +void ac_behavior(FSUB_S) { + dbg_printf("FSUB.S r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %.3f\n", load_float(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_float(rs2)); + float diff; + diff = load_float(rs1) - load_float(rs2); + save_float(diff, rd); + dbg_printf("Result = %.3f\n\n", diff); +} + +// Instruction FMUL.S behavior method +void ac_behavior(FMUL_S) { + dbg_printf("FMUL.S r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %.3f\n", load_float(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_float(rs2)); + float product; + product = load_float(rs1) * load_float(rs2); + save_float(product, rd); + dbg_printf("Result = %.3f\n\n", product); +} + +// Instruction FDIV.S behavior method +void ac_behavior(FDIV_S) { + dbg_printf("FDIV.S r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %.3f\n", load_float(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_float(rs2)); + float quot; + quot = load_float(rs1) / load_float(rs2); + save_float(quot, rd); + dbg_printf("Result = %.3f\n\n", quot); +} + +// Instruction FMIN.S behavior method +void ac_behavior(FMIN_S) { + dbg_printf("FMIN.S r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %.3f\n", load_float(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_float(rs2)); + float temp; + if (load_float(rs1) < load_float(rs2)) { + temp = load_float(rs1); + save_float(temp, rd); + } else { + temp = load_float(rs2); + save_float(temp, rd); + } + dbg_printf("Result = %.3f\n\n", temp); +} + +// Instruction FMAX.S behavior method +void ac_behavior(FMAX_S) { + dbg_printf("FMAX.S r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %.3f\n", load_float(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_float(rs2)); + float temp; + if (load_float(rs1) > load_float(rs2)) { + temp = load_float(rs1); + save_float(temp, rd); + } else { + temp = load_float(rs2); + save_float(temp, rd); + } + dbg_printf("Result = %.3f\n\n", temp); +} + +// Instruction FSQRT.S behavior method +void ac_behavior(FSQRT_S) { + dbg_printf("FSQRT.S r%d, r%d\n", rd, rs1); + dbg_printf("RBF[rs1] = %.3f\n", load_float(rs1)); + float temp; + if (load_float(rs1) < 0) { + dbg_printf("Invalid!"); + stop(); + } else + RBF[rd] = sqrt(RBF[rs1]); + dbg_printf("Result = %.3f\n\n", (float)RBF[rd]); +} + +// Instruction FMADD.S behavior method +void ac_behavior(FMADD_S) { + dbg_printf("FMADD.S r%d, r%d, r%d, r%d\n", rd, rs1, rs2, rs3); + dbg_printf("RBF[rs1] = %.3f\n", load_float(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_float(rs2)); + dbg_printf("RBF[rs2] = %.3f\n", load_float(rs3)); + float res; + res = load_float(rs1) * load_float(rs2) + load_float(rs3); + save_float(res, rd); + dbg_printf("Result = %.3f\n\n", res); +} + +// Instruction FMSUB.S behavior method +void ac_behavior(FMSUB_S) { + dbg_printf("FMSUB.S r%d, r%d, r%d, r%d\n", rd, rs1, rs2, rs3); + dbg_printf("RBF[rs1] = %.3f\n", load_float(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_float(rs2)); + dbg_printf("RBF[rs2] = %.3f\n", load_float(rs3)); + float res; + res = load_float(rs1) * load_float(rs2) - load_float(rs3); + save_float(res, rd); + dbg_printf("Result = %.3f\n\n", res); +} + +// Instruction FNMSUB.S behavior method +void ac_behavior(FNMSUB_S) { + dbg_printf("FNMSUB.S r%d, r%d, r%d, r%d\n", rd, rs1, rs2, rs3); + dbg_printf("RBF[rs1] = %.3f\n", load_float(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_float(rs2)); + dbg_printf("RBF[rs2] = %.3f\n", load_float(rs3)); + float res; + res = (-(load_float(rs1) * load_float(rs2) - load_float(rs3))); + save_float(res, rd); + dbg_printf("Result = %.3f\n\n", res); +} + +// Instruction FNMADD.S behavior method +void ac_behavior(FNMADD_S) { + dbg_printf("FNMADD.S r%d, r%d, r%d, r%d\n", rd, rs1, rs2, rs3); + dbg_printf("RBF[rs1] = %.3f\n", load_float(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_float(rs2)); + dbg_printf("RBF[rs2] = %.3f\n", load_float(rs3)); + float res; + res = (-(load_float(rs1) * load_float(rs2) + load_float(rs3))); + save_float(res, rd); + dbg_printf("Result = %.3f\n\n", res); +} + +// Instruction FCVT.W.S behavior method +void ac_behavior(FCVT_W_S) { + dbg_printf("FCVT.W.S r%d, r%d\n", rd, rs1); + dbg_printf("RBF[rs1] = %f\n", load_float(rs1)); + RB[rd] = round(load_float(rs1)); + dbg_printf("RB[rd] = %d \n \n", RB[rd]); +} + +// Instruction FCVT.WU.S behavior method +void ac_behavior(FCVT_WU_S) { + dbg_printf("FCVT.WU.S r%d, r%d\n", rd, rs1); + dbg_printf("RBF[rs1] = %f\n", load_float(rs1)); + RB[rd] = (unsigned int)(load_float(rs1)); + dbg_printf("RB[rd] = %d \n \n", RB[rd]); +} + +// Instruction FCVT.S.W behaior method +void ac_behavior(FCVT_S_W) { + dbg_printf("FCVT.S.W r%d, r%d \n", rd, rs1); + dbg_printf("RB[rs1] = %d \n", RB[rs1]); + float temp; + temp = (float)RB[rs1]; + save_float(temp, rd); +} + +// Instruction FCVT_S_WU behaior method +void ac_behavior(FCVT_S_WU) { + dbg_printf("FCVT.S.W r%d, r%d \n", rd, rs1); + dbg_printf("RB[rs1] = %d \n", RB[rs1]); + float temp; + temp = (float)RB[rs1]; + save_float(temp, rd); +} + +// Instruction FMV_X_S behavior method +void ac_behavior(FMV_X_S) { + dbg_printf("FMV.X.S r%d, r%d \n", rd, rs1); + dbg_printf("RBF[rs1] = %f \n", load_float(rs1)); + RB[rd] = (int)load_float(rs1); + dbg_printf("RB[rd] = %d \n \n", RB[rd]); +} + +// Instruction FMV_S_X behavior method +void ac_behavior(FMV_S_X) { + dbg_printf("FMV.S.X r%d, r%d \n", rd, rs1); + dbg_printf("RB[rs1] = %d \n", RB[rs1]); + save_float(RB[rs1], rd); + dbg_printf("RBF[rd] = %f \n \n", load_float(rd)); +} + +// Instruction FEQ_S behavior method +void ac_behavior(FEQ_S) { + dbg_printf("FEQ.S r%d, r%d, r%d \n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %f \n", load_float(rs1)); + dbg_printf("RBF[rs2] = %f \n", load_float(rs2)); + if ((isnan(load_float(rs1)) == 1) || (isnan(load_float(rs2)) == 1)) { + printf("Invalid Operation\n"); + RB[rd] = 0; + } + if (load_float(rs1) == load_float(rs2)) + RB[rd] = 1; + else + RB[rd] = 0; + dbg_printf("Result = %d \n \n", RB[rd]); +} + +// Instruction FLE_S behavior method +void ac_behavior(FLE_S) { + dbg_printf("FLE.S r%d, r%d, r%d \n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %f \n", load_float(rs1)); + dbg_printf("RBF[rs2] = %f \n", load_float(rs2)); + if ((isnan(load_float(rs1)) == 1) || (isnan(load_float(rs2)) == 1)) { + printf("Invalid Operation\n"); + RB[rd] = 0; + } + if (load_float(rs1) <= load_float(rs2)) + RB[rd] = 1; + else + RB[rd] = 0; + dbg_printf("Result = %d \n \n", RB[rd]); +} + +// Instruction FLT_S behavior method +void ac_behavior(FLT_S) { + dbg_printf("FLT.S r%d, r%d, r%d \n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %f \n", load_float(rs1)); + dbg_printf("RBF[rs2] = %f \n", load_float(rs2)); + if ((isnan(load_float(rs1)) == 1) || (isnan(load_float(rs2)) == 1)) { + printf("Invalid Operation\n"); + RB[rd] = 0; + } + if (load_float(rs1) < load_float(rs2)) + RB[rd] = 1; + else + RB[rd] = 0; + dbg_printf("Result = %d \n \n", RB[rd]); +} + +// Instruction FMV.S behavior method +void ac_behavior(FMV_S) { + dbg_printf("FMV.S r%d, r%d", rd, rs1); + float temp; + temp = load_float(rs1); + save_float(temp, rd); +} + +// Instruction FLD behavior method +void ac_behavior(FLD) { + int imm; + imm = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("FLD r%d, r%d, %d\n", rd, rs1, imm); + int sign_ext; + sign_ext = sign_extend(imm, 12); + RBF[rd * 2] = DM.read(RB[rs1] + sign_ext); + RBF[rd * 2 + 1] = DM.read(RB[rs1] + sign_ext + 4); + dbg_printf("RB[rs1] = %#x\n", RB[rs1]); + dbg_printf("addr = %#x\n", RB[rs1] + sign_ext); + double temp = load_double(rd); + dbg_printf("Double: %lf", temp); +} + +// Instruction FSD behavior method +void ac_behavior(FSD) { + int imm; + imm = (imm4 << 11) | (imm3 << 5) | (imm2 << 1) | imm1; + dbg_printf("FSD r%d, r%d, %d\n", rs1, rs2, imm); + int sign_ext; + sign_ext = sign_extend(imm, 12); + DM.write(RB[rs1] + sign_ext, RBF[rs2 * 2]); + DM.write(RB[rs1] + sign_ext + 4, RBF[rs2 * 2 + 1]); + dbg_printf("addr: %d\n\n", RB[rs1] + sign_ext); +} + +// Instruction FADD.D behavior method +void ac_behavior(FADD_D) { + dbg_printf("FADD.D r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %.3f\n", load_double(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_double(rs2)); + double sum; + sum = load_double(rs1) + load_double(rs2); + save_double(sum, rd); + dbg_printf("Result = %.3f\n\n", sum); +} + +// Instruction FSUB.D behavior method +void ac_behavior(FSUB_D) { + dbg_printf("FSUB.D r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %.3f\n", load_double(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_double(rs2)); + double diff; + diff = load_double(rs1) - load_double(rs2); + save_double(diff, rd); + dbg_printf("Result = %.3f\n\n", diff); +} + +// Instruction FMUL.D behavior method +void ac_behavior(FMUL_D) { + dbg_printf("FMUL.D r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %.3f\n", load_double(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_double(rs2)); + double product; + product = load_double(rs1) * load_double(rs2); + save_double(product, rd); + dbg_printf("Result = %.3f\n\n", product); +} + +// Instruction FDIV.D behavior method +void ac_behavior(FDIV_D) { + dbg_printf("FDIV.D r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %.3f\n", load_double(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_double(rs2)); + double quot; + quot = load_double(rs1) / load_double(rs2); + save_double(quot, rd); + dbg_printf("Result = %.3f\n\n", quot); +} + +// Instruction FMIN.D behavior method +void ac_behavior(FMIN_D) { + dbg_printf("FMIN.S r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %.3f\n", load_double(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_double(rs2)); + double temp; + if (load_double(rs1) < load_double(rs2)) { + temp = load_double(rs1); + save_double(temp, rd); + } else { + temp = load_double(rs2); + save_double(temp, rd); + } + dbg_printf("Result = %.3f\n\n", temp); +} + +// Instruction FMAX.D behavior method +void ac_behavior(FMAX_D) { + dbg_printf("FMAX.D r%d, r%d, r%d\n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %.3f\n", load_double(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_double(rs2)); + double temp; + if (load_double(rs1) > load_double(rs2)) { + temp = load_double(rs1); + save_double(temp, rd); + } else { + temp = load_double(rs2); + save_double(temp, rd); + } + dbg_printf("Result = %.3f\n\n", temp); +} + +// Instruction FSQRT.D behavior method +void ac_behavior(FSQRT_D) { + dbg_printf("FSQRT.D r%d, r%d\n", rd, rs1); + dbg_printf("RBF[rs1] = %.3f\n", load_double(rs1)); + double temp; + if (load_double(rs1) < 0) { + dbg_printf("Invalid!"); + stop(); + } else { + temp = sqrt(load_double(rs1)); + save_double(temp, rd); + } + dbg_printf("Result = %.3f\n\n", temp); +} + +// Instruction FMADD.D behavior method +void ac_behavior(FMADD_D) { + dbg_printf("FMADD.D r%d, r%d, r%d, r%d\n", rd, rs1, rs2, rs3); + dbg_printf("RBF[rs1] = %.3f\n", load_double(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_double(rs2)); + dbg_printf("RBF[rs2] = %.3f\n", load_double(rs3)); + double res; + res = load_double(rs1) * load_double(rs2) + load_double(rs3); + save_double(res, rd); + dbg_printf("Result = %.3f\n\n", res); +} + +// Instruction FMSUB.D behavior method +void ac_behavior(FMSUB_D) { + dbg_printf("FMSUB.D r%d, r%d, r%d, r%d\n", rd, rs1, rs2, rs3); + dbg_printf("RBF[rs1] = %.3f\n", load_double(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_double(rs2)); + dbg_printf("RBF[rs2] = %.3f\n", load_double(rs3)); + double res; + res = load_double(rs1) * load_double(rs2) - load_double(rs3); + save_double(res, rd); + dbg_printf("Result = %.3f\n\n", res); +} + +// Instruction FNMSUB.D behavior method +void ac_behavior(FNMSUB_D) { + dbg_printf("FNMSUB.D r%d, r%d, r%d, r%d\n", rd, rs1, rs2, rs3); + dbg_printf("RBF[rs1] = %.3f\n", load_double(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_double(rs2)); + dbg_printf("RBF[rs2] = %.3f\n", load_double(rs3)); + double res; + res = (-(load_double(rs1) * load_double(rs2) - load_double(rs3))); + save_double(res, rd); + dbg_printf("Result = %.3f\n\n", res); +} + +// Instruction FNMADD.D behavior method +void ac_behavior(FNMADD_D) { + dbg_printf("FNMADD.D r%d, r%d, r%d, r%d\n", rd, rs1, rs2, rs3); + dbg_printf("RBF[rs1] = %.3f\n", load_double(rs1)); + dbg_printf("RBF[rs2] = %.3f\n", load_double(rs2)); + dbg_printf("RBF[rs2] = %.3f\n", load_double(rs3)); + double res; + res = (-(load_double(rs1) * load_double(rs2) + load_double(rs3))); + save_double(res, rd); + dbg_printf("Result = %.3f\n\n", res); +} + +// Instruction FCVT.W.D behavior method +void ac_behavior(FCVT_W_D) { + dbg_printf("FCVT.W.D r%d, r%d\n", rd, rs1); + dbg_printf("RBF[rs1] = %f\n", load_double(rs1)); + RB[rd] = lround(load_double(rs1)); + dbg_printf("RB[rd] = %d \n \n", RB[rd]); +} + +// Instruction FCVT.WU.D behavior method +void ac_behavior(FCVT_WU_D) { + dbg_printf("FCVT.WU.D r%d, r%d\n", rd, rs1); + dbg_printf("RBF[rs1] = %f\n", load_double(rs1)); + RB[rd] = (unsigned int)(load_double(rs1)); + dbg_printf("RB[rd] = %d \n \n", RB[rd]); +} + +// Instruction FCVT_D_W behaior method +void ac_behavior(FCVT_D_W) { + dbg_printf("FCVT.D.W r%d, r%d \n", rd, rs1); + dbg_printf("RB[rs1] = %d \n", RB[rs1]); + double temp; + temp = (double)RB[rs1]; + save_float(temp, rd); +} + +// Instruction FCVT_D_WU behaior method +void ac_behavior(FCVT_D_WU) { + dbg_printf("FCVT.D.W r%d, r%d \n", rd, rs1); + dbg_printf("RB[rs1] = %d \n", RB[rs1]); + double temp; + temp = (double)RB[rs1]; + save_double(temp, rd); +} + +// Instruction FCVT_S_D behavior method +void ac_behavior(FCVT_S_D) { + dbg_printf("FCVT.S.D r%d, r%d", rd, rs1); + dbg_printf("RBF[rs1] = %f \n", load_float(rs1)); + double temp; + temp = (float)(load_double(rs1)); + save_float(temp, rd); +} + +// Instruction FCVT_D_S behavior method +void ac_behavior(FCVT_D_S) { + dbg_printf("FCVT.D.S r%d, r%d", rd, rs1); + dbg_printf("RBF[rs1] = %f \n", load_double(rs1)); + float temp; + temp = (double)(load_float(rs1)); + save_double(temp, rd); +} + +// Instruction FMV.D behavior method +void ac_behavior(FMV_D) { + dbg_printf("FMV.D r%d, r%d", rd, rs1); + double temp; + temp = load_double(rs1); + save_double(temp, rd); +} + +// Instruction FEQ_D behavior method +void ac_behavior(FEQ_D) { + dbg_printf("FEQ.D r%d, r%d, r%d \n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %f \n", load_double(rs1)); + dbg_printf("RBF[rs2] = %f \n", load_double(rs2)); + if ((custom_isnan(load_double(rs1)) == 1) || + (custom_isnan(load_double(rs2)) == 1)) { + printf("Invalid Operation\n"); + RB[rd] = 0; + } + if (load_double(rs1) == load_double(rs2)) + RB[rd] = 1; + else + RB[rd] = 0; + dbg_printf("Result = %d \n \n", RB[rd]); +} + +// Instruction FLE_D behavior method +void ac_behavior(FLE_D) { + dbg_printf("FLE.D r%d, r%d, r%d \n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %f \n", load_double(rs1)); + dbg_printf("RBF[rs2] = %f \n", load_double(rs2)); + if ((custom_isnan(load_double(rs1)) == 1) || + (custom_isnan(load_double(rs2)) == 1)) { + printf("Invalid Operation\n"); + RB[rd] = 0; + } + if (load_double(rs1) <= load_double(rs2)) + RB[rd] = 1; + else + RB[rd] = 0; + dbg_printf("Result = %d \n \n", RB[rd]); +} + +// Instruction FLT_D behavior method +void ac_behavior(FLT_D) { + dbg_printf("FLT.D r%d, r%d, r%d \n", rd, rs1, rs2); + dbg_printf("RBF[rs1] = %f \n", load_double(rs1)); + dbg_printf("RBF[rs2] = %f \n", load_double(rs2)); + if ((custom_isnan(load_double(rs1)) == 1) || + (custom_isnan(load_double(rs2)) == 1)) { + printf("Invalid Operation\n"); + RB[rd] = 0; + } + if (load_double(rs1) < load_double(rs2)) + RB[rd] = 1; + else + RB[rd] = 0; + dbg_printf("Result = %d \n \n", RB[rd]); +} diff --git a/pdl/riscv/riscv_isa_helper.H b/pdl/riscv/riscv_isa_helper.H new file mode 100644 index 0000000..3ca9ccf --- /dev/null +++ b/pdl/riscv/riscv_isa_helper.H @@ -0,0 +1,51 @@ +/** + * @file riscv_isa_helper.H + * + * + * @version 1.0 + * @date August 2016 + * + * + * @brief This is a helper header file included directly + * in the generated riscv_isa.H file. Here we put + * data structures and functions used throughout + * the riscv_isa.cpp (riscv instruction behaviors). + **/ + + static inline int sign_extend(int word, int word_length){ + int sign_ext; + int m = 0xFFFFFFFF; + if((word>>(word_length-1) == 1)) + sign_ext = word | (m<> 32; +} + +inline float load_float(uint32_t index) { + float res; + memcpy(&res, &RBF[index], sizeof(uint32_t)); + return res; +} + +inline void save_float(float input, uint32_t index) { + memcpy(&RBF[index], &input, sizeof(uint32_t)); +} + +static bool custom_isnan(double var) { + return var != var; +} diff --git a/pdl/riscv/riscv_syscall.H b/pdl/riscv/riscv_syscall.H new file mode 100644 index 0000000..4e03a4b --- /dev/null +++ b/pdl/riscv/riscv_syscall.H @@ -0,0 +1,40 @@ +/****************************************************** + * ArchC Architecture Dependent Syscall header file. * + * This file is automatically generated by ArchC * + * WITHOUT WARRANTY OF ANY KIND, either express * + * or implied. * + * For more information on ArchC, please visit: * + * http://www.archc.org * + * * + * The ArchC Team * + * Computer Systems Laboratory (LSC) * + * IC-UNICAMP * + * http://www.lsc.ic.unicamp.br * + ******************************************************/ + + +#ifndef riscv_SYSCALL_H +#define riscv_SYSCALL_H + +#include "riscv_arch.H" +#include "riscv_arch_ref.H" +#include "riscv_parms.H" +#include "ac_syscall.H" + +//riscv system calls +class riscv_syscall : public ac_syscall, public riscv_arch_ref +{ +public: + riscv_syscall(riscv_arch& ref) : ac_syscall(ref, riscv_parms::AC_RAMSIZE), riscv_arch_ref(ref) {}; + virtual ~riscv_syscall() {}; + + void get_buffer(int argn, unsigned char* buf, unsigned int size); + void set_buffer(int argn, unsigned char* buf, unsigned int size); + void set_buffer_noinvert(int argn, unsigned char* buf, unsigned int size); + int get_int(int argn); + void set_int(int argn, int val); + void return_from_syscall(); + void set_prog_args(int argc, char **argv); +}; + +#endif diff --git a/pdl/riscv/riscv_syscall.cpp b/pdl/riscv/riscv_syscall.cpp new file mode 100644 index 0000000..fad75d1 --- /dev/null +++ b/pdl/riscv/riscv_syscall.cpp @@ -0,0 +1,92 @@ +/************************************************* +************************************************** +* @file riscv_syscall.cpp +* @author Dário Dias +* @email dsd@cin.ufpe.br +* @version 0.20 +* @date 8 July 2016 +* @brief The ArchC Risc-V functional model. +************************************************** +*************************************************/ + +#include "riscv_syscall.H" + +// 'using namespace' statement to allow access to all +// riscv-specific datatypes +using namespace riscv_parms; +unsigned procNumber = 0; + +void riscv_syscall::get_buffer(int argn, unsigned char* buf, unsigned int size) +{ + unsigned int addr = RB[10+argn]; + + for (unsigned int i = 0; i $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-FP/015.const/015.const.c b/pdl/riscv/tests/acstone-FP/015.const/015.const.c new file mode 100644 index 0000000..51f15b9 --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/015.const/015.const.c @@ -0,0 +1,70 @@ +/** + * @file 015.const.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses int and returns 0. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + float i; + i=0x55555555; + + + i=0xAAAAAAAA; + + + i=0x00000000; + + + i=0xFFFFFFFF; + + + i=0x80000000; + + + i=0x00000001; + + + i=0x7FFFFFFF; + + + i=0xFFFFFFFE; + + + return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-FP/015.const/Makefile b/pdl/riscv/tests/acstone-FP/015.const/Makefile new file mode 100644 index 0000000..c592ed0 --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/015.const/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 015.const +GCC_OPTS = -m32 -Wa,-march=RV32IMAFD -std=gnu99 +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IMAFD -std=gnu99 + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-FP/021.cast/021.cast.c b/pdl/riscv/tests/acstone-FP/021.cast/021.cast.c new file mode 100644 index 0000000..d4d2a0a --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/021.cast/021.cast.c @@ -0,0 +1,67 @@ +/** + * @file 021.cast.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main that uses cast signed char to signed short int. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + float si; + signed int c; + + si=0; + c=0x01; + si=c; + + si=0; + c=0xFF; + si=c; + + si=0; + c=0x80; + si=c; + + si=0; + c=0x7F; + si=c; + + si=0; + + return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-FP/021.cast/Makefile b/pdl/riscv/tests/acstone-FP/021.cast/Makefile new file mode 100644 index 0000000..533144c --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/021.cast/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 021.cast +GCC_OPTS = -m32 -Wa,-march=RV32IMAFD -std=gnu99 +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IMAFD -std=gnu99 + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-FP/027.cast/027.cast.c b/pdl/riscv/tests/acstone-FP/027.cast/027.cast.c new file mode 100644 index 0000000..61462aa --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/027.cast/027.cast.c @@ -0,0 +1,66 @@ +/** + * @file 027.cast.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main that uses some unsigned casts. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + float uli; + unsigned int ui; + unsigned short int usi; + unsigned char uc; + + uc=0xFF; + usi=0xFFFF; + usi=uc; + /* Before usi must be 225 */ usi=0; + + usi=0xFFFF; + ui=0xFFFFFFFF; + ui=usi; + /* Before ui must be 65535 */ ui=0; + + ui=0xFFFFFFFF; + uli=0xFFFFFFFFFFFFFFFFULL; + uli=ui; + uli=0; + + return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-FP/027.cast/Makefile b/pdl/riscv/tests/acstone-FP/027.cast/Makefile new file mode 100644 index 0000000..f3b3d40 --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/027.cast/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 027.cast +GCC_OPTS = -m32 -Wa,-march=RV32IMAFD -std=gnu99 +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IMAFD -std=gnu99 + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-FP/033.add/033.add.c b/pdl/riscv/tests/acstone-FP/033.add/033.add.c new file mode 100644 index 0000000..b12e1d9 --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/033.add/033.add.c @@ -0,0 +1,154 @@ +/** + * @file 033.add.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed and unsigned int adds. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + float a,b,c; + float d; + double ua,ub,uc; + double ud; + + a=0x0000FFFF; + b=0xFFFF0000; + c=a+b; + c=0; + + a=0xFFFFFFEC; + b=0xFFFFFFE2; + c=a+b; + c=0; + + a=0xFFFFFFFE; + b=0x00000002; + c=a+b; + c=0; + + a=0x0000000A; + b=0xFFFFFFFB; + c=a+b; + c=0; + + a=0x00000005; + b=0xFFFFFFF6; + c=a+b; + c=0; + + a=0x0F0F0F0F; + b=0xF0F0F0F0; + c=a+b; + c=0; + + a=0xAAAAAAAA; + b=0x55555555; + c=a+b; + c=0; + + d=0; + d+=1; + d+=2; + d+=3; + d+=4; + d+=5; + d=0; + + + ua=0x0000FFFF; + ub=0xFFFF0000; + uc=ua+ub; + /* Before uc must be 4294967295 */ uc=0; + + ua=0xFFFFFFEC; + ub=0xFFFFFFE2; + uc=ua+ub; + /* Before uc must be 4294967246 */ uc=0; + + ua=0xFFFFFFFE; + ub=0x00000002; + uc=ua+ub; + /* Before uc must be 0 */ uc=0; + + ua=0x0000000A; + ub=0xFFFFFFFB; + uc=ua+ub; + /* Before uc must be 5 */ uc=0; + + ua=0x00000005; + ub=0xFFFFFFF6; + uc=ua+ub; + /* Before uc must be 4294967291 */ uc=0; + + ua=0x0F0F0F0F; + ub=0xF0F0F0F0; + uc=ua+ub; + /* Before uc must be 4294967295 */ uc=0; + + ua=0xAAAAAAAA; + ub=0x55555555; + uc=ua+ub; + /* Before uc must be 4294967295 */ uc=0; + + ud=0; + ud+=1; + ud+=2; + ud+=3; + ud+=4; + ud+=5; + /* Before ud must be 15 */ ud=0; + + d=15; + d+=0xFFFFFFFF; + d+=0xFFFFFFFE; + d+=0xFFFFFFFD; + d+=0xFFFFFFFC; + d+=0xFFFFFFFB; + d=0; + + ud=15; + ud+=0xFFFFFFFF; + ud+=0xFFFFFFFE; + ud+=0xFFFFFFFD; + ud+=0xFFFFFFFC; + ud+=0xFFFFFFFB; + /* Before ud must be 0 */ ud=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-FP/033.add/Makefile b/pdl/riscv/tests/acstone-FP/033.add/Makefile new file mode 100644 index 0000000..bbcf9e7 --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/033.add/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 033.add +GCC_OPTS = -m32 -Wa,-march=RV32IMAFD -std=gnu99 +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IMAFD -std=gnu99 + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-FP/041.sub/041.sub.c b/pdl/riscv/tests/acstone-FP/041.sub/041.sub.c new file mode 100644 index 0000000..10215e6 --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/041.sub/041.sub.c @@ -0,0 +1,154 @@ +/** + * @file 041.sub.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses signed and unsigned char subs. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + float a,b,c; + float d; + unsigned char ua,ub,uc; + unsigned char ud; + + a=0x0A; + b=0x14; + c=a-b; + c=0; + + a=0xEC; + b=0xE2; + c=a-b; + c=0; + + a=0xFE; + b=0x02; + c=a-b; + c=0; + + a=0x0A; + b=0xFB; + c=a-b; + c=0; + + a=0x05; + b=0xF6; + c=a-b; + c=0; + + a=0x0F; + b=0xF0; + c=a-b; + c=0; + + a=0xAA; + b=0x55; + c=a-b; + c=0; + + d=15; + d-=1; + d-=2; + d-=3; + d-=4; + d-=5; + d=0; + + + ua=0x0A; + ub=0x14; + uc=ua-ub; + /* Before uc must be 246 */ uc=0; + + ua=0xEC; + ub=0xE2; + uc=ua-ub; + /* Before uc must be 10 */ uc=0; + + ua=0xFE; + ub=0x02; + uc=ua-ub; + /* Before uc must be 252 */ uc=0; + + ua=0x0A; + ub=0xFB; + uc=ua-ub; + /* Before uc must be 15 */ uc=0; + + ua=0x05; + ub=0xF6; + uc=ua-ub; + /* Before uc must be 15 */ uc=0; + + ua=0x0F; + ub=0xF0; + uc=ua-ub; + /* Before uc must be 31 */ uc=0; + + ua=0xAA; + ub=0x55; + uc=ua-ub; + /* Before uc must be 85 */ uc=0; + + ud=15; + ud-=1; + ud-=2; + ud-=3; + ud-=4; + ud-=5; + /* Before ud must be 0 */ ud=0; + + d=0; + d-=0xFF; + d-=0xFE; + d-=0xFD; + d-=0xFC; + d-=0xFB; + d=0; + + ud=0; + ud-=0xFF; + ud-=0xFE; + ud-=0xFD; + ud-=0xFC; + ud-=0xFB; + /* Before ud must be 15 */ ud=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-FP/041.sub/Makefile b/pdl/riscv/tests/acstone-FP/041.sub/Makefile new file mode 100644 index 0000000..ec4870d --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/041.sub/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 041.sub +GCC_OPTS = -m32 -Wa,-march=RV32IMAFD -std=gnu99 +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IMAFD -std=gnu99 + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-FP/057.mul/057.mul.c b/pdl/riscv/tests/acstone-FP/057.mul/057.mul.c new file mode 100644 index 0000000..7a66a75 --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/057.mul/057.mul.c @@ -0,0 +1,106 @@ +/** + * @file 057.mul.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function uses various signed multiplication. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + float c1,c2,c3,c4,c5,cresult; + signed short int si1,si2,si3,si4,si5,siresult; + double i1,i2,i3,i4,i5,iresult; + long double li1,li2,li3,li4,li5,liresult; + + c1=1; + c2=2; + c3=3; + c4=4; + c5=5; + cresult=c1*c2*c3*c4*c5; + cresult=0; + + si1=1; + si2=2; + si3=3; + si4=4; + si5=5; + siresult=si1*si2*si3*si4*si5; + /* Before siresult must be 120 */ siresult=0; + + i1=1; + i2=2; + i3=3; + i4=4; + i5=5; + iresult=i1*i2*i3*i4*i5; + /* Before iresult must be 120 */ iresult=0; + + li1=1; + li2=2; + li3=3; + li4=4; + li5=5; + liresult=li1*li2*li3*li4*li5; + /* Before liresult must be 120 */ liresult=0; + + c1=5; + siresult=c1*7; + /* Before siresult must be 35 */ siresult=0; + + si1=5; + iresult=si1*7; + /* Before iresult must be 35 */ iresult=0; + + i1=5; + liresult=i1*7; + /* Before liresult must be 35 */ liresult=0; + + c1=17; + siresult=c1*(-1); + /* Before siresult must be -17 */ siresult=0; + + si1=17; + iresult=si1*(-1); + /* Before iresult must be -17 */ iresult=0; + + i1=17; + liresult=i1*(-1); + /* Before siresult must be -17 */ liresult=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-FP/057.mul/Makefile b/pdl/riscv/tests/acstone-FP/057.mul/Makefile new file mode 100644 index 0000000..3517ad2 --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/057.mul/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 057.mul +GCC_OPTS = -m32 -Wa,-march=RV32IMAFD -std=gnu99 +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IMAFD -std=gnu99 + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-FP/061.div/061.div.c b/pdl/riscv/tests/acstone-FP/061.div/061.div.c new file mode 100644 index 0000000..f137647 --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/061.div/061.div.c @@ -0,0 +1,109 @@ +/** + * @file 061.div.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed char division. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + float a,b,c; + + a=0xFF; + b=0x01; + c=a/b; + c=0; + + a=0x0F; + b=0x03; + c=a/b; + c=0; + + a=0xAA; + b=0x55; + c=a/b; + c=0; + + a=0x7F; + b=0xFF; + c=a/b; + c=0; + + a=0x00; + b=0x80; + c=a/b; + c=0; + + a=0x30; + b=0x05; + c=a/b; + c=0; + + a=0xFF; + b=0xFF; + c=a/b; + c=0; + + a=0xFE; + b=0x10; + c=a/b; + c=0; + + a=0x20; + b=0xFE; + c=a/b; + c=0; + + a=0x00; + b=0xFF; + c=a/b; + c=0; + + a=0x78; + c=a/5; + c=c/4; + c=c/3; + c=c/2; + c=0; + + a=0x10; + c=a/(-1); + c=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-FP/061.div/Makefile b/pdl/riscv/tests/acstone-FP/061.div/Makefile new file mode 100644 index 0000000..46efd7c --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/061.div/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 061.div +GCC_OPTS = -m32 -Wa,-march=RV32IMAFD -std=gnu99 +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IMAFD -std=gnu99 + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-FP/065.div/065.div.c b/pdl/riscv/tests/acstone-FP/065.div/065.div.c new file mode 100644 index 0000000..6b8a1b5 --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/065.div/065.div.c @@ -0,0 +1,109 @@ +/** + * @file 065.div.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed int division. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + float a,b,c; + + a=0xFFFFFFFF; + b=0x00000001; + c=a/b; + c=0; + + a=0x0000000F; + b=0x00000003; + c=a/b; + c=0; + + a=0xAAAAAAAA; + b=0x55555555; + c=a/b; + c=0; + + a=0x7FFFFFFF; + b=0xFFFFFFFF; + c=a/b; + c=0; + + a=0x00000000; + b=0x80000000; + c=a/b; + c=0; + + a=0x00000030; + b=0x00000005; + c=a/b; + c=0; + + a=0xFFFFFFFF; + b=0xFFFFFFFF; + c=a/b; + c=0; + + a=0xFFFFFFFE; + b=0x00000010; + c=a/b; + c=0; + + a=0x00000020; + b=0xFFFFFFFE; + c=a/b; + c=0; + + a=0x00000000; + b=0xFFFFFFFF; + c=a/b; + c=0; + + a=0x00000078; + c=a/5; + c=c/4; + c=c/3; + c=c/2; + c=0; + + a=0x10000000; + c=a/(-1); + c=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-FP/065.div/Makefile b/pdl/riscv/tests/acstone-FP/065.div/Makefile new file mode 100644 index 0000000..0553963 --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/065.div/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 065.div +GCC_OPTS = -m32 -Wa,-march=RV32IMAFD -std=gnu99 +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IMAFD -std=gnu99 + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-FP/111.if/111.if.c b/pdl/riscv/tests/acstone-FP/111.if/111.if.c new file mode 100644 index 0000000..1748a19 --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/111.if/111.if.c @@ -0,0 +1,244 @@ +/** + * @file 111.if.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses signed char ifs + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + float a,b; + unsigned char c_active_else,c_inactive_else; + unsigned char c_active_then,c_inactive_then; + + c_active_then=0; + c_active_else=0; + c_inactive_then=0; + c_inactive_else=0; + + a=0x00; + b=0xFF; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0xFF; + b=0xFE; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x01; + b=0x02; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + a=0x0F; + b=0x0F; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 3 */ c_active_then=0; + /* Before, c_active_else must be 2 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x01; + b=0xFF; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-FP/111.if/Makefile b/pdl/riscv/tests/acstone-FP/111.if/Makefile new file mode 100644 index 0000000..b24e1ff --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/111.if/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 111.if +GCC_OPTS = -m32 -Wa,-march=RV32IMAFD -std=gnu99 +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IMAFD -std=gnu99 + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-FP/132.call/132.call.c b/pdl/riscv/tests/acstone-FP/132.call/132.call.c new file mode 100644 index 0000000..e0e57f4 --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/132.call/132.call.c @@ -0,0 +1,141 @@ +/** + * @file 132.call.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses indirect calls functions. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* Declarations */ +float funcA(float input); +float funcB(float input); +float funcC(float input); +float funcD(float input); +float funcE(float input); +float funcF(float input); +float funcG(float input); +float funcH(float input); + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + float tmp=0; + tmp=funcA(-1); + tmp=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif + +float count=0; + +float funcA(float input) { + float a=-2; + funcB(input); + count++; + a++; + return input; +} + + + +float funcB(float input) { + float b=0; + funcC(input); + count++; + b++; + return input; +} + + + +float funcC(float input) { + float c=-1; + funcD(input); + count++; + c++; + return input; +} + + + +float funcD(float input) { + float d=9; + funcE(input); + count++; + d++; + return input; +} + + + +float funcE(float input) { + float e=-1; + funcF(input); + count++; + e++; + return input; +} + + + +float funcF(float input) { + float f=14; + funcG(input); + count++; + f++; + return input; +} + + + +float funcG(float input) { + float g=-2; + funcH(input); + count++; + g++; + return input; +} + + + +float funcH(float input) { + float h=1; + count++; + h++; + + return input; +} + diff --git a/pdl/riscv/tests/acstone-FP/132.call/Makefile b/pdl/riscv/tests/acstone-FP/132.call/Makefile new file mode 100644 index 0000000..6e04f6d --- /dev/null +++ b/pdl/riscv/tests/acstone-FP/132.call/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 132.call +GCC_OPTS = -m32 -Wa,-march=RV32IMAFD -std=gnu99 +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IMAFD -std=gnu99 + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/000.main/000.main.c b/pdl/riscv/tests/acstone-programs/000.main/000.main.c new file mode 100644 index 0000000..2e3c110 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/000.main/000.main.c @@ -0,0 +1,45 @@ +/** + * @file 000.main.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that returns 0. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/000.main/Makefile b/pdl/riscv/tests/acstone-programs/000.main/Makefile new file mode 100644 index 0000000..6bb3bae --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/000.main/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 000.main +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/011.const/011.const.c b/pdl/riscv/tests/acstone-programs/011.const/011.const.c new file mode 100644 index 0000000..fe6315f --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/011.const/011.const.c @@ -0,0 +1,71 @@ +/** + * @file 011.const.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed char and returns 0. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + signed char c; + + c=0x55; + /* After c is 85 */ + + /* Before c is 85 */ c=0xAA; + /* After c is -86 */ + + /* Before c is -86 */ c=0x00; + /* After c is 0 */ + + /* Before c is 0 */ c=0xFF; + /* After c is -1 */ + + /* Before c is -1 */ c=0x80; + /* After c is -128 */ + + /* Before c is -128 */ c=0x01; + /* After c is 1 */ + + /* Before c is 1 */ c=0x7F; + /* After c is 127 */ + + /* Before c is 127 */ c=0xFE; + /* After c is -2 */ + + /* Before c is -2 */ return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/011.const/Makefile b/pdl/riscv/tests/acstone-programs/011.const/Makefile new file mode 100644 index 0000000..dc99256 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/011.const/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 011.const +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/012.const/012.const.c b/pdl/riscv/tests/acstone-programs/012.const/012.const.c new file mode 100644 index 0000000..2924321 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/012.const/012.const.c @@ -0,0 +1,71 @@ +/** + * @file 012.const.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses unsigned char and returns 0. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + unsigned char uc; + + uc=0x55; + /* After uc is 85 */ + + /* Before uc is 85 */ uc=0xAA; + /* After uc is 170 */ + + /* Before uc is 170 */ uc=0x00; + /* After uc is 0 */ + + /* Before uc is 0 */ uc=0xFF; + /* After uc is 255 */ + + /* Before uc is 255 */ uc=0x80; + /* After uc is 128 */ + + /* Before uc is 128 */ uc=0x01; + /* After uc is 1 */ + + /* Before uc is 1 */ uc=0x7F; + /* After uc is 127 */ + + /* Before uc is 127 */ uc=0xFE; + /* After uc is 254 */ + + /* Before uc is 254 */ return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/012.const/Makefile b/pdl/riscv/tests/acstone-programs/012.const/Makefile new file mode 100644 index 0000000..db21655 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/012.const/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 012.const +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/013.const/013.const.c b/pdl/riscv/tests/acstone-programs/013.const/013.const.c new file mode 100644 index 0000000..cb1c3f3 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/013.const/013.const.c @@ -0,0 +1,71 @@ +/** + * @file 013.const.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed short int and returns 0. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + signed short int si; + + si=0x5555; + /* After si is 21845 */ + + /* Before si is 21845 */ si=0xAAAA; + /* After si is -21846 */ + + /* Before si is -21846 */ si=0x0000; + /* After si is 0 */ + + /* Before si is 0 */ si=0xFFFF; + /* After si is -1 */ + + /* Before si is -1 */ si=0x8000; + /* After si is -32768 */ + + /* Before si is -32768 */ si=0x0001; + /* After si is 1 */ + + /* Before si is 1 */ si=0x7FFF; + /* After si is 32767 */ + + /* Before si is 32767 */ si=0xFFFE; + /* After si is -2 */ + + /* Before si is -2 */ return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/013.const/Makefile b/pdl/riscv/tests/acstone-programs/013.const/Makefile new file mode 100644 index 0000000..bc6444e --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/013.const/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 013.const +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/014.const/014.const.c b/pdl/riscv/tests/acstone-programs/014.const/014.const.c new file mode 100644 index 0000000..d2355d1 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/014.const/014.const.c @@ -0,0 +1,71 @@ +/** + * @file 014.const.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses unsigned short int and returns 0. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + unsigned short int usi; + + usi=0x5555; + /* After usi is 21845 */ + + /* Before usi is 21845 */ usi=0xAAAA; + /* After usi is 43690 */ + + /* Before usi is 43690 */ usi=0x0000; + /* After usi is 0 */ + + /* Before usi is 0 */ usi=0xFFFF; + /* After usi is 65535 */ + + /* Before usi is 65535 */ usi=0x8000; + /* After usi is 32768 */ + + /* Before usi is 32768 */ usi=0x0001; + /* After usi is 1 */ + + /* Before usi is 1 */ usi=0x7FFF; + /* After usi is 32767 */ + + /* Before usi is 32767 */ usi=0xFFFE; + /* After usi is 65534 */ + + /* Before usi is 65534 */ return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/014.const/Makefile b/pdl/riscv/tests/acstone-programs/014.const/Makefile new file mode 100644 index 0000000..ba7bc93 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/014.const/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 014.const +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/015.const/015.const.c b/pdl/riscv/tests/acstone-programs/015.const/015.const.c new file mode 100644 index 0000000..e0041e3 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/015.const/015.const.c @@ -0,0 +1,70 @@ +/** + * @file 015.const.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses int and returns 0. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + signed int i; + i=0x55555555; + /* After i is 1431655765 */ + + /* Before i is 1431655765 */ i=0xAAAAAAAA; + /* After i is -1431655766 */ + + /* Before i is -1431655766 */ i=0x00000000; + /* After i is 0 */ + + /* Before i is 0 */ i=0xFFFFFFFF; + /* After i is -1 */ + + /* Before i is -1 */ i=0x80000000; + /* After i is -2147483648 */ + + /* Before i is -2147483648 */ i=0x00000001; + /* After i is 1 */ + + /* Before i is 1 */ i=0x7FFFFFFF; + /* After i is 2147483647 */ + + /* Before i is 2147483647 */ i=0xFFFFFFFE; + /* After i is -2 */ + + /* Before i is -2 */ return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/015.const/Makefile b/pdl/riscv/tests/acstone-programs/015.const/Makefile new file mode 100644 index 0000000..edafc69 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/015.const/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 015.const +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/016.const/016.const.c b/pdl/riscv/tests/acstone-programs/016.const/016.const.c new file mode 100644 index 0000000..5b1a7d3 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/016.const/016.const.c @@ -0,0 +1,71 @@ +/** + * @file 016.const.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses unsigned int and returns 0. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + unsigned int ui; + + ui=0x55555555; + /* After ui is 1431655765 */ + + /* Before ui is 1431655765 */ ui=0xAAAAAAAA; + /* After ui is 2863311530 */ + + /* Before ui is 2863311530 */ ui=0x00000000; + /* After ui is 0 */ + + /* Before ui is 0 */ ui=0xFFFFFFFF; + /* After ui is 4294967295 */ + + /* Before ui is 4294967295 */ ui=0x80000000; + /* After ui is 2147483648 */ + + /* Before ui is 2147483648 */ ui=0x00000001; + /* After ui is 1 */ + + /* Before ui is 1 */ ui=0x7FFFFFFF; + /* After ui is 2147483647 */ + + /* Before ui is 2147483647 */ ui=0xFFFFFFFE; + /* After ui is 4294967294 */ + + /* Before ui is 4294967294 */ return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/016.const/Makefile b/pdl/riscv/tests/acstone-programs/016.const/Makefile new file mode 100644 index 0000000..43fac7e --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/016.const/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 016.const +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/017.const/017.const.c b/pdl/riscv/tests/acstone-programs/017.const/017.const.c new file mode 100644 index 0000000..165052f --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/017.const/017.const.c @@ -0,0 +1,71 @@ +/** + * @file 017.const.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed long long int and returns 0. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + signed long long int li; + + li=0x5555555555555555LL; + /* After li is 6148914691236517205 */ + + /* Before li is 6148914691236517205 */ li=0xAAAAAAAAAAAAAAAALL; + /* After li is -6148914691236517206 */ + + /* Before li is -6148914691236517206 */ li=0x0000000000000000LL; + /* After li is 0 */ + + /* Before li is 0 */ li=0xFFFFFFFFFFFFFFFFLL; + /* After li is -1 */ + + /* Before li is -1 */ li=0x8000000000000000LL; + /* After li is -9223372036854775808 */ + + /* Before li is -9223372036854775808 */ li=0x0000000000000001LL; + /* After li is 1 */ + + /* Before li is 1 */ li=0x7FFFFFFFFFFFFFFFLL; + /* After li is 9223372036854775807 */ + + /* Before li is 9223372036854775807 */ li=0xFFFFFFFFFFFFFFFELL; + /* After li is -2 * / + + /* Before li is -2 */ return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/017.const/Makefile b/pdl/riscv/tests/acstone-programs/017.const/Makefile new file mode 100644 index 0000000..0fb4314 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/017.const/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 017.const +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/018.const/018.const.c b/pdl/riscv/tests/acstone-programs/018.const/018.const.c new file mode 100644 index 0000000..64a952d --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/018.const/018.const.c @@ -0,0 +1,71 @@ +/** + * @file 018.const.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses unsigned long long int and returns 0. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + unsigned long long int uli; + + uli=0x5555555555555555ULL; + /* After uli is 6148914691236517205 */ + + /* Before uli is 6148914691236517205 */ uli=0xAAAAAAAAAAAAAAAAULL; + /* After uli is 12297829382473034410 */ + + /* Before uli is 12297829382473034410 */ uli=0x0000000000000000ULL; + /* After uli is 0 */ + + /* Before uli is 0 */ uli=0xFFFFFFFFFFFFFFFFULL; + /* After uli is 18446744073709551615 */ + + /* Before uli is 18446744073709551615 */ uli=0x8000000000000000ULL; + /* After uli is 9223372036854775808 */ + + /* Before uli is 9223372036854775808 */ uli=0x0000000000000001ULL; + /* After uli is 1 */ + + /* Before uli is 1 */ uli=0x7FFFFFFFFFFFFFFFULL; + /* After uli is 9223372036854775807 */ + + /* Before uli is 9223372036854775807 */ uli=0xFFFFFFFFFFFFFFFEULL; + /* After uli is 18446744073709551614 * / + + /* Before uli is 18446744073709551614 */ return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/018.const/Makefile b/pdl/riscv/tests/acstone-programs/018.const/Makefile new file mode 100644 index 0000000..1e476d0 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/018.const/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 018.const +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/021.cast/021.cast.c b/pdl/riscv/tests/acstone-programs/021.cast/021.cast.c new file mode 100644 index 0000000..07f1e9e --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/021.cast/021.cast.c @@ -0,0 +1,67 @@ +/** + * @file 021.cast.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main that uses cast signed char to signed short int. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed short int si; + signed char c; + + si=0; + c=0x01; + si=c; + + /* Before si must be 1 */ si=0; + c=0xFF; + si=c; + + /* Before si must be -1 */ si=0; + c=0x80; + si=c; + + /* Before si must be -128 */ si=0; + c=0x7F; + si=c; + + /* Before si must be 127 */ si=0; + + return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/021.cast/Makefile b/pdl/riscv/tests/acstone-programs/021.cast/Makefile new file mode 100644 index 0000000..0a61fa2 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/021.cast/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 021.cast +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/022.cast/022.cast.c b/pdl/riscv/tests/acstone-programs/022.cast/022.cast.c new file mode 100644 index 0000000..a7bc018 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/022.cast/022.cast.c @@ -0,0 +1,67 @@ +/** + * @file 022.cast.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main that uses cast signed char to signed int. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed int i; + signed char c; + + i=0; + c=0x01; + i=c; + + /* Before i must be 1 */ i=0; + c=0xFF; + i=c; + + /* Before i must be -1 */ i=0; + c=0x80; + i=c; + + /* Before i must be -128 */ i=0; + c=0x7F; + i=c; + + /* Before i must be 127 */ i=0; + + return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/022.cast/Makefile b/pdl/riscv/tests/acstone-programs/022.cast/Makefile new file mode 100644 index 0000000..66d2015 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/022.cast/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 022.cast +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/023.cast/023.cast.c b/pdl/riscv/tests/acstone-programs/023.cast/023.cast.c new file mode 100644 index 0000000..ad30da3 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/023.cast/023.cast.c @@ -0,0 +1,67 @@ +/** + * @file 023.cast.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main that uses cast signed char to signed long long int. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed long long int li; + signed char c; + + li=0; + c=0x01; + li=c; + + /* Before li must be 1 */ li=0; + c=0xFF; + li=c; + + /* Before li must be -1 */ li=0; + c=0x80; + li=c; + + /* Before li must be -128 */ li=0; + c=0x7F; + li=c; + + /* Before li must be 127 */ li=0; + + return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/023.cast/Makefile b/pdl/riscv/tests/acstone-programs/023.cast/Makefile new file mode 100644 index 0000000..5ea44d6 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/023.cast/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 023.cast +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/024.cast/024.cast.c b/pdl/riscv/tests/acstone-programs/024.cast/024.cast.c new file mode 100644 index 0000000..f7d8ba6 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/024.cast/024.cast.c @@ -0,0 +1,67 @@ +/** + * @file 024.cast.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main that uses cast signed short int to signed int. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed int i; + signed short int si; + + i=0; + si=0x0001; + i=si; + + /* Before i must be 1 */ i=0; + si=0xFFFF; + i=si; + + /* Before i must be -1 */ i=0; + si=0x8000; + i=si; + + /* Before i must be -32768 */ i=0; + si=0x7FFF; + i=si; + + /* Before i must be 32767 */ i=0; + + return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/024.cast/Makefile b/pdl/riscv/tests/acstone-programs/024.cast/Makefile new file mode 100644 index 0000000..4a04b3c --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/024.cast/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 024.cast +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/025.cast/025.cast.c b/pdl/riscv/tests/acstone-programs/025.cast/025.cast.c new file mode 100644 index 0000000..407ab54 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/025.cast/025.cast.c @@ -0,0 +1,67 @@ +/** + * @file 025.cast.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main that uses cast signed short int to signed long long int. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed long long int li; + signed short int si; + + li=0; + si=0x0001; + li=si; + + /* Before li must be 1 */ li=0; + si=0xFFFF; + li=si; + + /* Before li must be -1 */ li=0; + si=0x8000; + li=si; + + /* Before li must be -32768 */ li=0; + si=0x7FFF; + li=si; + + /* Before li must be 32767 */ li=0; + + return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/025.cast/Makefile b/pdl/riscv/tests/acstone-programs/025.cast/Makefile new file mode 100644 index 0000000..647adc5 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/025.cast/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 025.cast +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/026.cast/026.cast.c b/pdl/riscv/tests/acstone-programs/026.cast/026.cast.c new file mode 100644 index 0000000..39b36be --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/026.cast/026.cast.c @@ -0,0 +1,67 @@ +/** + * @file 026.cast.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main that uses cast signed int to signed long long int. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed long long int li; + signed int i; + + li=0; + i=0x00000001; + li=i; + + /* Before li must be 1 */ li=0; + i=0xFFFFFFFF; + li=i; + + /* Before li must be -1 */ li=0; + i=0x80000000; + li=i; + + /* Before li must be -2147483648 */ li=0; + i=0x7FFFFFFF; + li=i; + + /* Before li must be 2147483647 */ li=0; + + return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/026.cast/Makefile b/pdl/riscv/tests/acstone-programs/026.cast/Makefile new file mode 100644 index 0000000..0e6c0b7 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/026.cast/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 026.cast +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/027.cast/027.cast.c b/pdl/riscv/tests/acstone-programs/027.cast/027.cast.c new file mode 100644 index 0000000..a5c58cc --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/027.cast/027.cast.c @@ -0,0 +1,66 @@ +/** + * @file 027.cast.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main that uses some unsigned casts. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned long long int uli; + unsigned int ui; + unsigned short int usi; + unsigned char uc; + + uc=0xFF; + usi=0xFFFF; + usi=uc; + /* Before usi must be 225 */ usi=0; + + usi=0xFFFF; + ui=0xFFFFFFFF; + ui=usi; + /* Before ui must be 65535 */ ui=0; + + ui=0xFFFFFFFF; + uli=0xFFFFFFFFFFFFFFFFULL; + uli=ui; + /* Before uli must be 4294967295 */ uli=0; + + return 0; + /* Return 0 */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/027.cast/Makefile b/pdl/riscv/tests/acstone-programs/027.cast/Makefile new file mode 100644 index 0000000..5a8dee8 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/027.cast/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 027.cast +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/031.add/031.add.c b/pdl/riscv/tests/acstone-programs/031.add/031.add.c new file mode 100644 index 0000000..2a90fbb --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/031.add/031.add.c @@ -0,0 +1,154 @@ +/** + * @file 031.add.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed and unsigned char adds. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed char a,b,c; + signed char d; + unsigned char ua,ub,uc; + unsigned char ud; + + a=0x0A; + b=0x14; + c=a+b; + /* Before c must be 30 */ c=0; + + a=0xEC; + b=0xE2; + c=a+b; + /* Before c must be -50 */ c=0; + + a=0xFE; + b=0x02; + c=a+b; + /* Before c must be 0 */ c=0; + + a=0x0A; + b=0xFB; + c=a+b; + /* Before c must be 5 */ c=0; + + a=0x05; + b=0xF6; + c=a+b; + /* Before c must be -5 */ c=0; + + a=0x0F; + b=0xF0; + c=a+b; + /* Before c must be -1 */ c=0; + + a=0xAA; + b=0x55; + c=a+b; + /* Before c must be -1 */ c=0; + + d=0; + d+=1; + d+=2; + d+=3; + d+=4; + d+=5; + /* Before d must be 15 */ d=0; + + + ua=0x0A; + ub=0x14; + uc=ua+ub; + /* Before uc must be 30 */ uc=0; + + ua=0xEC; + ub=0xE2; + uc=ua+ub; + /* Before uc must be 206 */ uc=0; + + ua=0xFE; + ub=0x02; + uc=ua+ub; + /* Before uc must be 0 */ uc=0; + + ua=0x0A; + ub=0xFB; + uc=ua+ub; + /* Before uc must be 5 */ uc=0; + + ua=0x05; + ub=0xF6; + uc=ua+ub; + /* Before uc must be 251 */ uc=0; + + ua=0x0F; + ub=0xF0; + uc=ua+ub; + /* Before uc must be 255 */ uc=0; + + ua=0xAA; + ub=0x55; + uc=ua+ub; + /* Before uc must be 255 */ uc=0; + + ud=0; + ud+=1; + ud+=2; + ud+=3; + ud+=4; + ud+=5; + /* Before ud must be 15 */ ud=0; + + d=15; + d+=0xFF; + d+=0xFE; + d+=0xFD; + d+=0xFC; + d+=0xFB; + /* Before d must be 0 */ d=0; + + ud=15; + ud+=0xFF; + ud+=0xFE; + ud+=0xFD; + ud+=0xFC; + ud+=0xFB; + /* Before ud must be 0 */ ud=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/031.add/031.add.c~ b/pdl/riscv/tests/acstone-programs/031.add/031.add.c~ new file mode 100644 index 0000000..30dc193 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/031.add/031.add.c~ @@ -0,0 +1,154 @@ +/** + * @file 031.add.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed and unsigned char adds. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed float a,b,c; + signed float d; + unsigned float ua,ub,uc; + unsigned float ud; + + a=0x0A; + b=0x14; + c=a+b; + /* Before c must be 30 */ c=0; + + a=0xEC; + b=0xE2; + c=a+b; + /* Before c must be -50 */ c=0; + + a=0xFE; + b=0x02; + c=a+b; + /* Before c must be 0 */ c=0; + + a=0x0A; + b=0xFB; + c=a+b; + /* Before c must be 5 */ c=0; + + a=0x05; + b=0xF6; + c=a+b; + /* Before c must be -5 */ c=0; + + a=0x0F; + b=0xF0; + c=a+b; + /* Before c must be -1 */ c=0; + + a=0xAA; + b=0x55; + c=a+b; + /* Before c must be -1 */ c=0; + + d=0; + d+=1; + d+=2; + d+=3; + d+=4; + d+=5; + /* Before d must be 15 */ d=0; + + + ua=0x0A; + ub=0x14; + uc=ua+ub; + /* Before uc must be 30 */ uc=0; + + ua=0xEC; + ub=0xE2; + uc=ua+ub; + /* Before uc must be 206 */ uc=0; + + ua=0xFE; + ub=0x02; + uc=ua+ub; + /* Before uc must be 0 */ uc=0; + + ua=0x0A; + ub=0xFB; + uc=ua+ub; + /* Before uc must be 5 */ uc=0; + + ua=0x05; + ub=0xF6; + uc=ua+ub; + /* Before uc must be 251 */ uc=0; + + ua=0x0F; + ub=0xF0; + uc=ua+ub; + /* Before uc must be 255 */ uc=0; + + ua=0xAA; + ub=0x55; + uc=ua+ub; + /* Before uc must be 255 */ uc=0; + + ud=0; + ud+=1; + ud+=2; + ud+=3; + ud+=4; + ud+=5; + /* Before ud must be 15 */ ud=0; + + d=15; + d+=0xFF; + d+=0xFE; + d+=0xFD; + d+=0xFC; + d+=0xFB; + /* Before d must be 0 */ d=0; + + ud=15; + ud+=0xFF; + ud+=0xFE; + ud+=0xFD; + ud+=0xFC; + ud+=0xFB; + /* Before ud must be 0 */ ud=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/031.add/Makefile b/pdl/riscv/tests/acstone-programs/031.add/Makefile new file mode 100644 index 0000000..ed65387 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/031.add/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 031.add +GCC_OPTS = -m32 -Wa,-march=RV32IMAF -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IMAF -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/032.add/032.add.c b/pdl/riscv/tests/acstone-programs/032.add/032.add.c new file mode 100644 index 0000000..6fb5594 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/032.add/032.add.c @@ -0,0 +1,154 @@ +/** + * @file 032.add.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses signed and unsigned short int adds. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed short int a,b,c; + signed short int d; + unsigned short int ua,ub,uc; + unsigned short int ud; + + a=0x00FF; + b=0xFF00; + c=a+b; + /* Before c must be -1 */ c=0; + + a=0xFFEC; + b=0xFFE2; + c=a+b; + /* Before c must be -50 */ c=0; + + a=0xFFFE; + b=0x0002; + c=a+b; + /* Before c must be 0 */ c=0; + + a=0x000A; + b=0xFFFB; + c=a+b; + /* Before c must be 5 */ c=0; + + a=0x0005; + b=0xFFF6; + c=a+b; + /* Before c must be -5 */ c=0; + + a=0x0F0F; + b=0xF0F0; + c=a+b; + /* Before c must be -1 */ c=0; + + a=0xAAAA; + b=0x5555; + c=a+b; + /* Before c must be -1 */ c=0; + + d=0; + d+=1; + d+=2; + d+=3; + d+=4; + d+=5; + /* Before d must be 15 */ d=0; + + + ua=0x00FF; + ub=0xFF00; + uc=ua+ub; + /* Before uc must be 65535 */ uc=0; + + ua=0xFFEC; + ub=0xFFE2; + uc=ua+ub; + /* Before uc must be 65486 */ uc=0; + + ua=0xFFFE; + ub=0x0002; + uc=ua+ub; + /* Before uc must be 0 */ uc=0; + + ua=0x000A; + ub=0xFFFB; + uc=ua+ub; + /* Before uc must be 5 */ uc=0; + + ua=0x0005; + ub=0xFFF6; + uc=ua+ub; + /* Before uc must be 65531 */ uc=0; + + ua=0x0F0F; + ub=0xF0F0; + uc=ua+ub; + /* Before uc must be 65535 */ uc=0; + + ua=0xAAAA; + ub=0x5555; + uc=ua+ub; + /* Before uc must be 65535 */ uc=0; + + ud=0; + ud+=1; + ud+=2; + ud+=3; + ud+=4; + ud+=5; + /* Before ud must be 15 */ ud=0; + + d=15; + d+=0xFFFF; + d+=0xFFFE; + d+=0xFFFD; + d+=0xFFFC; + d+=0xFFFB; + /* Before d must be 0 */ d=0; + + ud=15; + ud+=0xFFFF; + ud+=0xFFFE; + ud+=0xFFFD; + ud+=0xFFFC; + ud+=0xFFFB; + /* Before ud must be 0 */ ud=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/032.add/Makefile b/pdl/riscv/tests/acstone-programs/032.add/Makefile new file mode 100644 index 0000000..182b254 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/032.add/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 032.add +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/033.add/033.add.c b/pdl/riscv/tests/acstone-programs/033.add/033.add.c new file mode 100644 index 0000000..b3e58d0 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/033.add/033.add.c @@ -0,0 +1,154 @@ +/** + * @file 033.add.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed and unsigned int adds. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed int a,b,c; + signed int d; + unsigned int ua,ub,uc; + unsigned int ud; + + a=0x0000FFFF; + b=0xFFFF0000; + c=a+b; + /* Before c must be -1 */ c=0; + + a=0xFFFFFFEC; + b=0xFFFFFFE2; + c=a+b; + /* Before c must be -50 */ c=0; + + a=0xFFFFFFFE; + b=0x00000002; + c=a+b; + /* Before c must be 0 */ c=0; + + a=0x0000000A; + b=0xFFFFFFFB; + c=a+b; + /* Before c must be 5 */ c=0; + + a=0x00000005; + b=0xFFFFFFF6; + c=a+b; + /* Before c must be -5 */ c=0; + + a=0x0F0F0F0F; + b=0xF0F0F0F0; + c=a+b; + /* Before c must be -1 */ c=0; + + a=0xAAAAAAAA; + b=0x55555555; + c=a+b; + /* Before c must be -1 */ c=0; + + d=0; + d+=1; + d+=2; + d+=3; + d+=4; + d+=5; + /* Before d must be 15 */ d=0; + + + ua=0x0000FFFF; + ub=0xFFFF0000; + uc=ua+ub; + /* Before uc must be 4294967295 */ uc=0; + + ua=0xFFFFFFEC; + ub=0xFFFFFFE2; + uc=ua+ub; + /* Before uc must be 4294967246 */ uc=0; + + ua=0xFFFFFFFE; + ub=0x00000002; + uc=ua+ub; + /* Before uc must be 0 */ uc=0; + + ua=0x0000000A; + ub=0xFFFFFFFB; + uc=ua+ub; + /* Before uc must be 5 */ uc=0; + + ua=0x00000005; + ub=0xFFFFFFF6; + uc=ua+ub; + /* Before uc must be 4294967291 */ uc=0; + + ua=0x0F0F0F0F; + ub=0xF0F0F0F0; + uc=ua+ub; + /* Before uc must be 4294967295 */ uc=0; + + ua=0xAAAAAAAA; + ub=0x55555555; + uc=ua+ub; + /* Before uc must be 4294967295 */ uc=0; + + ud=0; + ud+=1; + ud+=2; + ud+=3; + ud+=4; + ud+=5; + /* Before ud must be 15 */ ud=0; + + d=15; + d+=0xFFFFFFFF; + d+=0xFFFFFFFE; + d+=0xFFFFFFFD; + d+=0xFFFFFFFC; + d+=0xFFFFFFFB; + /* Before d must be 0 */ d=0; + + ud=15; + ud+=0xFFFFFFFF; + ud+=0xFFFFFFFE; + ud+=0xFFFFFFFD; + ud+=0xFFFFFFFC; + ud+=0xFFFFFFFB; + /* Before ud must be 0 */ ud=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/033.add/Makefile b/pdl/riscv/tests/acstone-programs/033.add/Makefile new file mode 100644 index 0000000..5663b19 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/033.add/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 033.add +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/034.add/034.add.c b/pdl/riscv/tests/acstone-programs/034.add/034.add.c new file mode 100644 index 0000000..bc907be --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/034.add/034.add.c @@ -0,0 +1,154 @@ +/** + * @file 034.add.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses signed and unsigned long long int adds. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed long long int a,b,c; + signed long long int d; + unsigned long long int ua,ub,uc; + unsigned long long int ud; + + a=0x00000000FFFFFFFFLL; + b=0xFFFFFFFF00000000LL; + c=a+b; + /* Before c must be -1 */ c=0; + + a=0xFFFFFFFFFFFFFFECLL; + b=0xFFFFFFFFFFFFFFE2LL; + c=a+b; + /* Before c must be -50 */ c=0; + + a=0xFFFFFFFFFFFFFFFELL; + b=0x0000000000000002LL; + c=a+b; + /* Before c must be 0 */ c=0; + + a=0x000000000000000ALL; + b=0xFFFFFFFFFFFFFFFBLL; + c=a+b; + /* Before c must be 5 */ c=0; + + a=0x0000000000000005LL; + b=0xFFFFFFFFFFFFFFF6LL; + c=a+b; + /* Before c must be -5 */ c=0; + + a=0xF0F0F0F0F0F0F0F0LL; + b=0x0F0F0F0F0F0F0F0FLL; + c=a+b; + /* Before c must be -1 */ c=0; + + a=0xAAAAAAAAAAAAAAAALL; + b=0x5555555555555555LL; + c=a+b; + /* Before c must be -1 */ c=0; + + d=0; + d+=1; + d+=2; + d+=3; + d+=4; + d+=5; + /* Before d must be 15 */ d=0; + + + ua=0x00000000FFFFFFFFULL; + ub=0xFFFFFFFF00000000ULL; + uc=ua+ub; + /* Before uc must be 18446744073709551615 */ uc=0; + + ua=0xFFFFFFFFFFFFFFECULL; + ub=0xFFFFFFFFFFFFFFE2ULL; + uc=ua+ub; + /* Before uc must be 18446744073709551566 */ uc=0; + + ua=0xFFFFFFFFFFFFFFFEULL; + ub=0x0000000000000002ULL; + uc=ua+ub; + /* Before uc must be 0 */ uc=0; + + ua=0x000000000000000AULL; + ub=0xFFFFFFFFFFFFFFFBULL; + uc=ua+ub; + /* Before uc must be 5 */ uc=0; + + ua=0x0000000000000005ULL; + ub=0xFFFFFFFFFFFFFFF6ULL; + uc=ua+ub; + /* Before uc must be 18446744073709551611 */ uc=0; + + ua=0x0F0F0F0F0F0F0F0FULL; + ub=0xF0F0F0F0F0F0F0F0ULL; + uc=ua+ub; + /* Before uc must be 18446744073709551615 */ uc=0; + + ua=0xAAAAAAAAAAAAAAAAULL; + ub=0x5555555555555555ULL; + uc=ua+ub; + /* Before uc must be 18446744073709551615 */ uc=0; + + ud=0; + ud+=1; + ud+=2; + ud+=3; + ud+=4; + ud+=5; + /* Before ud must be 15 */ ud=0; + + d=15; + d+=0xFFFFFFFFFFFFFFFFULL; + d+=0xFFFFFFFFFFFFFFFEULL; + d+=0xFFFFFFFFFFFFFFFDULL; + d+=0xFFFFFFFFFFFFFFFCULL; + d+=0xFFFFFFFFFFFFFFFBULL; + /* Before d must be 0 */ d=0; + + ud=15; + ud+=0xFFFFFFFFFFFFFFFFULL; + ud+=0xFFFFFFFFFFFFFFFEULL; + ud+=0xFFFFFFFFFFFFFFFDULL; + ud+=0xFFFFFFFFFFFFFFFCULL; + ud+=0xFFFFFFFFFFFFFFFBULL; + /* Before ud must be 0 */ ud=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/034.add/Makefile b/pdl/riscv/tests/acstone-programs/034.add/Makefile new file mode 100644 index 0000000..64dc3cd --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/034.add/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 034.add +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/041.sub/041.sub.c b/pdl/riscv/tests/acstone-programs/041.sub/041.sub.c new file mode 100644 index 0000000..17a5f02 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/041.sub/041.sub.c @@ -0,0 +1,154 @@ +/** + * @file 041.sub.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses signed and unsigned char subs. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed char a,b,c; + signed char d; + unsigned char ua,ub,uc; + unsigned char ud; + + a=0x0A; + b=0x14; + c=a-b; + /* Before c must be -10 */ c=0; + + a=0xEC; + b=0xE2; + c=a-b; + /* Before c must be 10 */ c=0; + + a=0xFE; + b=0x02; + c=a-b; + /* Before c must be -4 */ c=0; + + a=0x0A; + b=0xFB; + c=a-b; + /* Before c must be 15 */ c=0; + + a=0x05; + b=0xF6; + c=a-b; + /* Before c must be 15 */ c=0; + + a=0x0F; + b=0xF0; + c=a-b; + /* Before c must be 31 */ c=0; + + a=0xAA; + b=0x55; + c=a-b; + /* Before c must be 85 */ c=0; + + d=15; + d-=1; + d-=2; + d-=3; + d-=4; + d-=5; + /* Before d must be 0 */ d=0; + + + ua=0x0A; + ub=0x14; + uc=ua-ub; + /* Before uc must be 246 */ uc=0; + + ua=0xEC; + ub=0xE2; + uc=ua-ub; + /* Before uc must be 10 */ uc=0; + + ua=0xFE; + ub=0x02; + uc=ua-ub; + /* Before uc must be 252 */ uc=0; + + ua=0x0A; + ub=0xFB; + uc=ua-ub; + /* Before uc must be 15 */ uc=0; + + ua=0x05; + ub=0xF6; + uc=ua-ub; + /* Before uc must be 15 */ uc=0; + + ua=0x0F; + ub=0xF0; + uc=ua-ub; + /* Before uc must be 31 */ uc=0; + + ua=0xAA; + ub=0x55; + uc=ua-ub; + /* Before uc must be 85 */ uc=0; + + ud=15; + ud-=1; + ud-=2; + ud-=3; + ud-=4; + ud-=5; + /* Before ud must be 0 */ ud=0; + + d=0; + d-=0xFF; + d-=0xFE; + d-=0xFD; + d-=0xFC; + d-=0xFB; + /* Before d must be 15 */ d=0; + + ud=0; + ud-=0xFF; + ud-=0xFE; + ud-=0xFD; + ud-=0xFC; + ud-=0xFB; + /* Before ud must be 15 */ ud=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/041.sub/Makefile b/pdl/riscv/tests/acstone-programs/041.sub/Makefile new file mode 100644 index 0000000..7021a78 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/041.sub/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 041.sub +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/042.sub/042.sub.c b/pdl/riscv/tests/acstone-programs/042.sub/042.sub.c new file mode 100644 index 0000000..7006fd2 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/042.sub/042.sub.c @@ -0,0 +1,154 @@ +/** + * @file 042.sub.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed and unsigned short int subs. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed short int a,b,c; + signed short int d; + unsigned short int ua,ub,uc; + unsigned short int ud; + + a=0x00FF; + b=0xFF00; + c=a-b; + /* Before c must be 511 */ c=0; + + a=0xFFEC; + b=0xFFE2; + c=a-b; + /* Before c must be 10 */ c=0; + + a=0xFFFE; + b=0x0002; + c=a-b; + /* Before c must be -4 */ c=0; + + a=0x000A; + b=0xFFFB; + c=a-b; + /* Before c must be 15 */ c=0; + + a=0x0005; + b=0xFFF6; + c=a-b; + /* Before c must be 15 */ c=0; + + a=0x0F0F; + b=0xF0F0; + c=a-b; + /* Before c must be 7711 */ c=0; + + a=0xAAAA; + b=0x5555; + c=a-b; + /* Before c must be 21845 */ c=0; + + d=15; + d-=1; + d-=2; + d-=3; + d-=4; + d-=5; + /* Before d must be 0 */ d=0; + + + ua=0x00FF; + ub=0xFF00; + uc=ua-ub; + /* Before uc must be 511 */ uc=0; + + ua=0xFFEC; + ub=0xFFE2; + uc=ua-ub; + /* Before uc must be 10 */ uc=0; + + ua=0xFFFE; + ub=0x0002; + uc=ua-ub; + /* Before uc must be 65532 */ uc=0; + + ua=0x000A; + ub=0xFFFB; + uc=ua-ub; + /* Before uc must be 15 */ uc=0; + + ua=0x0005; + ub=0xFFF6; + uc=ua-ub; + /* Before uc must be 15 */ uc=0; + + ua=0x0F0F; + ub=0xF0F0; + uc=ua-ub; + /* Before uc must be 7711 */ uc=0; + + ua=0xAAAA; + ub=0x5555; + uc=ua-ub; + /* Before uc must be 21845 */ uc=0; + + ud=15; + ud-=1; + ud-=2; + ud-=3; + ud-=4; + ud-=5; + /* Before ud must be 0 */ ud=0; + + d=0; + d-=0xFFFF; + d-=0xFFFE; + d-=0xFFFD; + d-=0xFFFC; + d-=0xFFFB; + /* Before d must be 15 */ d=0; + + ud=0; + ud-=0xFFFF; + ud-=0xFFFE; + ud-=0xFFFD; + ud-=0xFFFC; + ud-=0xFFFB; + /* Before ud must be 15 */ ud=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/042.sub/Makefile b/pdl/riscv/tests/acstone-programs/042.sub/Makefile new file mode 100644 index 0000000..5a0afbb --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/042.sub/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 042.sub +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/043.sub/043.sub.c b/pdl/riscv/tests/acstone-programs/043.sub/043.sub.c new file mode 100644 index 0000000..7e3c55c --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/043.sub/043.sub.c @@ -0,0 +1,154 @@ +/** + * @file 043.sub.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses signed and unsigned int subs. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed int a,b,c; + signed int d; + unsigned int ua,ub,uc; + unsigned int ud; + + a=0x0000FFFF; + b=0xFFFF0000; + c=a-b; + /* Before c must be 131071 */ c=0; + + a=0xFFFFFFEC; + b=0xFFFFFFE2; + c=a-b; + /* Before c must be 10 */ c=0; + + a=0xFFFFFFFE; + b=0x00000002; + c=a-b; + /* Before c must be -4 */ c=0; + + a=0x0000000A; + b=0xFFFFFFFB; + c=a-b; + /* Before c must be 15 */ c=0; + + a=0x00000005; + b=0xFFFFFFF6; + c=a-b; + /* Before c must be 15 */ c=0; + + a=0x0F0F0F0F; + b=0xF0F0F0F0; + c=a-b; + /* Before c must be 505290271 */ c=0; + + a=0xAAAAAAAA; + b=0x55555555; + c=a-b; + /* Before c must be 1431655765 */ c=0; + + d=15; + d-=1; + d-=2; + d-=3; + d-=4; + d-=5; + /* Before d must be 0 */ d=0; + + + ua=0x0000FFFF; + ub=0xFFFF0000; + uc=ua-ub; + /* Before uc must be 131071 */ uc=0; + + ua=0xFFFFFFEC; + ub=0xFFFFFFE2; + uc=ua-ub; + /* Before uc must be 10 */ uc=0; + + ua=0xFFFFFFFE; + ub=0x00000002; + uc=ua-ub; + /* Before uc must be 4294967292 */ uc=0; + + ua=0x0000000A; + ub=0xFFFFFFFB; + uc=ua-ub; + /* Before uc must be 15 */ uc=0; + + ua=0x00000005; + ub=0xFFFFFFF6; + uc=ua-ub; + /* Before uc must be 15 */ uc=0; + + ua=0x0F0F0F0F; + ub=0xF0F0F0F0; + uc=ua-ub; + /* Before uc must be 505290271 */ uc=0; + + ua=0xAAAAAAAA; + ub=0x55555555; + uc=ua-ub; + /* Before uc must be 1431655765 */ uc=0; + + ud=15; + ud-=1; + ud-=2; + ud-=3; + ud-=4; + ud-=5; + /* Before ud must be 0 */ ud=0; + + d=0; + d-=0xFFFFFFFF; + d-=0xFFFFFFFE; + d-=0xFFFFFFFD; + d-=0xFFFFFFFC; + d-=0xFFFFFFFB; + /* Before d must be 15 */ d=0; + + ud=0; + ud-=0xFFFFFFFF; + ud-=0xFFFFFFFE; + ud-=0xFFFFFFFD; + ud-=0xFFFFFFFC; + ud-=0xFFFFFFFB; + /* Before ud must be 15 */ ud=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/043.sub/Makefile b/pdl/riscv/tests/acstone-programs/043.sub/Makefile new file mode 100644 index 0000000..9f8e6ed --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/043.sub/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 043.sub +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/044.sub/044.sub.c b/pdl/riscv/tests/acstone-programs/044.sub/044.sub.c new file mode 100644 index 0000000..99d6b97 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/044.sub/044.sub.c @@ -0,0 +1,154 @@ +/** + * @file 044.sub.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses signed and unsigned long long int adds. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed long long int a,b,c; + signed long long int d; + unsigned long long int ua,ub,uc; + unsigned long long int ud; + + a=0x00000000FFFFFFFFLL; + b=0xFFFFFFFF00000000LL; + c=a-b; + /* Before c must be 8589934591 */ c=0; + + a=0xFFFFFFFFFFFFFFECLL; + b=0xFFFFFFFFFFFFFFE2LL; + c=a-b; + /* Before c must be 10 */ c=0; + + a=0xFFFFFFFFFFFFFFFELL; + b=0x0000000000000002LL; + c=a-b; + /* Before c must be -4 */ c=0; + + a=0x000000000000000ALL; + b=0xFFFFFFFFFFFFFFFBLL; + c=a-b; + /* Before c must be 15 */ c=0; + + a=0x0000000000000005LL; + b=0xFFFFFFFFFFFFFFF6LL; + c=a-b; + /* Before c must be 15 */ c=0; + + a=0xF0F0F0F0F0F0F0F0LL; + b=0x0F0F0F0F0F0F0F0FLL; + c=a-b; + /* Before c must be -2170205185142300191 */ c=0; + + a=0xAAAAAAAAAAAAAAAALL; + b=0x5555555555555555LL; + c=a-b; + /* Before c must be 6148914691236517205 */ c=0; + + d=15; + d-=1; + d-=2; + d-=3; + d-=4; + d-=5; + /* Before d must be 0 */ d=0; + + + ua=0x00000000FFFFFFFFULL; + ub=0xFFFFFFFF00000000ULL; + uc=ua-ub; + /* Before uc must be 8589934591 */ uc=0; + + ua=0xFFFFFFFFFFFFFFECULL; + ub=0xFFFFFFFFFFFFFFE2ULL; + uc=ua-ub; + /* Before uc must be 10 */ uc=0; + + ua=0xFFFFFFFFFFFFFFFEULL; + ub=0x0000000000000002ULL; + uc=ua-ub; + /* Before uc must be 18446744073709551612 */ uc=0; + + ua=0x000000000000000AULL; + ub=0xFFFFFFFFFFFFFFFBULL; + uc=ua-ub; + /* Before uc must be 15 */ uc=0; + + ua=0x0000000000000005ULL; + ub=0xFFFFFFFFFFFFFFF6ULL; + uc=ua-ub; + /* Before uc must be 15 */ uc=0; + + ua=0x0F0F0F0F0F0F0F0FULL; + ub=0xF0F0F0F0F0F0F0F0ULL; + uc=ua-ub; + /* Before uc must be 2170205185142300191 */ uc=0; + + ua=0xAAAAAAAAAAAAAAAAULL; + ub=0x5555555555555555ULL; + uc=ua-ub; + /* Before uc must be 6148914691236517205 */ uc=0; + + ud=15; + ud-=1; + ud-=2; + ud-=3; + ud-=4; + ud-=5; + /* Before ud must be 0 */ ud=0; + + d=0; + d-=0xFFFFFFFFFFFFFFFFULL; + d-=0xFFFFFFFFFFFFFFFEULL; + d-=0xFFFFFFFFFFFFFFFDULL; + d-=0xFFFFFFFFFFFFFFFCULL; + d-=0xFFFFFFFFFFFFFFFBULL; + /* Before d must be 15 */ d=0; + + ud=0; + ud-=0xFFFFFFFFFFFFFFFFULL; + ud-=0xFFFFFFFFFFFFFFFEULL; + ud-=0xFFFFFFFFFFFFFFFDULL; + ud-=0xFFFFFFFFFFFFFFFCULL; + ud-=0xFFFFFFFFFFFFFFFBULL; + /* Before ud must be 15 */ ud=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/044.sub/Makefile b/pdl/riscv/tests/acstone-programs/044.sub/Makefile new file mode 100644 index 0000000..45dae37 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/044.sub/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 044.sub +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/051.mul/051.mul.c b/pdl/riscv/tests/acstone-programs/051.mul/051.mul.c new file mode 100644 index 0000000..fab5ff4 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/051.mul/051.mul.c @@ -0,0 +1,84 @@ +/** + * @file 051.mul.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses signed char multiplication. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed char a,b; + signed short int c; + + a=0x02; + b=0x04; + c=(signed short int)(a)*(signed short int)(b); + /* Before c must be 8 */ c=0; + + a=0xFF; + b=0xFF; + c=(signed short int)(a)*(signed short int)(b); + /* Before c must be 1 */ c=0; + + a=0xFF; + b=0x01; + c=(signed short int)(a)*(signed short int)(b); + /* Before c must be -1 */ c=0; + + a=0xFF; + b=0x0A; + c=(signed short int)(a)*(signed short int)(b); + /* Before c must be -10 */ c=0; + + a=0xFE; + b=0xFC; + c=(signed short int)(a)*(signed short int)(b); + /* Before c must be 8 */ c=0; + + a=0x0A; + b=0x0B; + c=(signed short int)(a)*(signed short int)(b); + /* Before c must be 110 */ c=0; + + a=0xF6; + b=0x0B; + c=(signed short int)(a)*(signed short int)(b); + /* Before c must be -110 */ c=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/051.mul/Makefile b/pdl/riscv/tests/acstone-programs/051.mul/Makefile new file mode 100644 index 0000000..0454f8a --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/051.mul/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 051.mul +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/052.mul/052.mul.c b/pdl/riscv/tests/acstone-programs/052.mul/052.mul.c new file mode 100644 index 0000000..a11f39b --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/052.mul/052.mul.c @@ -0,0 +1,84 @@ +/** + * @file 052.mul.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses unsigned char multiplication. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned char a,b; + unsigned short int c; + + a=0x02; + b=0x04; + c=(unsigned short int)(a)*(unsigned short int)(b); + /* Before c must be 8 */ c=0; + + a=0xFF; + b=0xFF; + c=(unsigned short int)(a)*(unsigned short int)(b); + /* Before c must be 65025 */ c=0; + + a=0xFF; + b=0x01; + c=(unsigned short int)(a)*(unsigned short int)(b); + /* Before c must be 255 */ c=0; + + a=0xFF; + b=0x0A; + c=(unsigned short int)(a)*(unsigned short int)(b); + /* Before c must be 2550 */ c=0; + + a=0xFE; + b=0xFC; + c=(unsigned short int)(a)*(unsigned short int)(b); + /* Before c must be 64008 */ c=0; + + a=0x0A; + b=0x0B; + c=(unsigned short int)(a)*(unsigned short int)(b); + /* Before c must be 110 */ c=0; + + a=0xF6; + b=0x0B; + c=(unsigned short int)(a)*(unsigned short int)(b); + /* Before c must be 2706 */ c=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/052.mul/Makefile b/pdl/riscv/tests/acstone-programs/052.mul/Makefile new file mode 100644 index 0000000..a0f8ec2 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/052.mul/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 052.mul +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/053.mul/053.mul.c b/pdl/riscv/tests/acstone-programs/053.mul/053.mul.c new file mode 100644 index 0000000..f28a086 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/053.mul/053.mul.c @@ -0,0 +1,99 @@ +/** + * @file 053.mul.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses signed short int multiplication. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed short int a,b; + signed int c; + + a=0x0002; + b=0x0004; + c=(signed int)(a)*(signed int)(b); + /* Before c must be 8 */ c=0; + + a=0xFFFF; + b=0xFFFF; + c=(signed int)(a)*(signed int)(b); + /* Before c must be 1 */ c=0; + + a=0xFFFF; + b=0x0001; + c=(signed int)(a)*(signed int)(b); + /* Before c must be -1 */ c=0; + + a=0xFFFF; + b=0x000A; + c=(signed int)(a)*(signed int)(b); + /* Before c must be -10 */ c=0; + + a=0xFFFE; + b=0xFFFC; + c=(signed int)(a)*(signed int)(b); + /* Before c must be 8 */ c=0; + + a=0x000A; + b=0x000B; + c=(signed int)(a)*(signed int)(b); + /* Before c must be 110 */ c=0; + + a=0xFFF6; + b=0x000B; + c=(signed int)(a)*(signed int)(b); + /* Before c must be -110 */ c=0; + + a=0xF000; + b=0xF001; + c=(signed int)(a)*(signed int)(b); + /* Before c must be 16773120 */ c=0; + + a=0x5555; + b=0x3333; + c=(signed int)(a)*(signed int)(b); + /* Before c must be 286322415 */ c=0; + + a=0x5353; + b=0x8000; + c=(signed int)(a)*(signed int)(b); + /* Before c must be -698974208 */ c=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/053.mul/Makefile b/pdl/riscv/tests/acstone-programs/053.mul/Makefile new file mode 100644 index 0000000..aaa9b57 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/053.mul/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 053.mul +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/054.mul/054.mul.c b/pdl/riscv/tests/acstone-programs/054.mul/054.mul.c new file mode 100644 index 0000000..ed262ca --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/054.mul/054.mul.c @@ -0,0 +1,99 @@ +/** + * @file 054.mul.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses unsigned short int multiplication. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned short int a,b; + unsigned int c; + + a=0x0002; + b=0x0004; + c=(unsigned int)(a)*(unsigned int)(b); + /* Before c must be 8 */ c=0; + + a=0xFFFF; + b=0xFFFF; + c=(unsigned int)(a)*(unsigned int)(b); + /* Before c must be 4294836225 */ c=0; + + a=0xFFFF; + b=0x0001; + c=(unsigned int)(a)*(unsigned int)(b); + /* Before c must be 65535 */ c=0; + + a=0xFFFF; + b=0x000A; + c=(unsigned int)(a)*(unsigned int)(b); + /* Before c must be 655350 */ c=0; + + a=0xFFFE; + b=0xFFFC; + c=(unsigned int)(a)*(unsigned int)(b); + /* Before c must be 4294574088 */ c=0; + + a=0x000A; + b=0x000B; + c=(unsigned int)(a)*(unsigned int)(b); + /* Before c must be 110 */ c=0; + + a=0xFFF6; + b=0x000B; + c=(unsigned int)(a)*(unsigned int)(b); + /* Before c must be 720786 */ c=0; + + a=0xF000; + b=0xF001; + c=(unsigned int)(a)*(unsigned int)(b); + /* Before c must be 3774935040 */ c=0; + + a=0x5555; + b=0x3333; + c=(unsigned int)(a)*(unsigned int)(b); + /* Before c must be 286322415 */ c=0; + + a=0x5353; + b=0x8000; + c=(unsigned int)(a)*(unsigned int)(b); + /* Before c must be 698974208 */ c=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/054.mul/Makefile b/pdl/riscv/tests/acstone-programs/054.mul/Makefile new file mode 100644 index 0000000..d2cdf86 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/054.mul/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 054.mul +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/055.mul/055.mul.c b/pdl/riscv/tests/acstone-programs/055.mul/055.mul.c new file mode 100644 index 0000000..b4748b6 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/055.mul/055.mul.c @@ -0,0 +1,115 @@ +/** + * @file 055.mul.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses signed int multiplication. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed int a,b; + signed long long int c; + + a=0x00000002; + b=0x00000004; + c=(signed long long int)(a)*(signed long long int)(b); + /* Before c must be 8 */ c=0; + + a=0xFFFFFFFF; + b=0xFFFFFFFF; + c=(signed long long int)(a)*(signed long long int)(b); + /* Before c must be 1 */ c=0; + + a=0xFFFFFFFF; + b=0x00000001; + c=(signed long long int)(a)*(signed long long int)(b); + /* Before c must be -1 */ c=0; + + a=0xFFFFFFFF; + b=0x0000000A; + c=(signed long long int)(a)*(signed long long int)(b); + /* Before c must be -10 */ c=0; + + a=0xFFFFFFFE; + b=0xFFFFFFFC; + c=(signed long long int)(a)*(signed long long int)(b); + /* Before c must be 8 */ c=0; + + a=0x0000000A; + b=0x0000000B; + c=(signed long long int)(a)*(signed long long int)(b); + /* Before c must be 110 */ c=0; + + a=0xFFFFFFF6; + b=0x0000000B; + c=(signed long long int)(a)*(signed long long int)(b); + /* Before c must be -110 */ c=0; + + a=0x0000F000; + b=0x0000F001; + c=(signed long long int)(a)*(signed long long int)(b); + /* Before c must be 3774935040 */ c=0; + + a=0x55555555; + b=0x33333333; + c=(signed long long int)(a)*(signed long long int)(b); + /* Before c must be 1229782937674641135 */ c=0; + + a=0x00005353; + b=0x00008000; + c=(signed long long int)(a)*(signed long long int)(b); + /* Before c must be 698974208 */ c=0; + + a=0xFFFFF000; + b=0xFFFFF001; + c=(signed long long int)(a)*(signed long long int)(b); + /* Before c must be 16773120 */ c=0; + + a=0x00005555; + b=0x33330000; + c=(signed long long int)(a)*(signed long long int)(b); + /* Before c must be 18764425789440 */ c=0; + + a=0x53535353; + b=0x80008000; + c=(signed long long int)(a)*(signed long long int)(b); + /* Before c must be -3002071363408527360 */ c=0; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/055.mul/Makefile b/pdl/riscv/tests/acstone-programs/055.mul/Makefile new file mode 100644 index 0000000..137677a --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/055.mul/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 055.mul +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/056.mul/056.mul.c b/pdl/riscv/tests/acstone-programs/056.mul/056.mul.c new file mode 100644 index 0000000..701a46a --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/056.mul/056.mul.c @@ -0,0 +1,115 @@ +/** + * @file 056.mul.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses unsigned int multiplication. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned int a,b; + unsigned long long int c; + + a=0x00000002; + b=0x00000004; + c=(unsigned long long int)(a)*(unsigned long long int)(b); + /* Before c must be 8 */ c=0; + + a=0xFFFFFFFF; + b=0xFFFFFFFF; + c=(unsigned long long int)(a)*(unsigned long long int)(b); + /* Before c must be 18446744065119617025 */ c=0; + + a=0xFFFFFFFF; + b=0x00000001; + c=(unsigned long long int)(a)*(unsigned long long int)(b); + /* Before c must be 4294967295 */ c=0; + + a=0xFFFFFFFF; + b=0x0000000A; + c=(unsigned long long int)(a)*(unsigned long long int)(b); + /* Before c must be 42949672950 */ c=0; + + a=0xFFFFFFFE; + b=0xFFFFFFFC; + c=(unsigned long long int)(a)*(unsigned long long int)(b); + /* Before c must be 18446744047939747848 */ c=0; + + a=0x0000000A; + b=0x0000000B; + c=(unsigned long long int)(a)*(unsigned long long int)(b); + /* Before c must be 110 */ c=0; + + a=0xFFFFFFF6; + b=0x0000000B; + c=(unsigned long long int)(a)*(unsigned long long int)(b); + /* Before c must be 47244640146 */ c=0; + + a=0x0000F000; + b=0x0000F001; + c=(unsigned long long int)(a)*(unsigned long long int)(b); + /* Before c must be 3774935040 */ c=0; + + a=0x55555555; + b=0x33333333; + c=(unsigned long long int)(a)*(unsigned long long int)(b); + /* Before c must be 1229782937674641135 */ c=0; + + a=0x00005353; + b=0x00008000; + c=(unsigned long long int)(a)*(unsigned long long int)(b); + /* Before c must be 698974208 */ c=0; + + a=0xFFFFF000; + b=0xFFFFF001; + c=(unsigned long long int)(a)*(unsigned long long int)(b); + /* Before c must be 18446708893649203200 */ c=0; + + a=0x00005555; + b=0x33330000; + c=(unsigned long long int)(a)*(unsigned long long int)(b); + /* Before c must be 18764425789440 */ c=0; + + a=0x53535353; + b=0x80008000; + c=(unsigned long long int)(a)*(unsigned long long int)(b); + /* Before c must be 3002162980753866752 */ c=0; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/056.mul/Makefile b/pdl/riscv/tests/acstone-programs/056.mul/Makefile new file mode 100644 index 0000000..5960dfd --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/056.mul/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 056.mul +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/057.mul/057.mul.c b/pdl/riscv/tests/acstone-programs/057.mul/057.mul.c new file mode 100644 index 0000000..1ab7eab --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/057.mul/057.mul.c @@ -0,0 +1,106 @@ +/** + * @file 057.mul.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function uses various signed multiplication. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + signed char c1,c2,c3,c4,c5,cresult; + signed short int si1,si2,si3,si4,si5,siresult; + signed int i1,i2,i3,i4,i5,iresult; + signed long long int li1,li2,li3,li4,li5,liresult; + + c1=1; + c2=2; + c3=3; + c4=4; + c5=5; + cresult=c1*c2*c3*c4*c5; + /* Before cresult must be 120 */ cresult=0; + + si1=1; + si2=2; + si3=3; + si4=4; + si5=5; + siresult=si1*si2*si3*si4*si5; + /* Before siresult must be 120 */ siresult=0; + + i1=1; + i2=2; + i3=3; + i4=4; + i5=5; + iresult=i1*i2*i3*i4*i5; + /* Before iresult must be 120 */ iresult=0; + + li1=1; + li2=2; + li3=3; + li4=4; + li5=5; + liresult=li1*li2*li3*li4*li5; + /* Before liresult must be 120 */ liresult=0; + + c1=5; + siresult=c1*7; + /* Before siresult must be 35 */ siresult=0; + + si1=5; + iresult=si1*7; + /* Before iresult must be 35 */ iresult=0; + + i1=5; + liresult=i1*7; + /* Before liresult must be 35 */ liresult=0; + + c1=17; + siresult=c1*(-1); + /* Before siresult must be -17 */ siresult=0; + + si1=17; + iresult=si1*(-1); + /* Before iresult must be -17 */ iresult=0; + + i1=17; + liresult=i1*(-1); + /* Before siresult must be -17 */ liresult=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/057.mul/Makefile b/pdl/riscv/tests/acstone-programs/057.mul/Makefile new file mode 100644 index 0000000..386b1b1 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/057.mul/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 057.mul +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/058.mul/058.mul.c b/pdl/riscv/tests/acstone-programs/058.mul/058.mul.c new file mode 100644 index 0000000..58126d7 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/058.mul/058.mul.c @@ -0,0 +1,106 @@ +/** + * @file 058.mul.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function uses various unsigned multiplication. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + unsigned char uc1,uc2,uc3,uc4,uc5,ucresult; + unsigned short int usi1,usi2,usi3,usi4,usi5,usiresult; + unsigned int ui1,ui2,ui3,ui4,ui5,uiresult; + unsigned long long int uli1,uli2,uli3,uli4,uli5,uliresult; + + uc1=1; + uc2=2; + uc3=3; + uc4=4; + uc5=5; + ucresult=uc1*uc2*uc3*uc4*uc5; + /* Before ucresult must be 120 */ ucresult=0; + + usi1=1; + usi2=2; + usi3=3; + usi4=4; + usi5=5; + usiresult=usi1*usi2*usi3*usi4*usi5; + /* Before usiresult must be 120 */ usiresult=0; + + ui1=1; + ui2=2; + ui3=3; + ui4=4; + ui5=5; + uiresult=ui1*ui2*ui3*ui4*ui5; + /* Before uiresult must be 120 */ uiresult=0; + + uli1=1; + uli2=2; + uli3=3; + uli4=4; + uli5=5; + uliresult=uli1*uli2*uli3*uli4*uli5; + /* Before uliresult must be 120 */ uliresult=0; + + uc1=5; + usiresult=uc1*7; + /* Before usiresult must be 35 */ usiresult=0; + + usi1=5; + uiresult=usi1*7; + /* Before uiresult must be 35 */ uiresult=0; + + ui1=5; + uliresult=ui1*7; + /* Before uliresult must be 35 */ uliresult=0; + + uc1=17; + usiresult=uc1*5; + /* Before usiresult must be 85 */ usiresult=0; + + usi1=17; + uiresult=usi1*5; + /* Before uiresult must be 85 */ uiresult=0; + + ui1=17; + uliresult=ui1*5; + /* Before siresult must be 85 */ uliresult=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/058.mul/Makefile b/pdl/riscv/tests/acstone-programs/058.mul/Makefile new file mode 100644 index 0000000..b4bf7bb --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/058.mul/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 058.mul +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/061.div/061.div.c b/pdl/riscv/tests/acstone-programs/061.div/061.div.c new file mode 100644 index 0000000..96e00ae --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/061.div/061.div.c @@ -0,0 +1,109 @@ +/** + * @file 061.div.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed char division. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed char a,b,c; + + a=0xFF; + b=0x01; + c=a/b; + /* Before c must be -1 */ c=0; + + a=0x0F; + b=0x03; + c=a/b; + /* Before c must be 5 */ c=0; + + a=0xAA; + b=0x55; + c=a/b; + /* Before c must be -1 */ c=0; + + a=0x7F; + b=0xFF; + c=a/b; + /* Before c must be -127 */ c=0; + + a=0x00; + b=0x80; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x30; + b=0x05; + c=a/b; + /* Before c must be 9 */ c=0; + + a=0xFF; + b=0xFF; + c=a/b; + /* Before c must be 1 */ c=0; + + a=0xFE; + b=0x10; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x20; + b=0xFE; + c=a/b; + /* Before c must be -16 */ c=0; + + a=0x00; + b=0xFF; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x78; + c=a/5; + c=c/4; + c=c/3; + c=c/2; + /* Before c must be 1 */ c=0; + + a=0x10; + c=a/(-1); + /* Before c must be -16 */ c=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/061.div/Makefile b/pdl/riscv/tests/acstone-programs/061.div/Makefile new file mode 100644 index 0000000..37ea7e8 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/061.div/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 061.div +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/062.div/062.div.c b/pdl/riscv/tests/acstone-programs/062.div/062.div.c new file mode 100644 index 0000000..691db3c --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/062.div/062.div.c @@ -0,0 +1,109 @@ +/** + * @file 062.div.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses unsigned char division. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned char a,b,c; + + a=0xFF; + b=0x01; + c=a/b; + /* Before c must be 255 */ c=0; + + a=0x0F; + b=0x03; + c=a/b; + /* Before c must be 5 */ c=0; + + a=0xAA; + b=0x55; + c=a/b; + /* Before c must be 2 */ c=0; + + a=0x7F; + b=0xFF; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x00; + b=0x80; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x30; + b=0x05; + c=a/b; + /* Before c must be 9 */ c=0; + + a=0xFF; + b=0xFF; + c=a/b; + /* Before c must be 1 */ c=0; + + a=0xFE; + b=0x10; + c=a/b; + /* Before c must be 15 */ c=0; + + a=0x20; + b=0xFE; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x00; + b=0xFF; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x78; + c=a/5; + c=c/4; + c=c/3; + c=c/2; + /* Before c must be 1 */ c=0; + + a=0x10; + c=a/0xFF; + /* Before c must be 0 */ c=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/062.div/Makefile b/pdl/riscv/tests/acstone-programs/062.div/Makefile new file mode 100644 index 0000000..71d8ec6 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/062.div/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 062.div +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/063.div/063.div.c b/pdl/riscv/tests/acstone-programs/063.div/063.div.c new file mode 100644 index 0000000..1272e91 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/063.div/063.div.c @@ -0,0 +1,109 @@ +/** + * @file 063.div.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed short int division. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed short int a,b,c; + + a=0xFFFF; + b=0x0001; + c=a/b; + /* Before c must be -1 */ c=0; + + a=0x000F; + b=0x0003; + c=a/b; + /* Before c must be 5 */ c=0; + + a=0xAAAA; + b=0x5555; + c=a/b; + /* Before c must be -1 */ c=0; + + a=0x7FFF; + b=0xFFFF; + c=a/b; + /* Before c must be -32767 */ c=0; + + a=0x0000; + b=0x8000; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x0030; + b=0x0005; + c=a/b; + /* Before c must be 9 */ c=0; + + a=0xFFFF; + b=0xFFFF; + c=a/b; + /* Before c must be 1 */ c=0; + + a=0xFFFE; + b=0x0010; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x0020; + b=0xFFFE; + c=a/b; + /* Before c must be -16 */ c=0; + + a=0x0000; + b=0xFFFF; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x0078; + c=a/5; + c=c/4; + c=c/3; + c=c/2; + /* Before c must be 1 */ c=0; + + a=0x1000; + c=a/(-1); + /* Before c must be -4096 */ c=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/063.div/Makefile b/pdl/riscv/tests/acstone-programs/063.div/Makefile new file mode 100644 index 0000000..8b860eb --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/063.div/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 063.div +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/064.div/064.div.c b/pdl/riscv/tests/acstone-programs/064.div/064.div.c new file mode 100644 index 0000000..aeb9003 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/064.div/064.div.c @@ -0,0 +1,109 @@ +/** + * @file 064.div.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses unsigned short int division. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned short int a,b,c; + + a=0xFFFF; + b=0x0001; + c=a/b; + /* Before c must be 65535 */ c=0; + + a=0x000F; + b=0x0003; + c=a/b; + /* Before c must be 5 */ c=0; + + a=0xAAAA; + b=0x5555; + c=a/b; + /* Before c must be 2 */ c=0; + + a=0x7FFF; + b=0xFFFF; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x0000; + b=0x8000; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x0030; + b=0x0005; + c=a/b; + /* Before c must be 9 */ c=0; + + a=0xFFFF; + b=0xFFFF; + c=a/b; + /* Before c must be 1 */ c=0; + + a=0xFFFE; + b=0x0010; + c=a/b; + /* Before c must be 4095 */ c=0; + + a=0x0020; + b=0xFFFE; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x0000; + b=0xFFFF; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x78; + c=a/5; + c=c/4; + c=c/3; + c=c/2; + /* Before c must be 1 */ c=0; + + a=0x10; + c=a/0xFFFF; + /* Before c must be 0 */ c=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/064.div/Makefile b/pdl/riscv/tests/acstone-programs/064.div/Makefile new file mode 100644 index 0000000..2a83217 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/064.div/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 064.div +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/065.div/065.div.c b/pdl/riscv/tests/acstone-programs/065.div/065.div.c new file mode 100644 index 0000000..fed38d0 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/065.div/065.div.c @@ -0,0 +1,109 @@ +/** + * @file 065.div.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed int division. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed int a,b,c; + + a=0xFFFFFFFF; + b=0x00000001; + c=a/b; + /* Before c must be -1 */ c=0; + + a=0x0000000F; + b=0x00000003; + c=a/b; + /* Before c must be 5 */ c=0; + + a=0xAAAAAAAA; + b=0x55555555; + c=a/b; + /* Before c must be -1 */ c=0; + + a=0x7FFFFFFF; + b=0xFFFFFFFF; + c=a/b; + /* Before c must be -2147483647 */ c=0; + + a=0x00000000; + b=0x80000000; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x00000030; + b=0x00000005; + c=a/b; + /* Before c must be 9 */ c=0; + + a=0xFFFFFFFF; + b=0xFFFFFFFF; + c=a/b; + /* Before c must be 1 */ c=0; + + a=0xFFFFFFFE; + b=0x00000010; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x00000020; + b=0xFFFFFFFE; + c=a/b; + /* Before c must be -16 */ c=0; + + a=0x00000000; + b=0xFFFFFFFF; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x00000078; + c=a/5; + c=c/4; + c=c/3; + c=c/2; + /* Before c must be 1 */ c=0; + + a=0x10000000; + c=a/(-1); + /* Before c must be -268435456 */ c=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/065.div/Makefile b/pdl/riscv/tests/acstone-programs/065.div/Makefile new file mode 100644 index 0000000..b1ca244 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/065.div/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 065.div +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/066.div/066.div.c b/pdl/riscv/tests/acstone-programs/066.div/066.div.c new file mode 100644 index 0000000..2419ddb --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/066.div/066.div.c @@ -0,0 +1,109 @@ +/** + * @file 066.div.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses unsigned int division. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned int a,b,c; + + a=0xFFFFFFFF; + b=0x00000001; + c=a/b; + /* Before c must be 4294967295 */ c=0; + + a=0x0000000F; + b=0x00000003; + c=a/b; + /* Before c must be 5 */ c=0; + + a=0xAAAAAAAA; + b=0x55555555; + c=a/b; + /* Before c must be 2 */ c=0; + + a=0x7FFFFFFF; + b=0xFFFFFFFF; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x00000000; + b=0x80000000; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x00000030; + b=0x00000005; + c=a/b; + /* Before c must be 9 */ c=0; + + a=0xFFFFFFFF; + b=0xFFFFFFFF; + c=a/b; + /* Before c must be 1 */ c=0; + + a=0xFFFFFFFE; + b=0x00000010; + c=a/b; + /* Before c must be 268435455 */ c=0; + + a=0x00000020; + b=0xFFFFFFFE; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x00000000; + b=0xFFFFFFFF; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x78; + c=a/5; + c=c/4; + c=c/3; + c=c/2; + /* Before c must be 1 */ c=0; + + a=0x10000000; + c=a/0xFFFFFFFF; + /* Before c must be 0 */ c=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/066.div/Makefile b/pdl/riscv/tests/acstone-programs/066.div/Makefile new file mode 100644 index 0000000..c3931c0 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/066.div/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 066.div +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/067.div/067.div.c b/pdl/riscv/tests/acstone-programs/067.div/067.div.c new file mode 100644 index 0000000..ddeab25 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/067.div/067.div.c @@ -0,0 +1,109 @@ +/** + * @file 067.div.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed long long int division. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed long long int a,b,c; + + a=0xFFFFFFFFFFFFFFFFLL; + b=0x0000000000000001LL; + c=a/b; + /* Before c must be -1 */ c=0; + + a=0x000000000000000FLL; + b=0x0000000000000003LL; + c=a/b; + /* Before c must be 5 */ c=0; + + a=0xAAAAAAAAAAAAAAAALL; + b=0x5555555555555555LL; + c=a/b; + /* Before c must be -1 */ c=0; + + a=0x7FFFFFFFFFFFFFFFLL; + b=0xFFFFFFFFFFFFFFFFLL; + c=a/b; + /* Before c must be -9223372036854775807 */ c=0; + + a=0x0000000000000000LL; + b=0x8000000000000000LL; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x0000000000000030LL; + b=0x0000000000000005LL; + c=a/b; + /* Before c must be 9 */ c=0; + + a=0xFFFFFFFFFFFFFFFFLL; + b=0xFFFFFFFFFFFFFFFFLL; + c=a/b; + /* Before c must be 1 */ c=0; + + a=0xFFFFFFFFFFFFFFFELL; + b=0x0000000000000010LL; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x0000000000000020LL; + b=0xFFFFFFFFFFFFFFFELL; + c=a/b; + /* Before c must be -16 */ c=0; + + a=0x0000000000000000LL; + b=0xFFFFFFFFFFFFFFFFLL; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x0000000000000078LL; + c=a/5; + c=c/4; + c=c/3; + c=c/2; + /* Before c must be 1 */ c=0; + + a=0x1000000000000000LL; + c=a/(-1); + /* Before c must be -1152921504606846976 */ c=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/067.div/Makefile b/pdl/riscv/tests/acstone-programs/067.div/Makefile new file mode 100644 index 0000000..b431425 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/067.div/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 067.div +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/068.div/068.div.c b/pdl/riscv/tests/acstone-programs/068.div/068.div.c new file mode 100644 index 0000000..c2bde30 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/068.div/068.div.c @@ -0,0 +1,109 @@ +/** + * @file 068.div.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses unsigned long long int division. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned long long int a,b,c; + + a=0xFFFFFFFFFFFFFFFFULL; + b=0x0000000000000001ULL; + c=a/b; + /* Before c must be 18446744073709551615 */ c=0; + + a=0x000000000000000FULL; + b=0x0000000000000003ULL; + c=a/b; + /* Before c must be 5 */ c=0; + + a=0xAAAAAAAAAAAAAAAAULL; + b=0x5555555555555555ULL; + c=a/b; + /* Before c must be 2 */ c=0; + + a=0x7FFFFFFFFFFFFFFFULL; + b=0xFFFFFFFFFFFFFFFFULL; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x0000000000000000ULL; + b=0x8000000000000000ULL; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x0000000000000030ULL; + b=0x0000000000000005ULL; + c=a/b; + /* Before c must be 9 */ c=0; + + a=0xFFFFFFFFFFFFFFFFULL; + b=0xFFFFFFFFFFFFFFFFULL; + c=a/b; + /* Before c must be 1 */ c=0; + + a=0xFFFFFFFFFFFFFFFEULL; + b=0x0000000000000010ULL; + c=a/b; + /* Before c must be 1152921504606846975 */ c=0; + + a=0x0000000000000020ULL; + b=0xFFFFFFFFFFFFFFFEULL; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x0000000000000000ULL; + b=0xFFFFFFFFFFFFFFFFULL; + c=a/b; + /* Before c must be 0 */ c=0; + + a=0x78; + c=a/5; + c=c/4; + c=c/3; + c=c/2; + /* Before c must be 1 */ c=0; + + a=0x1000000000000000ULL; + c=a/0xFFFFFFFFFFFFFFFFULL; + /* Before c must be 0 */ c=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/068.div/Makefile b/pdl/riscv/tests/acstone-programs/068.div/Makefile new file mode 100644 index 0000000..bf8849e --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/068.div/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 068.div +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/071.bool/071.bool.c b/pdl/riscv/tests/acstone-programs/071.bool/071.bool.c new file mode 100644 index 0000000..7d8fe7d --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/071.bool/071.bool.c @@ -0,0 +1,143 @@ +/** + * @file 071.bool.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses char boolean operators. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned char a,b,c,d,e,f,g,h,i,j; + + a=0xFF; + b=0xFF; + c=a|b; + /* Before c must be 255 */ c=0; + d=a&b; + /* Before d must be 255 */ d=0; + e=a^b; + /* Before e must be 0 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 0 */ g=0; + h=~(a^b); + /* Before h must be 255 */ h=0; + i=~a; + /* Before i must be 0 */ i=0; + j=~b; + /* Before j must be 0 */ j=0; + + a=0x0F; + b=0xF0; + c=a|b; + /* Before c must be 255 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 255 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 255 */ g=0; + h=~(a^b); + /* Before h must be 0 */ h=0; + i=~a; + /* Before i must be 240 */ i=0; + j=~b; + /* Before j must be 15 */ j=0; + + a=0xFF; + b=0x00; + c=a|b; + /* Before c must be 255 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 255 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 255 */ g=0; + h=~(a^b); + /* Before h must be 0 */ h=0; + i=~a; + /* Before i must be 0 */ i=0; + j=~b; + /* Before j must be 255 */ j=0; + + a=0x55; + b=0xAA; + c=a|b; + /* Before c must be 255 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 255 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 255 */ g=0; + h=~(a^b); + /* Before h must be 0 */ h=0; + i=~a; + /* Before i must be 170 */ i=0; + j=~b; + /* Before j must be 85 */ j=0; + + a=0x00; + b=0x00; + c=a|b; + /* Before c must be 0 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 0 */ e=0; + f=~(a|b); + /* Before f must be 255 */ f=0; + g=~(a&b); + /* Before g must be 255 */ g=0; + h=~(a^b); + /* Before h must be 255 */ h=0; + i=~a; + /* Before i must be 255 */ i=0; + j=~b; + /* Before j must be 255 */ j=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/071.bool/Makefile b/pdl/riscv/tests/acstone-programs/071.bool/Makefile new file mode 100644 index 0000000..a01ea3c --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/071.bool/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 071.bool +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/072.bool/072.bool.c b/pdl/riscv/tests/acstone-programs/072.bool/072.bool.c new file mode 100644 index 0000000..c338276 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/072.bool/072.bool.c @@ -0,0 +1,143 @@ +/** + * @file 072.bool.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses short int boolean operators. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned short int a,b,c,d,e,f,g,h,i,j; + + a=0xFFFF; + b=0xFFFF; + c=a|b; + /* Before c must be 65535 */ c=0; + d=a&b; + /* Before d must be 65535 */ d=0; + e=a^b; + /* Before e must be 0 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 0 */ g=0; + h=~(a^b); + /* Before h must be 65535 */ h=0; + i=~a; + /* Before i must be 0 */ i=0; + j=~b; + /* Before j must be 0 */ j=0; + + a=0x0F0F; + b=0xF0F0; + c=a|b; + /* Before c must be 65535 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 65535 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 65535 */ g=0; + h=~(a^b); + /* Before h must be 0 */ h=0; + i=~a; + /* Before i must be 61680 */ i=0; + j=~b; + /* Before j must be 3855 */ j=0; + + a=0xFFFF; + b=0x0000; + c=a|b; + /* Before c must be 65535 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 65535 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 65535 */ g=0; + h=~(a^b); + /* Before h must be 0 */ h=0; + i=~a; + /* Before i must be 0 */ i=0; + j=~b; + /* Before j must be 65535 */ j=0; + + a=0x5555; + b=0xAAAA; + c=a|b; + /* Before c must be 65535 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 65535 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 65535 */ g=0; + h=~(a^b); + /* Before h must be 0 */ h=0; + i=~a; + /* Before i must be 43690 */ i=0; + j=~b; + /* Before j must be 21845 */ j=0; + + a=0x0000; + b=0x0000; + c=a|b; + /* Before c must be 0 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 0 */ e=0; + f=~(a|b); + /* Before f must be 65535 */ f=0; + g=~(a&b); + /* Before g must be 65535 */ g=0; + h=~(a^b); + /* Before h must be 65535 */ h=0; + i=~a; + /* Before i must be 65535 */ i=0; + j=~b; + /* Before j must be 65535 */ j=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/072.bool/Makefile b/pdl/riscv/tests/acstone-programs/072.bool/Makefile new file mode 100644 index 0000000..d4986e1 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/072.bool/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 072.bool +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/073.bool/073.bool.c b/pdl/riscv/tests/acstone-programs/073.bool/073.bool.c new file mode 100644 index 0000000..588bf41 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/073.bool/073.bool.c @@ -0,0 +1,143 @@ +/** + * @file 073.bool.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses int boolean operators. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned int a,b,c,d,e,f,g,h,i,j; + + a=0xFFFFFFFF; + b=0xFFFFFFFF; + c=a|b; + /* Before c must be 4294967295 */ c=0; + d=a&b; + /* Before d must be 4294967295 */ d=0; + e=a^b; + /* Before e must be 0 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 0 */ g=0; + h=~(a^b); + /* Before h must be 4294967295 */ h=0; + i=~a; + /* Before i must be 0 */ i=0; + j=~b; + /* Before j must be 0 */ j=0; + + a=0x0F0F0F0F; + b=0xF0F0F0F0; + c=a|b; + /* Before c must be 4294967295 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 4294967295 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 4294967295 */ g=0; + h=~(a^b); + /* Before h must be 0 */ h=0; + i=~a; + /* Before i must be 4042322160 */ i=0; + j=~b; + /* Before j must be 252645135 */ j=0; + + a=0xFFFFFFFF; + b=0x00000000; + c=a|b; + /* Before c must be 4294967295 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 4294967295 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 4294967295 */ g=0; + h=~(a^b); + /* Before h must be 0 */ h=0; + i=~a; + /* Before i must be 0 */ i=0; + j=~b; + /* Before j must be 4294967295 */ j=0; + + a=0x55555555; + b=0xAAAAAAAA; + c=a|b; + /* Before c must be 4294967295 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 4294967295 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 4294967295 */ g=0; + h=~(a^b); + /* Before h must be 0 */ h=0; + i=~a; + /* Before i must be 2863311530 */ i=0; + j=~b; + /* Before j must be 1431655765 */ j=0; + + a=0x00000000; + b=0x00000000; + c=a|b; + /* Before c must be 0 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 0 */ e=0; + f=~(a|b); + /* Before f must be 4294967295 */ f=0; + g=~(a&b); + /* Before g must be 4294967295 */ g=0; + h=~(a^b); + /* Before h must be 4294967295 */ h=0; + i=~a; + /* Before i must be 4294967295 */ i=0; + j=~b; + /* Before j must be 4294967295 */ j=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/073.bool/Makefile b/pdl/riscv/tests/acstone-programs/073.bool/Makefile new file mode 100644 index 0000000..e2fc9a7 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/073.bool/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 073.bool +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/074.bool/074.bool.c b/pdl/riscv/tests/acstone-programs/074.bool/074.bool.c new file mode 100644 index 0000000..3c3777c --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/074.bool/074.bool.c @@ -0,0 +1,143 @@ +/** + * @file 074.bool.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses long long int boolean operators. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned long long int a,b,c,d,e,f,g,h,i,j; + + a=0xFFFFFFFFFFFFFFFFULL; + b=0xFFFFFFFFFFFFFFFFULL; + c=a|b; + /* Before c must be 18446744073709551615 */ c=0; + d=a&b; + /* Before d must be 18446744073709551615 */ d=0; + e=a^b; + /* Before e must be 0 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 0 */ g=0; + h=~(a^b); + /* Before h must be 18446744073709551615 */ h=0; + i=~a; + /* Before i must be 0 */ i=0; + j=~b; + /* Before j must be 0 */ j=0; + + a=0x0F0F0F0F0F0F0F0FULL; + b=0xF0F0F0F0F0F0F0F0ULL; + c=a|b; + /* Before c must be 18446744073709551615 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 18446744073709551615 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 18446744073709551615 */ g=0; + h=~(a^b); + /* Before h must be 0 */ h=0; + i=~a; + /* Before i must be 17361641481138401520 */ i=0; + j=~b; + /* Before j must be 1085102592571150095 */ j=0; + + a=0xFFFFFFFFFFFFFFFFULL; + b=0x0000000000000000ULL; + c=a|b; + /* Before c must be 18446744073709551615 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 18446744073709551615 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 18446744073709551615 */ g=0; + h=~(a^b); + /* Before h must be 0 */ h=0; + i=~a; + /* Before i must be 0 */ i=0; + j=~b; + /* Before j must be 18446744073709551615 */ j=0; + + a=0x5555555555555555ULL; + b=0xAAAAAAAAAAAAAAAAULL; + c=a|b; + /* Before c must be 18446744073709551615 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 18446744073709551615 */ e=0; + f=~(a|b); + /* Before f must be 0 */ f=0; + g=~(a&b); + /* Before g must be 18446744073709551615 */ g=0; + h=~(a^b); + /* Before h must be 0 */ h=0; + i=~a; + /* Before i must be 12297829382473034410 */ i=0; + j=~b; + /* Before j must be 6148914691236517205 */ j=0; + + a=0x0000000000000000ULL; + b=0x0000000000000000ULL; + c=a|b; + /* Before c must be 0 */ c=0; + d=a&b; + /* Before d must be 0 */ d=0; + e=a^b; + /* Before e must be 0 */ e=0; + f=~(a|b); + /* Before f must be 18446744073709551615 */ f=0; + g=~(a&b); + /* Before g must be 18446744073709551615 */ g=0; + h=~(a^b); + /* Before h must be 18446744073709551615 */ h=0; + i=~a; + /* Before i must be 18446744073709551615 */ i=0; + j=~b; + /* Before j must be 18446744073709551615 */ j=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/074.bool/Makefile b/pdl/riscv/tests/acstone-programs/074.bool/Makefile new file mode 100644 index 0000000..c572dbe --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/074.bool/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 074.bool +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/075.bool/075.bool.c b/pdl/riscv/tests/acstone-programs/075.bool/075.bool.c new file mode 100644 index 0000000..6534de0 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/075.bool/075.bool.c @@ -0,0 +1,64 @@ +/** + * @file 075.bool.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses various boolean operators. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned long long int a,b; + + a=0xAAAAAAAAAAAAAAAAULL; + b=a|0xF0F0F0F0F0F0F0F0ULL; + /* Before b must be 18085043209519168250 */ b=0; + b=a&0xF0F0F0F0F0F0F0F0ULL; + /* Before b must be 11574427654092267680 */ b=0; + b=a^0xF0F0F0F0F0F0F0F0ULL; + /* Before b must be 6510615555426900570 */ b=0; + b=~(a|0xF0F0F0F0F0F0F0F0ULL); + /* Before b must be 361700864190383365 */ b=0; + b=~(a&0xF0F0F0F0F0F0F0F0ULL); + /* Before b must be 6872316419617283935 */ b=0; + b=~(a^0xF0F0F0F0F0F0F0F0ULL); + /* Before b must be 11936128518282651045 */ b=0; + b=~0xF0F0F0F0F0F0F0F0ULL; + /* Before b must be 1085102592571150095 */ b=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/075.bool/Makefile b/pdl/riscv/tests/acstone-programs/075.bool/Makefile new file mode 100644 index 0000000..c6f5171 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/075.bool/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 075.bool +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/081.shift/081.shift.c b/pdl/riscv/tests/acstone-programs/081.shift/081.shift.c new file mode 100644 index 0000000..122a95f --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/081.shift/081.shift.c @@ -0,0 +1,149 @@ +/** + * @file 081.shift.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed and unsigned char shifts. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned char uc; + signed char sc; + + + uc=0xFF; + uc=uc>>1; + /* Before uc must be 127 */ uc=0; + + uc=0x00; + uc=uc>>1; + /* Before uc must be 0 */ uc=0; + + uc=0x01; + uc=uc>>1; + /* Before uc must be 0 */ uc=0; + + uc=0x80; + uc=uc>>1; + /* Before uc must be 64 */ uc=0; + + uc=0xAA; + uc=uc>>1; + /* Before uc must be 85 */ uc=0; + + uc=0x3C; + uc=uc>>2; + /* Before uc must be 15 */ uc=0; + + + sc=0xFF; + sc=sc>>1; + /* Before sc must be -1 */ sc=0; + + sc=0x00; + sc=sc>>1; + /* Before sc must be 0 */ sc=0; + + sc=0x01; + sc=sc>>1; + /* Before sc must be 0 */ sc=0; + + sc=0x80; + sc=sc>>1; + /* Before sc must be -64 */ sc=0; + + sc=0xAA; + sc=sc>>1; + /* Before sc must be -43 */ sc=0; + + sc=0x3C; + sc=sc>>2; + /* Before sc must be 15 */ sc=0; + + + uc=0xFF; + uc=uc<<1; + /* Before uc must be 254 */ uc=0; + + uc=0x00; + uc=uc<<1; + /* Before uc must be 0 */ uc=0; + + uc=0x01; + uc=uc<<1; + /* Before uc must be 2 */ uc=0; + + uc=0x80; + uc=uc<<1; + /* Before uc must be 0 */ uc=0; + + uc=0xAA; + uc=uc<<1; + /* Before uc must be 84 */ uc=0; + + uc=0x3C; + uc=uc<<2; + /* Before uc must be 240 */ uc=0; + + + sc=0xFF; + sc=sc<<1; + /* Before sc must be -2 */ sc=0; + + sc=0x00; + sc=sc<<1; + /* Before sc must be 0 */ sc=0; + + sc=0x01; + sc=sc<<1; + /* Before sc must be 2 */ sc=0; + + sc=0x80; + sc=sc<<1; + /* Before sc must be 0 */ sc=0; + + sc=0xAA; + sc=sc<<1; + /* Before sc must be 84 */ sc=0; + + sc=0x3C; + sc=sc<<2; + /* Before sc must be -16 */ sc=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/081.shift/Makefile b/pdl/riscv/tests/acstone-programs/081.shift/Makefile new file mode 100644 index 0000000..a87a0da --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/081.shift/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 081.shift +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/082.shift/082.shift.c b/pdl/riscv/tests/acstone-programs/082.shift/082.shift.c new file mode 100644 index 0000000..3219489 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/082.shift/082.shift.c @@ -0,0 +1,149 @@ +/** + * @file 082.shift.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed and unsigned short int shifts. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned short int usi; + signed short int ssi; + + + usi=0xFFFF; + usi=usi>>1; + /* Before usi must be 32767 */ usi=0; + + usi=0x0000; + usi=usi>>1; + /* Before usi must be 0 */ usi=0; + + usi=0x0001; + usi=usi>>1; + /* Before usi must be 0 */ usi=0; + + usi=0x8000; + usi=usi>>1; + /* Before usi must be 16384 */ usi=0; + + usi=0xAAAA; + usi=usi>>1; + /* Before usi must be 21845 */ usi=0; + + usi=0x03C0; + usi=usi>>2; + /* Before usi must be 240 */ usi=0; + + + ssi=0xFFFF; + ssi=ssi>>1; + /* Before ssi must be -1 */ ssi=0; + + ssi=0x0000; + ssi=ssi>>1; + /* Before ssi must be 0 */ ssi=0; + + ssi=0x0001; + ssi=ssi>>1; + /* Before ssi must be 0 */ ssi=0; + + ssi=0x8000; + ssi=ssi>>1; + /* Before ssi must be -16384 */ ssi=0; + + ssi=0xAAAA; + ssi=ssi>>1; + /* Before ssi must be -10923 */ ssi=0; + + ssi=0x03C0; + ssi=ssi>>2; + /* Before ssi must be 240 */ ssi=0; + + + usi=0xFFFF; + usi=usi<<1; + /* Before usi must be 65534 */ usi=0; + + usi=0x0000; + usi=usi<<1; + /* Before usi must be 0 */ usi=0; + + usi=0x0001; + usi=usi<<1; + /* Before usi must be 2 */ usi=0; + + usi=0x8000; + usi=usi<<1; + /* Before usi must be 0 */ usi=0; + + usi=0xAAAA; + usi=usi<<1; + /* Before usi must be 21844 */ usi=0; + + usi=0x03C0; + usi=usi<<2; + /* Before usi must be 3840 */ usi=0; + + + ssi=0xFFFF; + ssi=ssi<<1; + /* Before ssi must be -2 */ ssi=0; + + ssi=0x0000; + ssi=ssi<<1; + /* Before ssi must be 0 */ ssi=0; + + ssi=0x0001; + ssi=ssi<<1; + /* Before ssi must be 2 */ ssi=0; + + ssi=0x8000; + ssi=ssi<<1; + /* Before ssi must be 0 */ ssi=0; + + ssi=0xAAAA; + ssi=ssi<<1; + /* Before ssi must be 21844 */ ssi=0; + + ssi=0x03C0; + ssi=ssi<<2; + /* Before ssi must be 3840 */ ssi=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/082.shift/Makefile b/pdl/riscv/tests/acstone-programs/082.shift/Makefile new file mode 100644 index 0000000..6d499d9 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/082.shift/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 082.shift +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/083.shift/083.shift.c b/pdl/riscv/tests/acstone-programs/083.shift/083.shift.c new file mode 100644 index 0000000..74a01b1 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/083.shift/083.shift.c @@ -0,0 +1,149 @@ +/** + * @file 083.shift.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed and unsigned int shifts. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned int ui; + signed int si; + + + ui=0xFFFFFFFF; + ui=ui>>1; + /* Before ui must be 2147483647 */ ui=0; + + ui=0x00000000; + ui=ui>>1; + /* Before ui must be 0 */ ui=0; + + ui=0x00000001; + ui=ui>>1; + /* Before ui must be 0 */ ui=0; + + ui=0x80000000; + ui=ui>>1; + /* Before ui must be 1073741824 */ ui=0; + + ui=0xAAAAAAAA; + ui=ui>>1; + /* Before ui must be 1431655765 */ ui=0; + + ui=0x0003C000; + ui=ui>>2; + /* Before ui must be 61440 */ ui=0; + + + si=0xFFFFFFFF; + si=si>>1; + /* Before si must be -1 */ si=0; + + si=0x00000000; + si=si>>1; + /* Before si must be 0 */ si=0; + + si=0x00000001; + si=si>>1; + /* Before si must be 0 */ si=0; + + si=0x80000000; + si=si>>1; + /* Before si must be -1073741824 */ si=0; + + si=0xAAAAAAAA; + si=si>>1; + /* Before si must be -715827883 */ si=0; + + si=0x0003C000; + si=si>>2; + /* Before si must be 61440 */ si=0; + + + ui=0xFFFFFFFF; + ui=ui<<1; + /* Before ui must be 4294967294 */ ui=0; + + ui=0x00000000; + ui=ui<<1; + /* Before ui must be 0 */ ui=0; + + ui=0x00000001; + ui=ui<<1; + /* Before ui must be 2 */ ui=0; + + ui=0x80000000; + ui=ui<<1; + /* Before ui must be 0 */ ui=0; + + ui=0xAAAAAAAA; + ui=ui<<1; + /* Before ui must be 1431655764 */ ui=0; + + ui=0x0003C000; + ui=ui<<2; + /* Before ui must be 983040 */ ui=0; + + + si=0xFFFFFFFF; + si=si<<1; + /* Before si must be -2 */ si=0; + + si=0x00000000; + si=si<<1; + /* Before si must be 0 */ si=0; + + si=0x00000001; + si=si<<1; + /* Before si must be 2 */ si=0; + + si=0x80000000; + si=si<<1; + /* Before si must be 0 */ si=0; + + si=0xAAAAAAAA; + si=si<<1; + /* Before si must be 1431655764 */ si=0; + + si=0x0003C000; + si=si<<2; + /* Before si must be 983040 */ si=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/083.shift/Makefile b/pdl/riscv/tests/acstone-programs/083.shift/Makefile new file mode 100644 index 0000000..62bef5e --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/083.shift/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 083.shift +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/084.shift/084.shift.c b/pdl/riscv/tests/acstone-programs/084.shift/084.shift.c new file mode 100644 index 0000000..d25fb1f --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/084.shift/084.shift.c @@ -0,0 +1,148 @@ +/** + * @file 084.shift.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed and unsigned long long int shifts. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned long long int uli; + signed long long int sli; + + uli=0xFFFFFFFFFFFFFFFFULL; + uli=uli>>1; + /* Before uli must be 9223372036854775807 */ uli=0; + + uli=0x0000000000000000ULL; + uli=uli>>1; + /* Before uli must be 0 */ uli=0; + + uli=0x0000000000000001ULL; + uli=uli>>1; + /* Before uli must be 0 */ uli=0; + + uli=0x8000000000000000ULL; + uli=uli>>1; + /* Before uli must be 4611686018427387904 */ uli=0; + + uli=0xAAAAAAAAAAAAAAAAULL; + uli=uli>>1; + /* Before uli must be 6148914691236517205 */ uli=0; + + uli=0x00000003C0000000ULL; + uli=uli>>2; + /* Before uli must be 4026531840 */ uli=0; + + + sli=0xFFFFFFFFFFFFFFFFLL; + sli=sli>>1; + /* Before sli must be -1 */ sli=0; + + sli=0x0000000000000000LL; + sli=sli>>1; + /* Before sli must be 0 */ sli=0; + + sli=0x0000000000000001LL; + sli=sli>>1; + /* Before sli must be 0 */ sli=0; + + sli=0x8000000000000000LL; + sli=sli>>1; + /* Before sli must be -4611686018427387904 */ sli=0; + + sli=0xAAAAAAAAAAAAAAAALL; + sli=sli>>1; + /* Before sli must be -3074457345618258603 */ sli=0; + + sli=0x00000003C0000000LL; + sli=sli>>2; + /* Before sli must be 4026531840 */ sli=0; + + + uli=0xFFFFFFFFFFFFFFFFULL; + uli=uli<<1; + /* Before uli must be 18446744073709551614 */ uli=0; + + uli=0x0000000000000000ULL; + uli=uli<<1; + /* Before uli must be 0 */ uli=0; + + uli=0x0000000000000001ULL; + uli=uli<<1; + /* Before uli must be 2 */ uli=0; + + uli=0x8000000000000000ULL; + uli=uli<<1; + /* Before uli must be 0 */ uli=0; + + uli=0xAAAAAAAAAAAAAAAAULL; + uli=uli<<1; + /* Before uli must be 6148914691236517204 */ uli=0; + + uli=0x00000003C0000000ULL; + uli=uli<<2; + /* Before uli must be 64424509440 */ uli=0; + + + sli=0xFFFFFFFFFFFFFFFFLL; + sli=sli<<1; + /* Before sli must be -2 */ sli=0; + + sli=0x0000000000000000LL; + sli=sli<<1; + /* Before sli must be 0 */ sli=0; + + sli=0x0000000000000001LL; + sli=sli<<1; + /* Before sli must be 2 */ sli=0; + + sli=0x8000000000000000LL; + sli=sli<<1; + /* Before sli must be 0 */ sli=0; + + sli=0xAAAAAAAAAAAAAAAALL; + sli=sli<<1; + /* Before sli must be 6148914691236517204 */ sli=0; + + sli=0x00000003C0000000LL; + sli=sli<<2; + /* Before sli must be 64424509440 */ sli=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/084.shift/Makefile b/pdl/riscv/tests/acstone-programs/084.shift/Makefile new file mode 100644 index 0000000..6c1bb06 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/084.shift/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 084.shift +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/085.shift/085.shift.c b/pdl/riscv/tests/acstone-programs/085.shift/085.shift.c new file mode 100644 index 0000000..ad9fb7a --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/085.shift/085.shift.c @@ -0,0 +1,73 @@ +/** + * @file 085.shift.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses shifts and some logic operators. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned long long int abcdefgh; + unsigned long long int hgfedcba; + unsigned int abcd; + unsigned int dcba; + unsigned short int ab; + unsigned short int ba; + + abcdefgh=0x8899AABBCCDDEEFFULL; + hgfedcba=(((abcdefgh & 0xFF00000000000000ULL)>>56) | + ((abcdefgh & 0x00FF000000000000ULL)>>40) | + ((abcdefgh & 0x0000FF0000000000ULL)>>24) | + ((abcdefgh & 0x000000FF00000000ULL)>>8) | + ((abcdefgh & 0x00000000FF000000ULL)<<8) | + ((abcdefgh & 0x0000000000FF0000ULL)<<24) | + ((abcdefgh & 0x000000000000FF00ULL)<<40) | + ((abcdefgh & 0x00000000000000FFULL)<<56)); + /* Before hgfedcba must be 18441921395520346504 */ hgfedcba=0; + + abcd=0xAABBCCDD; + dcba=(((abcd & 0x000000FF)<<24) | ((abcd & 0x0000FF00)<<8) | + ((abcd & 0x00FF0000)>>8) | ((abcd & 0xFF000000)>>24)); + /* Before dcba must be 3721182122 */ dcba=0; + + ab=0xAABB; + ba=(((ab & 0x00FF)<<8) | ((ab & 0xFF00)>>8)); + /* Before ba must be 48042 */ ba=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/085.shift/Makefile b/pdl/riscv/tests/acstone-programs/085.shift/Makefile new file mode 100644 index 0000000..cc069dc --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/085.shift/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 085.shift +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/111.if/111.if.c b/pdl/riscv/tests/acstone-programs/111.if/111.if.c new file mode 100644 index 0000000..88c24c6 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/111.if/111.if.c @@ -0,0 +1,244 @@ +/** + * @file 111.if.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses signed char ifs + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed char a,b; + unsigned char c_active_else,c_inactive_else; + unsigned char c_active_then,c_inactive_then; + + c_active_then=0; + c_active_else=0; + c_inactive_then=0; + c_inactive_else=0; + + a=0x00; + b=0xFF; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0xFF; + b=0xFE; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x01; + b=0x02; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + a=0x0F; + b=0x0F; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 3 */ c_active_then=0; + /* Before, c_active_else must be 2 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x01; + b=0xFF; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/111.if/Makefile b/pdl/riscv/tests/acstone-programs/111.if/Makefile new file mode 100644 index 0000000..cf1ef1e --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/111.if/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 111.if +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/112.if/112.if.c b/pdl/riscv/tests/acstone-programs/112.if/112.if.c new file mode 100644 index 0000000..d4ff964 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/112.if/112.if.c @@ -0,0 +1,244 @@ +/** + * @file 112.if.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses unsigned char ifs + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned char a,b; + unsigned char c_active_else,c_inactive_else; + unsigned char c_active_then,c_inactive_then; + + c_active_then=0; + c_active_else=0; + c_inactive_then=0; + c_inactive_else=0; + + a=0x00; + b=0xFF; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0xFF; + b=0xFE; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x01; + b=0x02; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + a=0x0F; + b=0x0F; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 3 */ c_active_then=0; + /* Before, c_active_else must be 2 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x01; + b=0xFF; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/112.if/Makefile b/pdl/riscv/tests/acstone-programs/112.if/Makefile new file mode 100644 index 0000000..3695088 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/112.if/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 112.if +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/113.if/113.if.c b/pdl/riscv/tests/acstone-programs/113.if/113.if.c new file mode 100644 index 0000000..007c8d5 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/113.if/113.if.c @@ -0,0 +1,244 @@ +/** + * @file 113.if.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses signed short int ifs + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed short int a,b; + unsigned char c_active_else,c_inactive_else; + unsigned char c_active_then,c_inactive_then; + + c_active_then=0; + c_active_else=0; + c_inactive_then=0; + c_inactive_else=0; + + a=0x0000; + b=0xFFFF; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0xFFFF; + b=0xFFFE; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x0001; + b=0x0002; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + a=0x000F; + b=0x000F; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 3 */ c_active_then=0; + /* Before, c_active_else must be 2 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x0001; + b=0xFFFF; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/113.if/Makefile b/pdl/riscv/tests/acstone-programs/113.if/Makefile new file mode 100644 index 0000000..a7bf984 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/113.if/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 113.if +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/114.if/114.if.c b/pdl/riscv/tests/acstone-programs/114.if/114.if.c new file mode 100644 index 0000000..f33f896 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/114.if/114.if.c @@ -0,0 +1,244 @@ +/** + * @file 114.if.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses unsigned short int ifs + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned short int a,b; + unsigned char c_active_else,c_inactive_else; + unsigned char c_active_then,c_inactive_then; + + c_active_then=0; + c_active_else=0; + c_inactive_then=0; + c_inactive_else=0; + + a=0x0000; + b=0xFFFF; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0xFFFF; + b=0xFFFE; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x0001; + b=0x0002; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + a=0x000F; + b=0x000F; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 3 */ c_active_then=0; + /* Before, c_active_else must be 2 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x0001; + b=0xFFFF; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/114.if/Makefile b/pdl/riscv/tests/acstone-programs/114.if/Makefile new file mode 100644 index 0000000..e593b50 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/114.if/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 114.if +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/115.if/115.if.c b/pdl/riscv/tests/acstone-programs/115.if/115.if.c new file mode 100644 index 0000000..010db7b --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/115.if/115.if.c @@ -0,0 +1,244 @@ +/** + * @file 115.if.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses signed int ifs + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed int a,b; + unsigned char c_active_else,c_inactive_else; + unsigned char c_active_then,c_inactive_then; + + c_active_then=0; + c_active_else=0; + c_inactive_then=0; + c_inactive_else=0; + + a=0x00000000; + b=0xFFFFFFFF; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0xFFFFFFFF; + b=0xFFFFFFFE; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x00000001; + b=0x00000002; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + a=0x0000000F; + b=0x0000000F; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 3 */ c_active_then=0; + /* Before, c_active_else must be 2 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x00000001; + b=0xFFFFFFFF; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/115.if/Makefile b/pdl/riscv/tests/acstone-programs/115.if/Makefile new file mode 100644 index 0000000..29f3f86 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/115.if/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 115.if +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/116.if/116.if.c b/pdl/riscv/tests/acstone-programs/116.if/116.if.c new file mode 100644 index 0000000..73e9176 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/116.if/116.if.c @@ -0,0 +1,244 @@ +/** + * @file 116.if.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses unsigned int ifs + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned int a,b; + unsigned char c_active_else,c_inactive_else; + unsigned char c_active_then,c_inactive_then; + + c_active_then=0; + c_active_else=0; + c_inactive_then=0; + c_inactive_else=0; + + a=0x00000000; + b=0xFFFFFFFF; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0xFFFFFFFF; + b=0xFFFFFFFE; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x00000001; + b=0x00000002; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + a=0x0000000F; + b=0x0000000F; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 3 */ c_active_then=0; + /* Before, c_active_else must be 2 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x00000001; + b=0xFFFFFFFF; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/116.if/Makefile b/pdl/riscv/tests/acstone-programs/116.if/Makefile new file mode 100644 index 0000000..39a812b --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/116.if/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 116.if +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/117.if/117.if.c b/pdl/riscv/tests/acstone-programs/117.if/117.if.c new file mode 100644 index 0000000..0d283fc --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/117.if/117.if.c @@ -0,0 +1,244 @@ +/** + * @file 117.if.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses signed long long int ifs + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed long long int a,b; + unsigned char c_active_else,c_inactive_else; + unsigned char c_active_then,c_inactive_then; + + c_active_then=0; + c_active_else=0; + c_inactive_then=0; + c_inactive_else=0; + + a=0x0000000000000000LL; + b=0xFFFFFFFFFFFFFFFFLL; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0xFFFFFFFFFFFFFFFFLL; + b=0xFFFFFFFFFFFFFFFELL; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x0000000000000001LL; + b=0x0000000000000002LL; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + a=0x000000000000000FLL; + b=0x000000000000000FLL; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 3 */ c_active_then=0; + /* Before, c_active_else must be 2 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x0000000000000001LL; + b=0xFFFFFFFFFFFFFFFFLL; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/117.if/Makefile b/pdl/riscv/tests/acstone-programs/117.if/Makefile new file mode 100644 index 0000000..549228c --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/117.if/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 117.if +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/118.if/118.if.c b/pdl/riscv/tests/acstone-programs/118.if/118.if.c new file mode 100644 index 0000000..6cf4b2b --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/118.if/118.if.c @@ -0,0 +1,244 @@ +/** + * @file 118.if.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses unsigned long long int ifs + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned long long int a,b; + unsigned char c_active_else,c_inactive_else; + unsigned char c_active_then,c_inactive_then; + + c_active_then=0; + c_active_else=0; + c_inactive_then=0; + c_inactive_else=0; + + a=0x0000000000000000ULL; + b=0xFFFFFFFFFFFFFFFFULL; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0xFFFFFFFFFFFFFFFFULL; + b=0xFFFFFFFFFFFFFFFEULL; + if(a > b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x0000000000000001ULL; + b=0x0000000000000002ULL; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + a=0x000000000000000FULL; + b=0x000000000000000FULL; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a == b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a >= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 3 */ c_active_then=0; + /* Before, c_active_else must be 2 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + a=0x0000000000000001ULL; + b=0xFFFFFFFFFFFFFFFFULL; + if(a > b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a < b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + if(a == b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a >= b) { + c_inactive_then++; /* $=FAILED! */ + } + else { + c_active_else++; /* $=OK! */ + } + if(a <= b) { + c_active_then++; /* $=OK! */ + } + else { + c_inactive_else++; /* $=FAILED! */ + } + /* Before, c_active_then must be 2 */ c_active_then=0; + /* Before, c_active_else must be 3 */ c_active_else=0; + /* Before, c_inactive_then must be 0 */ c_inactive_then=0; + /* Before, c_inactive_else must be 0 */ c_inactive_else=0; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/118.if/Makefile b/pdl/riscv/tests/acstone-programs/118.if/Makefile new file mode 100644 index 0000000..0eb68ec --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/118.if/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 118.if +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/119.if/119.if.c b/pdl/riscv/tests/acstone-programs/119.if/119.if.c new file mode 100644 index 0000000..5884f95 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/119.if/119.if.c @@ -0,0 +1,131 @@ +/** + * @file 119.if.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses various ifs. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed char a; + unsigned char b; + signed short int c; + unsigned short int d; + signed int e; + unsigned int f; + signed long long int g; + unsigned long long int h; + + unsigned char ok,failed; + + ok=0; + failed=0; + a=0; + b=1; + c=2; + d=3; + e=4; + f=5; + g=6; + h=7; + + if(a==0) + if(b==1) + if(c==2) + if(d==3) + if(e==4) + if(f==5) + if(g==6) + if(h==7) + ok++; /* $= OK! */ + + if(a>=0) + if(b<=1) + if(c>=2) + if(d<=3) + if(e>=4) + if(f>=5) + if(g<=6) + if(h<=7) + ok++; /* $= OK! */ + + if(a>=-1) + if(b>=1) + if(c>=-2) + if(d>=3) + if(e>=-3) + if(f>=5) + if(g>=-4) + if(h>=7) + ok++; /* $= OK! */ + + if(a==0) + if(b==1) + if(c==2) + if(d==3) + if(e<4) + if(f==5) + if(g==6) + if(h==7) + failed++; /* $= FAILED! */ + + if(a>=0) + if(b<=1) + if(c>=2) + if(d<=3) + if(e>=4) + if(f>=5) + if(g<=6) + if(h==8) + failed++; /* $= FAILED! */ + + if(a==-1) + if(b>=1) + if(c>=-2) + if(d>=3) + if(e>=-3) + if(f>=5) + if(g>=-4) + if(h>=7) + failed++; /* $= FAILED! */ + + ok=0; /* Before ok must be 3 */ + failed=0; /* Before failed must be 0 */ + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/119.if/Makefile b/pdl/riscv/tests/acstone-programs/119.if/Makefile new file mode 100644 index 0000000..bfdfc9a --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/119.if/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 119.if +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/121.loop/121.loop.c b/pdl/riscv/tests/acstone-programs/121.loop/121.loop.c new file mode 100644 index 0000000..643fd0d --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/121.loop/121.loop.c @@ -0,0 +1,100 @@ +/** + * @file 121.loop.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses while loops. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned long long int cont; + + unsigned char a; + signed char b; + unsigned short int c; + signed short int d; + unsigned int e; + signed int f; + unsigned long long int g; + signed long long int h; + + cont=0; + + a=5; + while(a--) + cont++; + /* Before a must be 255 and cont 5 */ a=0; + + b=5; + while(b--) + cont++; + /* Before b must be -1 and cont 10 */ b=0; + + c=5; + while(c--) + cont++; + /* Before c must be 65535 and cont 15 */ c=0; + + d=5; + while(d--) + cont++; + /* Before d must be -1 and cont 20 */ d=0; + + e=5; + while(e--) + cont++; + /* Before e must be 4294967295 and cont 25 */ e=0; + + f=5; + while(f--) + cont++; + /* Before f must be -1 and cont 30 */ f=0; + + g=5; + while(g--) + cont++; + /* Before g must be 18446744073709551615 and cont 35 */ g=0; + + h=5; + while(h--) + cont++; + /* Before h must be -1 and cont 40 */ h=0; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/121.loop/Makefile b/pdl/riscv/tests/acstone-programs/121.loop/Makefile new file mode 100644 index 0000000..9457638 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/121.loop/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 121.loop +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/122.loop/122.loop.c b/pdl/riscv/tests/acstone-programs/122.loop/122.loop.c new file mode 100644 index 0000000..d7623bd --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/122.loop/122.loop.c @@ -0,0 +1,91 @@ +/** + * @file 122.loop.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses for loops. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned long long int cont; + + unsigned char a; + signed char b; + unsigned short int c; + signed short int d; + unsigned int e; + signed int f; + unsigned long long int g; + signed long long int h; + + cont=0; + + for(a=0;a<5;a++) + cont++; + /* Before a must be 5 and cont 5 */ a=0; + + for(b=0;b<5;b++) + cont++; + /* Before b must be 5 and cont 10 */ b=0; + + for(c=0;c<5;c++) + cont++; + /* Before c must be 5 and cont 15 */ c=0; + + for(d=0;d<5;d++) + cont++; + /* Before d must be 5 and cont 20 */ d=0; + + for(e=0;e<5;e++) + cont++; + /* Before e must be 5 and cont 25 */ e=0; + + for(f=0;f<5;f++) + cont++; + /* Before f must be 5 and cont 30 */ f=0; + + for(g=0;g<5;g++) + cont++; + /* Before g must be 5 and cont 35 */ g=0; + + for(h=0;h<5;h++) + cont++; + /* Before h must be 5 and cont 40 */ h=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/122.loop/Makefile b/pdl/riscv/tests/acstone-programs/122.loop/Makefile new file mode 100644 index 0000000..ff09422 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/122.loop/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 122.loop +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/123.loop/123.loop.c b/pdl/riscv/tests/acstone-programs/123.loop/123.loop.c new file mode 100644 index 0000000..36d74ba --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/123.loop/123.loop.c @@ -0,0 +1,89 @@ +/** + * @file 123.loop.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses a implemented unsigned multiplication + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned char count; + unsigned int C,A,Q,M; + unsigned long long int result; + + count=32; /* 32 bits * 32 bits = 64 bits */ + + /* Some variable */ + M=0x1314AB42; + Q=0xF1B34517; + A=0x00000000; + C=0x00000000; + + while(count!=0) { + + /* if q0 = 1 add */ + if(Q & 0x00000001) { + if(((unsigned long long int)A+ + (unsigned long long int)M) > 0xFFFFFFFF) /* Check if have carry */ + C=1; + else + C=0; + A=A+M; + } + + /* Shift */ + Q=Q>>1; + if(A & 0x00000001) + Q=(Q | 0x80000000); + A=A>>1; + if(C & 0x00000001) + A=(A | 0x80000000); + C=C>>1; + + /* Decrement counter */ + count--; + + } + + result=0; + result=((((unsigned long long int)(A)) << 32) | + ((unsigned long long int)(Q))); + /* Before result must be 1298111822488546542 */ result=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/123.loop/Makefile b/pdl/riscv/tests/acstone-programs/123.loop/Makefile new file mode 100644 index 0000000..54f9d3a --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/123.loop/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 123.loop +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/124.loop/124.loop.c b/pdl/riscv/tests/acstone-programs/124.loop/124.loop.c new file mode 100644 index 0000000..b0deaa9 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/124.loop/124.loop.c @@ -0,0 +1,104 @@ +/** + * @file 124.loop.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses a implemented signed multiplication (Booth) + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned char count; + unsigned int A,Q,Qmenos,M,mask; + signed long long int result; + + count=32; /* 32 bits * 32 bits = 64 bits */ + + /* Some variable */ + M=0x82348243; + Q=0x41378972; + Qmenos=0x00000000; + A=0x00000000; + + while(count!=0) { + + mask=(((Q<<1) & 0x00000002) | (Qmenos & 0x00000001)); + + switch(mask) { + + case 0x0: /* q0=0 and qm=0 */ + case 0x3: /* qo=1 and qm=1 */ + /* Nothing */ + break; + + case 0x2: /* q0=1 and qm=0 */ + A=A-M; + break; + + case 0x1: /* q0=0 and qm=1 */ + A=A+M; + break; + + } + + /* Shift */ + if(Q & 0x00000001) + Qmenos=1; + else + Qmenos=0; + + Q=Q>>1; + + if(A & 0x00000001) + Q=(Q | 0x80000000); + else + Q=(Q & 0x7FFFFFFF); + + A=A>>1; + if(A & 0x40000000) + A=(A | 0x80000000); + + count--; + } + + result=0; + result=((((unsigned long long int)(A)) << 32) | + ((unsigned long long int)(Q))); + /* Before result must be -2309208815826051882 */ result=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/124.loop/Makefile b/pdl/riscv/tests/acstone-programs/124.loop/Makefile new file mode 100644 index 0000000..f737c94 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/124.loop/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 124.loop +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/125.loop/125.loop.c b/pdl/riscv/tests/acstone-programs/125.loop/125.loop.c new file mode 100644 index 0000000..c78c796 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/125.loop/125.loop.c @@ -0,0 +1,73 @@ +/** + * @file 125.loop.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses a implemented simple strlen loop. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned char *ac="ArchC - Architecture Description Language\n"; + unsigned char *lsc="Computer System Laboratory\n"; + unsigned char *ic="Institute of Computing - UNICAMP\n"; + unsigned char *p; + unsigned int count; + + p=ac; + count=0; + while(*p) { /* strlen */ + p++; count++; + } + /* Before count must be 42 */ count=0; + + p=lsc; + count=0; + while(*p) { /* strlen */ + p++; count++; + } + /* Before count must be 27 */ count=0; + + p=ic; + count=0; + while(*p) { /* strlen */ + p++; count++; + } + /* Before count must be 33 */ count=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/125.loop/Makefile b/pdl/riscv/tests/acstone-programs/125.loop/Makefile new file mode 100644 index 0000000..d0b6e9e --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/125.loop/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 125.loop +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/126.loop/126.loop.c b/pdl/riscv/tests/acstone-programs/126.loop/126.loop.c new file mode 100644 index 0000000..1a6a1c1 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/126.loop/126.loop.c @@ -0,0 +1,73 @@ +/** + * @file 126.loop.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses implemented simple fatorial loop. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned long long int nu; + unsigned long long int resultu; + unsigned long long int iu; + + signed long long int ns; + signed long long int results; + signed long long int is; + + nu=25; + resultu=1; + iu=nu; + while(iu>1) { + resultu=resultu*iu; + iu--; + } + /* Before must be 7034535277573963776 */ resultu=0; + + ns=25; + results=1; + is=ns; + while(is>1) { + results=results*is; + is--; + } + /* Before must be 7034535277573963776 */ results=0; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/126.loop/Makefile b/pdl/riscv/tests/acstone-programs/126.loop/Makefile new file mode 100644 index 0000000..1511770 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/126.loop/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 126.loop +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/131.call/131.call.c b/pdl/riscv/tests/acstone-programs/131.call/131.call.c new file mode 100644 index 0000000..312f408 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/131.call/131.call.c @@ -0,0 +1,75 @@ +/** + * @file 131.call.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses calls functions arg int, ret int. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + int tmp; + + tmp=funcmenos(0); + /* Before tmp must be -1 */ tmp=0; + + tmp=funcmais(0); + /* Before tmp must be 1 */ tmp=0; + + tmp=funcmenos(-1); + /* Before tmp must be -2 */ tmp=0; + + tmp=funcmais(-1); + /* Before tmp must be 0 */ tmp=0; + + tmp=funcmenos(1); + /* Before tmp must be 0 */ tmp=0; + + tmp=funcmais(1); + /* Before tmp must be 2 */ tmp=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif + +int funcmenos(int input) { + return(input-1); +} + +int funcmais(int input) { + return(input+1); +} + diff --git a/pdl/riscv/tests/acstone-programs/131.call/Makefile b/pdl/riscv/tests/acstone-programs/131.call/Makefile new file mode 100644 index 0000000..704cbad --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/131.call/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 131.call +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/132.call/132.call.c b/pdl/riscv/tests/acstone-programs/132.call/132.call.c new file mode 100644 index 0000000..d1afe4f --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/132.call/132.call.c @@ -0,0 +1,141 @@ +/** + * @file 132.call.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses indirect calls functions. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* Declarations */ +signed char funcA(signed char input); +signed char funcB(signed char input); +signed char funcC(signed char input); +signed char funcD(signed char input); +signed char funcE(signed char input); +signed char funcF(signed char input); +signed char funcG(signed char input); +signed char funcH(signed char input); + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed char tmp=0; + tmp=funcA(-1); + /* Before tmp must be -1 */ tmp=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif + +unsigned long long int count=0; + +signed char funcA(signed char input) { + signed int a=-2; + funcB(input); + count++; + a++; + /* Before a must be -1 */ return input; +} + + + +signed char funcB(signed char input) { + unsigned int b=0; + funcC(input); + count++; + b++; + /* Before b must be 1 */ return input; +} + + + +signed char funcC(signed char input) { + signed short int c=-1; + funcD(input); + count++; + c++; + /* Before c must be 0 */ return input; +} + + + +signed char funcD(signed char input) { + unsigned short int d=9; + funcE(input); + count++; + d++; + /* Before d must be 10 */ return input; +} + + + +signed char funcE(signed char input) { + signed int e=-1; + funcF(input); + count++; + e++; + /* Before e must be 0 */ return input; +} + + + +signed char funcF(signed char input) { + unsigned int f=14; + funcG(input); + count++; + f++; + /* Before f must be 15 */ return input; +} + + + +signed char funcG(signed char input) { + signed long long int g=-2; + funcH(input); + count++; + g++; + /* Before g must be -1 */ return input; +} + + + +signed char funcH(signed char input) { + unsigned long long int h=1; + count++; + h++; + + /* Before h must be 2 */ return input; +} + diff --git a/pdl/riscv/tests/acstone-programs/132.call/Makefile b/pdl/riscv/tests/acstone-programs/132.call/Makefile new file mode 100644 index 0000000..e6606ec --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/132.call/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 132.call +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/133.call/133.call.c b/pdl/riscv/tests/acstone-programs/133.call/133.call.c new file mode 100644 index 0000000..4674cb4 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/133.call/133.call.c @@ -0,0 +1,75 @@ +/** + * @file 133.call.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses recursive fatorial. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* Declarations */ +unsigned long long int ulifatorial(unsigned long long int n); +signed long long int slifatorial(signed long long int n); + + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned long long int ulin; + signed long long int slin; + + ulin=ulifatorial(25); + /* Before ulin must be 7034535277573963776 */ ulin=0; + slin=slifatorial(25); + /* Before slin must be 7034535277573963776 */ slin=0; + + return 0; + /* Return 0 only */ +} + + +unsigned long long int ulifatorial(unsigned long long int n) { + if(n > 1) + return(n*ulifatorial(n-1)); + else + return 1; +} + +signed long long int slifatorial(signed long long int n) { + if(n > 1) + return(n*slifatorial(n-1)); + else + return 1; +} + + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/133.call/Makefile b/pdl/riscv/tests/acstone-programs/133.call/Makefile new file mode 100644 index 0000000..85a4e38 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/133.call/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 133.call +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/134.call/134.call.c b/pdl/riscv/tests/acstone-programs/134.call/134.call.c new file mode 100644 index 0000000..7b943ca --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/134.call/134.call.c @@ -0,0 +1,76 @@ +/** + * @file 134.call.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:21 -0300 + * @brief It is a simple main function that uses recursive Fibonacci function. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* Declarations */ +unsigned long long int ulifibonacci(unsigned long long int n); +signed long long int slifibonacci(signed long long int n); + + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned long long int ulin; + signed long long int slin; + + ulin=ulifibonacci(13); + /* Before ulin must be */ ulin=0; + slin=slifibonacci(13); + /* Before ulin must be */ slin=0; + + return 0; + /* Return 0 only */ +} + +unsigned long long int ulifibonacci(unsigned long long int n) { + if(n < 3) + return 1; + else + return(ulifibonacci(n-1)+ + ulifibonacci(n-2)); +} + +signed long long int slifibonacci(signed long long int n) { + if(n < 3) + return 1; + else + return(slifibonacci(n-1)+ + slifibonacci(n-2)); +} + + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/134.call/Makefile b/pdl/riscv/tests/acstone-programs/134.call/Makefile new file mode 100644 index 0000000..ec8a269 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/134.call/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 134.call +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/141.array/141.array.c b/pdl/riscv/tests/acstone-programs/141.array/141.array.c new file mode 100644 index 0000000..8f7b2aa --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/141.array/141.array.c @@ -0,0 +1,162 @@ +/** + * @file 141.array.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses size three dot products. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + unsigned char uca[3]; + unsigned char ucb[3]; + unsigned char ucc; + + signed char sca[3]; + signed char scb[3]; + signed char scc; + + unsigned short int usia[3]; + unsigned short int usib[3]; + unsigned short int usic; + + signed short int ssia[3]; + signed short int ssib[3]; + signed short int ssic; + + unsigned int uia[3]; + unsigned int uib[3]; + unsigned int uic; + + signed int sia[3]; + signed int sib[3]; + signed int sic; + + unsigned long long int ulia[3]; + unsigned long long int ulib[3]; + unsigned long long int ulic; + + signed long long int slia[3]; + signed long long int slib[3]; + signed long long int slic; + + unsigned char count; + + for(count=1;count<=3;count++) { + uca[count-1]=count; + ucb[count-1]=count; + } + + for(count=1;count<=3;count++) { + usia[count-1]=count; + usib[count-1]=count; + } + + for(count=1;count<=3;count++) { + uia[count-1]=count; + uib[count-1]=count; + } + + for(count=1;count<=3;count++) { + ulia[count-1]=count; + ulib[count-1]=count; + } + + for(count=1;count<=3;count++) { + sca[count-1]=count; + scb[count-1]=count; + } + + for(count=1;count<=3;count++) { + ssia[count-1]=count; + ssib[count-1]=count; + } + + for(count=1;count<=3;count++) { + sia[count-1]=count; + sib[count-1]=count; + } + + for(count=1;count<=3;count++) { + slia[count-1]=count; + slib[count-1]=count; + } + + + ucc=0; + for(count=0;count<3;count++) + ucc=ucc+(uca[count]*ucb[count]); + /* Before ucc must be 14 */ ucc=0; + + scc=0; + for(count=0;count<3;count++) + scc=scc+(sca[count]*scb[count]); + /* Before scc must be 14 */ scc=0; + + usic=0; + for(count=0;count<3;count++) + usic=usic+(usia[count]*usib[count]); + /* Before usic must be 14 */ usic=0; + + ssic=0; + for(count=0;count<3;count++) + ssic=ssic+(ssia[count]*ssib[count]); + /* Before ssic must be 14 */ ssic=0; + + uic=0; + for(count=0;count<3;count++) + uic=uic+(uia[count]*uib[count]); + /* Before uic must be 14 */ uic=0; + + sic=0; + for(count=0;count<3;count++) + sic=sic+(sia[count]*sib[count]); + /* Before sic must be 14 */ sic=0; + + ulic=0; + for(count=0;count<3;count++) + ulic=ulic+(ulia[count]*ulib[count]); + /* Before ulic must be 14 */ ulic=0; + + slic=0; + for(count=0;count<3;count++) + slic=slic+(slia[count]*slib[count]); + /* Before slic must be 14 */ slic=0; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/141.array/Makefile b/pdl/riscv/tests/acstone-programs/141.array/Makefile new file mode 100644 index 0000000..a9405e1 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/141.array/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 141.array +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/142.array/142.array.c b/pdl/riscv/tests/acstone-programs/142.array/142.array.c new file mode 100644 index 0000000..7c94c46 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/142.array/142.array.c @@ -0,0 +1,82 @@ +/** + * @file 142.array.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses a kind of square matrix multiplication. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +int main() { + + signed long long int a[10][10]; + signed long long int b[10][10]; + signed long long int c[10][10]; + + unsigned char i,j,k; + + unsigned char error=0; + + for(i=0 ; i<10 ; i++) /* A = I */ + for(j=0 ; j<10 ; j++) { + if(i==j) + a[i][j]=1; + else + a[i][j]=0; + } + + for(i=0 ; i<10 ; i++) /* B = X */ + for(j=0 ; j<10 ; j++) + b[i][j]=((signed long long int)i+(signed long long int)j); + + for(i=0 ; i<10 ; i++) /* C = 0 */ + for(j=0 ; j<10 ; j++) + c[i][j]=0; + + for(i=0 ; i<10 ; i++) /* C = A . B */ + for(j=0 ; j<10 ; j++) + for(k=0 ; k<10 ; k++) + c[i][j]=c[i][j]+(a[i][k]*b[k][j]); + + for(i=0 ; i<10 ; i++) /* B = C ? */ + for(j=0 ; j<10 ; j++) + if(b[i][j] != c[i][j]) + error=1; + + /* Before error must be 0 */ error=0; + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif diff --git a/pdl/riscv/tests/acstone-programs/142.array/Makefile b/pdl/riscv/tests/acstone-programs/142.array/Makefile new file mode 100644 index 0000000..e2ed077 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/142.array/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := 142.array +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET).c + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET).c -o $(TARGET).run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) $(TARGET).run > $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/143.array/143.array.c b/pdl/riscv/tests/acstone-programs/143.array/143.array.c new file mode 100644 index 0000000..f71295a --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/143.array/143.array.c @@ -0,0 +1,151 @@ +/** + * @file 143.array.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed and unsigned char Bubble Sort. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +void scBubbleSort(signed char scarray[],int size); +void ucBubbleSort(unsigned char ucarray[],int size); + +int main() { + + signed char scinput[21]; + unsigned char ucinput[21]; + + signed char i; + unsigned char j; + + int count,errorsc,erroruc; + + scinput[0]=0xDF; + scinput[1]=0x44; + scinput[2]=0x12; + scinput[3]=0x45; + scinput[4]=0x80; + scinput[5]=0xDD; + scinput[6]=0x43; + scinput[7]=0x67; + scinput[8]=0x00; + scinput[9]=0x23; + scinput[10]=0x01; + scinput[11]=0xF7; + scinput[12]=0x45; + scinput[13]=0x86; + scinput[14]=0x96; + scinput[15]=0x52; + scinput[16]=0xFF; + scinput[17]=0x56; + scinput[18]=0x23; + scinput[19]=0x10; + scinput[20]=0x05; + + ucinput[0]=0xDF; + ucinput[1]=0x44; + ucinput[2]=0x12; + ucinput[3]=0x45; + ucinput[4]=0x80; + ucinput[5]=0xDD; + ucinput[6]=0x43; + ucinput[7]=0x67; + ucinput[8]=0x00; + ucinput[9]=0x23; + ucinput[10]=0x01; + ucinput[11]=0xF7; + ucinput[12]=0x45; + ucinput[13]=0x86; + ucinput[14]=0x96; + ucinput[15]=0x52; + ucinput[16]=0xFF; + ucinput[17]=0x56; + ucinput[18]=0x23; + ucinput[19]=0x10; + ucinput[20]=0x05; + + + /* signed sort */ + scBubbleSort(scinput,21); + /* unsigned sort */ + ucBubbleSort(ucinput,21); + + + /* Check */ + errorsc=0; + for(count=0 ; count < 20 ; count++) + if(scinput[count] > scinput[count+1]) + errorsc=1; + + /* Check */ + erroruc=0; + for(count=0 ; count < 20 ; count++) + if(ucinput[count] > ucinput[count+1]) + erroruc=1; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif + +/* signed char bubble sort */ +void scBubbleSort(signed char scarray[],int size) { + int i,j; + signed char temp; + for(i=(size-1);i>=0;i--) { + for(j=0;j=0;i--) { + for(j=0;j $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/144.array/144.array.c b/pdl/riscv/tests/acstone-programs/144.array/144.array.c new file mode 100644 index 0000000..852276c --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/144.array/144.array.c @@ -0,0 +1,151 @@ +/** + * @file 144.array.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed and unsigned short int Bubble Sort. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +void ssiBubbleSort(signed short int ssiarray[],int size); +void usiBubbleSort(unsigned short int usiarray[],int size); + +int main() { + + signed short int ssiinput[21]; + unsigned short int usiinput[21]; + + signed char i; + unsigned char j; + + int count,errorssi,errorusi; + + ssiinput[0]=0xF5DF; + ssiinput[1]=0x2444; + ssiinput[2]=0x5612; + ssiinput[3]=0xF645; + ssiinput[4]=0xFF80; + ssiinput[5]=0x12DD; + ssiinput[6]=0x4343; + ssiinput[7]=0xF167; + ssiinput[8]=0x0000; + ssiinput[9]=0x0123; + ssiinput[10]=0x3301; + ssiinput[11]=0x12F7; + ssiinput[12]=0x8745; + ssiinput[13]=0x8286; + ssiinput[14]=0x1296; + ssiinput[15]=0x3452; + ssiinput[16]=0xE3FF; + ssiinput[17]=0x2456; + ssiinput[18]=0x6723; + ssiinput[19]=0x7510; + ssiinput[20]=0x0005; + + usiinput[0]=0xF5DF; + usiinput[1]=0x2444; + usiinput[2]=0x5612; + usiinput[3]=0xF645; + usiinput[4]=0xFF80; + usiinput[5]=0x12DD; + usiinput[6]=0x4343; + usiinput[7]=0xF167; + usiinput[8]=0x0000; + usiinput[9]=0x0123; + usiinput[10]=0x3301; + usiinput[11]=0x12F7; + usiinput[12]=0x8745; + usiinput[13]=0x8286; + usiinput[14]=0x1296; + usiinput[15]=0x3452; + usiinput[16]=0xE3FF; + usiinput[17]=0x2456; + usiinput[18]=0x6723; + usiinput[19]=0x7510; + usiinput[20]=0x0005; + + + /* signed sort */ + ssiBubbleSort(ssiinput,21); + /* unsigned sort */ + usiBubbleSort(usiinput,21); + + + /* Check */ + errorssi=0; + for(count=0 ; count < 20 ; count++) + if(ssiinput[count] > ssiinput[count+1]) + errorusi=1; + + /* Check */ + errorusi=0; + for(count=0 ; count < 20 ; count++) + if(usiinput[count] > usiinput[count+1]) + errorusi=1; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif + +/* signed short int bubble sort */ +void ssiBubbleSort(signed short int ssiarray[],int size) { + int i,j; + signed short int temp; + for(i=(size-1);i>=0;i--) { + for(j=0;j=0;i--) { + for(j=0;j $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/145.array/145.array.c b/pdl/riscv/tests/acstone-programs/145.array/145.array.c new file mode 100644 index 0000000..f7cc849 --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/145.array/145.array.c @@ -0,0 +1,151 @@ +/** + * @file 145.array.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed and unsigned int Bubble Sort. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +void siBubbleSort(signed int siarray[],int size); +void uiBubbleSort(unsigned int uiarray[],int size); + +int main() { + + signed int siinput[21]; + unsigned int uiinput[21]; + + signed char i; + unsigned char j; + + int count,errorsi,errorui; + + siinput[0]=0xF234F5DF; + siinput[1]=0x23512444; + siinput[2]=0x34565612; + siinput[3]=0x1234F645; + siinput[4]=0x8901FF80; + siinput[5]=0x789012DD; + siinput[6]=0x23454343; + siinput[7]=0x8965F167; + siinput[8]=0x00000000; + siinput[9]=0x45670123; + siinput[10]=0x23453301; + siinput[11]=0x543212F7; + siinput[12]=0x76548745; + siinput[13]=0x23458286; + siinput[14]=0x87651296; + siinput[15]=0xD3453452; + siinput[16]=0xC432E3FF; + siinput[17]=0x22222456; + siinput[18]=0x12346723; + siinput[19]=0xD4567510; + siinput[20]=0x00000005; + + uiinput[0]=0xF234F5DF; + uiinput[1]=0x23512444; + uiinput[2]=0x34565612; + uiinput[3]=0x1234F645; + uiinput[4]=0x8901FF80; + uiinput[5]=0x789012DD; + uiinput[6]=0x23454343; + uiinput[7]=0x8965F167; + uiinput[8]=0x00000000; + uiinput[9]=0x45670123; + uiinput[10]=0x23453301; + uiinput[11]=0x543212F7; + uiinput[12]=0x76548745; + uiinput[13]=0x23458286; + uiinput[14]=0x87651296; + uiinput[15]=0xD3453452; + uiinput[16]=0xC432E3FF; + uiinput[17]=0x22222456; + uiinput[18]=0x12346723; + uiinput[19]=0xD4567510; + uiinput[20]=0x00000005; + + + /* signed sort */ + siBubbleSort(siinput,21); + /* unsigned sort */ + uiBubbleSort(uiinput,21); + + + /* Check */ + errorsi=0; + for(count=0 ; count < 20 ; count++) + if(siinput[count] > siinput[count+1]) + errorui=1; + + /* Check */ + errorui=0; + for(count=0 ; count < 20 ; count++) + if(uiinput[count] > uiinput[count+1]) + errorui=1; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif + +/* signed int bubble sort */ +void siBubbleSort(signed int siarray[],int size) { + int i,j; + signed int temp; + for(i=(size-1);i>=0;i--) { + for(j=0;j=0;i--) { + for(j=0;j $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/acstone-programs/146.array/146.array.c b/pdl/riscv/tests/acstone-programs/146.array/146.array.c new file mode 100644 index 0000000..8b724cc --- /dev/null +++ b/pdl/riscv/tests/acstone-programs/146.array/146.array.c @@ -0,0 +1,153 @@ +/** + * @file 146.array.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:22 -0300 + * @brief It is a simple main function that uses signed and unsigned long long int Bubble Sort. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* It is a simple main function that uses signed and unsigned long long int Bubble Sort.*/ + +/* The file begin.h is included if compiler flag -DBEGINCODE is used */ +#ifdef BEGINCODE +#include "begin.h" +#endif + +void sliBubbleSort(signed long long int siarray[],int size); +void uliBubbleSort(unsigned long long int uiarray[],int size); + +int main() { + + signed long long int sliinput[21]; + unsigned long long int uliinput[21]; + + signed char i; + unsigned char j; + + int count,errorsli,erroruli; + + sliinput[0]=0xF5032345F234F5DFLL; + sliinput[1]=0xD3A4F62123512444LL; + sliinput[2]=0x9876223434565612LL; + sliinput[3]=0x000000001234F645LL; + sliinput[4]=0x234567898901FF80LL; + sliinput[5]=0x78905432789012DDLL; + sliinput[6]=0x1234567823454343LL; + sliinput[7]=0x890765238965F167LL; + sliinput[8]=0x0000000000000000LL; + sliinput[9]=0x4523457845670123LL; + sliinput[10]=0x0987123423453301LL; + sliinput[11]=0x56780987543212F7LL; + sliinput[12]=0x8654123476548745LL; + sliinput[13]=0x45E3213423458286LL; + sliinput[14]=0xF234566887651296LL; + sliinput[15]=0xD345674902953452LL; + sliinput[16]=0x4523457845670123LL; + sliinput[17]=0x2345678922222456LL; + sliinput[18]=0x8889098612346723LL; + sliinput[19]=0x12345433D4567510LL; + sliinput[20]=0x0000000000000005LL; + + uliinput[0]=0xF5032345F234F5DFULL; + uliinput[1]=0xD3A4F62123512444ULL; + uliinput[2]=0x9876223434565612ULL; + uliinput[3]=0x000000001234F645ULL; + uliinput[4]=0x234567898901FF80ULL; + uliinput[5]=0x78905432789012DDULL; + uliinput[6]=0x1234567823454343ULL; + uliinput[7]=0x890765238965F167ULL; + uliinput[8]=0x0000000000000000ULL; + uliinput[9]=0x4523457845670123ULL; + uliinput[10]=0x0987123423453301ULL; + uliinput[11]=0x56780987543212F7ULL; + uliinput[12]=0x8654123476548745ULL; + uliinput[13]=0x45E3213423458286ULL; + uliinput[14]=0xF234566887651296ULL; + uliinput[15]=0xD345674902953452ULL; + uliinput[16]=0x4523457845670123ULL; + uliinput[17]=0x2345678922222456ULL; + uliinput[18]=0x8889098612346723ULL; + uliinput[19]=0x12345433D4567510ULL; + uliinput[20]=0x0000000000000005ULL; + + + /* signed sort */ + sliBubbleSort(sliinput,21); + /* unsigned sort */ + uliBubbleSort(uliinput,21); + + + /* Check */ + errorsli=0; + for(count=0 ; count < 20 ; count++) + if(sliinput[count] > sliinput[count+1]) + erroruli=1; + + /* Check */ + erroruli=0; + for(count=0 ; count < 20 ; count++) + if(uliinput[count] > uliinput[count+1]) + erroruli=1; + + + return 0; + /* Return 0 only */ +} + +/* The file end.h is included if compiler flag -DENDCODE is used */ +#ifdef ENDCODE +#include "end.h" +#endif + +/* signed long long int bubble sort */ +void sliBubbleSort(signed long long int sliarray[],int size) { + int i,j; + signed long long int temp; + for(i=(size-1);i>=0;i--) { + for(j=0;j=0;i--) { + for(j=0;j $(TARGET).out + +clean: + rm $(TARGET).run crt.o $(TARGET).out diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_large/Makefile b/pdl/riscv/tests/automotive-IMA/basicmath_large/Makefile new file mode 100644 index 0000000..693e507 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_large/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := basicmath_large.c rad2deg.c cubic.c isqrt.c +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET) + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET) -o basicmath_large.run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) basicmath_large.run > basicmath_large.out + +clean: + rm basicmath_large.run crt.o basicmath_large.out diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_large/basicmath_large.c b/pdl/riscv/tests/automotive-IMA/basicmath_large/basicmath_large.c new file mode 100755 index 0000000..8320e5d --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_large/basicmath_large.c @@ -0,0 +1,123 @@ +#include "snipmath.h" +#include + +/* The printf's may be removed to isolate just the math calculations */ + +int main(void) +{ + double a1 = 1.0, b1 = -10.5, c1 = 32.0, d1 = -30.0; + double x[3]; + double X; + int solutions; + int i; + unsigned long l = 0x3fed0169L; + struct int_sqrt q; + long n = 0; + + /* solve soem cubic functions */ + printf("********* CUBIC FUNCTIONS ***********\n"); + /* should get 3 solutions: 2, 6 & 2.5 */ + SolveCubic(a1, b1, c1, d1, &solutions, x); + printf("Solutions:"); + for(i=0;i0;b1-=.25) { + for(c1=5;c1<15;c1+=0.61) { + for(d1=-1;d1>-5;d1-=.451) { + SolveCubic(a1, b1, c1, d1, &solutions, x); + printf("Solutions:"); + for(i=0;i +#include +#include "snipmath.h" + +void SolveCubic(double a, + double b, + double c, + double d, + int *solutions, + double *x) +{ + long double a1 = b/a, a2 = c/a, a3 = d/a; + long double Q = (a1*a1 - 3.0*a2)/9.0; + long double R = (2.0*a1*a1*a1 - 9.0*a1*a2 + 27.0*a3)/54.0; + double R2_Q3 = R*R - Q*Q*Q; + + double theta; + + if (R2_Q3 <= 0) + { + *solutions = 3; + theta = acos(R/sqrt(Q*Q*Q)); + x[0] = -2.0*sqrt(Q)*cos(theta/3.0) - a1/3.0; + x[1] = -2.0*sqrt(Q)*cos((theta+2.0*PI)/3.0) - a1/3.0; + x[2] = -2.0*sqrt(Q)*cos((theta+4.0*PI)/3.0) - a1/3.0; + } + else + { + *solutions = 1; + x[0] = pow(sqrt(R2_Q3)+fabs(R), 1/3.0); + x[0] += Q/x[0]; + x[0] *= (R < 0.0) ? 1 : -1; + x[0] -= a1/3.0; + } +} + +#ifdef TEST + +int main(void) +{ + double a1 = 1.0, b1 = -10.5, c1 = 32.0, d1 = -30.0; + double a2 = 1.0, b2 = -4.5, c2 = 17.0, d2 = -30.0; + double x[3]; + int solutions; + + SolveCubic(a1, b1, c1, d1, &solutions, x); + + /* should get 3 solutions: 2, 6 & 2.5 */ + + SolveCubic(a2, b2, c2, d2, &solutions, x); + + /* should get 1 solution: 2.5 */ + + return 0; +} + +#endif /* TEST */ diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_large/isqrt.c b/pdl/riscv/tests/automotive-IMA/basicmath_large/isqrt.c new file mode 100755 index 0000000..3003b48 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_large/isqrt.c @@ -0,0 +1,89 @@ +/* +++Date last modified: 05-Jul-1997 */ + +#include +#include "snipmath.h" + +#define BITSPERLONG 32 + +#define TOP2BITS(x) ((x & (3L << (BITSPERLONG-2))) >> (BITSPERLONG-2)) + + +/* usqrt: + ENTRY x: unsigned long + EXIT returns floor(sqrt(x) * pow(2, BITSPERLONG/2)) + + Since the square root never uses more than half the bits + of the input, we use the other half of the bits to contain + extra bits of precision after the binary point. + + EXAMPLE + suppose BITSPERLONG = 32 + then usqrt(144) = 786432 = 12 * 65536 + usqrt(32) = 370727 = 5.66 * 65536 + + NOTES + (1) change BITSPERLONG to BITSPERLONG/2 if you do not want + the answer scaled. Indeed, if you want n bits of + precision after the binary point, use BITSPERLONG/2+n. + The code assumes that BITSPERLONG is even. + (2) This is really better off being written in assembly. + The line marked below is really a "arithmetic shift left" + on the double-long value with r in the upper half + and x in the lower half. This operation is typically + expressible in only one or two assembly instructions. + (3) Unrolling this loop is probably not a bad idea. + + ALGORITHM + The calculations are the base-two analogue of the square + root algorithm we all learned in grammar school. Since we're + in base 2, there is only one nontrivial trial multiplier. + + Notice that absolutely no multiplications or divisions are performed. + This means it'll be fast on a wide range of processors. +*/ + +void usqrt(unsigned long x, struct int_sqrt *q) +{ + unsigned long a = 0L; /* accumulator */ + unsigned long r = 0L; /* remainder */ + unsigned long e = 0L; /* trial product */ + + int i; + + for (i = 0; i < BITSPERLONG; i++) /* NOTE 1 */ + { + r = (r << 2) + TOP2BITS(x); x <<= 2; /* NOTE 2 */ + a <<= 1; + e = (a << 1) + 1; + if (r >= e) + { + r -= e; + a++; + } + } + memcpy(q, &a, sizeof(long)); +} + +#ifdef TEST + +#include +#include + +main(void) +{ + int i; + unsigned long l = 0x3fed0169L; + struct int_sqrt q; + + for (i = 0; i < 101; ++i) + { + usqrt(i, &q); + printf("sqrt(%3d) = %2d, remainder = %2d\n", + i, q.sqrt, q.frac); + } + usqrt(l, &q); + printf("\nsqrt(%lX) = %X, remainder = %X\n", l, q.sqrt, q.frac); + return 0; +} + +#endif /* TEST */ diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_large/pi.h b/pdl/riscv/tests/automotive-IMA/basicmath_large/pi.h new file mode 100755 index 0000000..d379b48 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_large/pi.h @@ -0,0 +1,13 @@ +/* +++Date last modified: 05-Jul-1997 */ + +#ifndef PI__H +#define PI__H + +#ifndef PI + #define PI (4*atan(1)) +#endif + +#define deg2rad(d) ((d)*PI/180) +#define rad2deg(r) ((r)*180/PI) + +#endif /* PI__H */ diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_large/rad2deg.c b/pdl/riscv/tests/automotive-IMA/basicmath_large/rad2deg.c new file mode 100755 index 0000000..5a20184 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_large/rad2deg.c @@ -0,0 +1,39 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** RAD2DEG.C - Functions to convert between radians and degrees +*/ + +#include +#include "snipmath.h" + +#undef rad2deg /* These are macros defined in PI.H */ +#undef deg2rad + +double rad2deg(double rad) +{ + return (180.0 * rad / (PI)); +} + +double deg2rad(double deg) +{ + return (PI * deg / 180.0); +} + +#ifdef TEST + +#include + +main() +{ + double X; + + for (X = 0.0; X <= 360.0; X += 45.0) + printf("%3.0f degrees = %.12f radians\n", X, deg2rad(X)); + puts(""); + for (X = 0.0; X <= (2 * PI + 1e-6); X += (PI / 6)) + printf("%.12f radians = %3.0f degrees\n", X, rad2deg(X)); + return 0; +} + +#endif /* TEST */ diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_large/round.h b/pdl/riscv/tests/automotive-IMA/basicmath_large/round.h new file mode 100755 index 0000000..9d31c60 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_large/round.h @@ -0,0 +1,55 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** rounding macros by Dave Knapp, Thad Smith, Jon Strayer, & Bob Stout +*/ + +#ifndef ROUND__H +#define ROUND__H + +#include + +#if defined(__cplusplus) && __cplusplus + +/* +** Safe C++ inline versions +*/ + +/* round to integer */ + +inline int iround(double x) +{ + return (int)floor(x + 0.5); +} + +/* round number n to d decimal points */ + +inline double fround(double n, unsigned d) +{ + return floor(n * pow(10., d) + .5) / pow(10., d); +} + +#else + +/* +** NOTE: These C macro versions are unsafe since arguments are referenced +** more than once. +** +** Avoid using these with expression arguments to be safe. +*/ + +/* +** round to integer +*/ + +#define iround(x) floor((x) + 0.5) + +/* +** round number n to d decimal points +*/ + +#define fround(n,d) (floor((n)*pow(10.,(d))+.5)/pow(10.,(d))) + +#endif + +#endif /* ROUND__H */ diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_large/snipmath.h b/pdl/riscv/tests/automotive-IMA/basicmath_large/snipmath.h new file mode 100755 index 0000000..ad046db --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_large/snipmath.h @@ -0,0 +1,75 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** SNIPMATH.H - Header file for SNIPPETS math functions and macros +*/ + +#ifndef SNIPMATH__H +#define SNIPMATH__H + +#include +#include "sniptype.h" +#include "round.h" + +/* +** Callable library functions begin here +*/ + +void SetBCDLen(int n); /* Bcdl.C */ +long BCDtoLong(char *BCDNum); /* Bcdl.C */ +void LongtoBCD(long num, char BCDNum[]); /* Bcdl.C */ +double bcd_to_double(void *buf, size_t len, /* Bcdd.C */ + int digits); +int double_to_bcd(double arg, char *buf, /* Bcdd.C */ + size_t length, size_t digits ); +DWORD ncomb1 (int n, int m); /* Combin.C */ +DWORD ncomb2 (int n, int m); /* Combin.C */ +void SolveCubic(double a, double b, double c, /* Cubic.C */ + double d, int *solutions, + double *x); +DWORD dbl2ulong(double t); /* Dbl2Long.C */ +long dbl2long(double t); /* Dbl2Long.C */ +double dround(double x); /* Dblround.C */ + +/* Use #defines for Permutations and Combinations -- Factoryl.C */ + +#define log10P(n,r) (log10factorial(n)-log10factorial((n)-(r))) +#define log10C(n,r) (log10P((n),(r))-log10factorial(r)) + +double log10factorial(double N); /* Factoryl.C */ + +double fibo(unsigned short term); /* Fibo.C */ +double frandom(int n); /* Frand.C */ +double ipow(double x, int n); /* Ipow.C */ +int ispow2(int x); /* Ispow2.C */ +long double ldfloor(long double a); /* Ldfloor.C */ +int initlogscale(long dmax, long rmax); /* Logscale.C */ +long logscale(long d); /* Logscale.C */ + +float MSBINToIEEE(float f); /* Msb2Ieee.C */ +float IEEEToMSBIN(float f); /* Msb2Ieee.C */ +int perm_index (char pit[], int size); /* Perm_Idx.C */ +int round_div(int n, int d); /* Rnd_Div.C */ +long round_ldiv(long n, long d); /* Rnd_Div.C */ +double rad2deg(double rad); /* Rad2Deg.C */ +double deg2rad(double deg); /* Rad2Deg.C */ + +#include "pi.h" +#ifndef PHI + #define PHI ((1.0+sqrt(5.0))/2.0) /* the golden number */ + #define INV_PHI (1.0/PHI) /* the golden ratio */ +#endif + +/* +** File: ISQRT.C +*/ + +struct int_sqrt { + unsigned sqrt, + frac; +}; + +void usqrt(unsigned long x, struct int_sqrt *q); + + +#endif /* SNIPMATH__H */ diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_large/sniptype.h b/pdl/riscv/tests/automotive-IMA/basicmath_large/sniptype.h new file mode 100755 index 0000000..899ee5b --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_large/sniptype.h @@ -0,0 +1,37 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** SNIPTYPE.H - Include file for SNIPPETS data types and commonly used macros +*/ + +#ifndef SNIPTYPE__H +#define SNIPTYPE__H + +#include /* For free() */ +#include /* For NULL & strlen() */ + +typedef enum {Error_ = -1, Success_, False_ = 0, True_} Boolean_T; + +/*#if !defined(WIN32) && !defined(_WIN32) && !defined(__NT__) \ + && !defined(_WINDOWS) + #if !defined(OS2)*/ + typedef unsigned char BYTE; + typedef unsigned long DWORD; +/* #endif*/ + typedef unsigned short WORD; +/*#else + #define WIN32_LEAN_AND_MEAN + #define NOGDI + #define NOSERVICE + #undef INC_OLE1 + #undef INC_OLE2 + #include + #define HUGE + #endif*/ + +#define NUL '\0' +#define LAST_CHAR(s) (((char *)s)[strlen(s) - 1]) +#define TOBOOL(x) (!(!(x))) +#define FREE(p) (free(p),(p)=NULL) + +#endif /* SNIPTYPE__H */ diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_small/Makefile b/pdl/riscv/tests/automotive-IMA/basicmath_small/Makefile new file mode 100644 index 0000000..66a0702 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_small/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := basicmath_small.c rad2deg.c cubic.c isqrt.c +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET) + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET) -o basicmath_small.run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) basicmath_small.run > basicmath_small.out + +clean: + rm basicmath_small.run crt.o basicmath_small.out diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_small/basicmath_small.c b/pdl/riscv/tests/automotive-IMA/basicmath_small/basicmath_small.c new file mode 100755 index 0000000..049fea2 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_small/basicmath_small.c @@ -0,0 +1,84 @@ +#include "snipmath.h" +#include + +/* The printf's may be removed to isolate just the math calculations */ + +int main(void) +{ + double a1 = 1.0, b1 = -10.5, c1 = 32.0, d1 = -30.0; + double a2 = 1.0, b2 = -4.5, c2 = 17.0, d2 = -30.0; + double a3 = 1.0, b3 = -3.5, c3 = 22.0, d3 = -31.0; + double a4 = 1.0, b4 = -13.7, c4 = 1.0, d4 = -35.0; + double x[3]; + double X; + int solutions; + int i; + unsigned long l = 0x3fed0169L; + struct int_sqrt q; + long n = 0; + + /* solve soem cubic functions */ + printf("********* CUBIC FUNCTIONS ***********\n"); + /* should get 3 solutions: 2, 6 & 2.5 */ + SolveCubic(a1, b1, c1, d1, &solutions, x); + printf("Solutions:"); + for(i=0;i0;b1--) { + for(c1=5;c1<15;c1+=0.5) { + for(d1=-1;d1>-11;d1--) { + SolveCubic(a1, b1, c1, d1, &solutions, x); + printf("Solutions:"); + for(i=0;i +#include +#include "snipmath.h" + +void SolveCubic(double a, + double b, + double c, + double d, + int *solutions, + double *x) +{ + long double a1 = b/a, a2 = c/a, a3 = d/a; + long double Q = (a1*a1 - 3.0*a2)/9.0; + long double R = (2.0*a1*a1*a1 - 9.0*a1*a2 + 27.0*a3)/54.0; + double R2_Q3 = R*R - Q*Q*Q; + + double theta; + + if (R2_Q3 <= 0) + { + *solutions = 3; + theta = acos(R/sqrt(Q*Q*Q)); + x[0] = -2.0*sqrt(Q)*cos(theta/3.0) - a1/3.0; + x[1] = -2.0*sqrt(Q)*cos((theta+2.0*PI)/3.0) - a1/3.0; + x[2] = -2.0*sqrt(Q)*cos((theta+4.0*PI)/3.0) - a1/3.0; + } + else + { + *solutions = 1; + x[0] = pow(sqrt(R2_Q3)+fabs(R), 1/3.0); + x[0] += Q/x[0]; + x[0] *= (R < 0.0) ? 1 : -1; + x[0] -= a1/3.0; + } +} + +#ifdef TEST + +int main(void) +{ + double a1 = 1.0, b1 = -10.5, c1 = 32.0, d1 = -30.0; + double a2 = 1.0, b2 = -4.5, c2 = 17.0, d2 = -30.0; + double x[3]; + int solutions; + + SolveCubic(a1, b1, c1, d1, &solutions, x); + + /* should get 3 solutions: 2, 6 & 2.5 */ + + SolveCubic(a2, b2, c2, d2, &solutions, x); + + /* should get 1 solution: 2.5 */ + + return 0; +} + +#endif /* TEST */ diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_small/isqrt.c b/pdl/riscv/tests/automotive-IMA/basicmath_small/isqrt.c new file mode 100755 index 0000000..3003b48 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_small/isqrt.c @@ -0,0 +1,89 @@ +/* +++Date last modified: 05-Jul-1997 */ + +#include +#include "snipmath.h" + +#define BITSPERLONG 32 + +#define TOP2BITS(x) ((x & (3L << (BITSPERLONG-2))) >> (BITSPERLONG-2)) + + +/* usqrt: + ENTRY x: unsigned long + EXIT returns floor(sqrt(x) * pow(2, BITSPERLONG/2)) + + Since the square root never uses more than half the bits + of the input, we use the other half of the bits to contain + extra bits of precision after the binary point. + + EXAMPLE + suppose BITSPERLONG = 32 + then usqrt(144) = 786432 = 12 * 65536 + usqrt(32) = 370727 = 5.66 * 65536 + + NOTES + (1) change BITSPERLONG to BITSPERLONG/2 if you do not want + the answer scaled. Indeed, if you want n bits of + precision after the binary point, use BITSPERLONG/2+n. + The code assumes that BITSPERLONG is even. + (2) This is really better off being written in assembly. + The line marked below is really a "arithmetic shift left" + on the double-long value with r in the upper half + and x in the lower half. This operation is typically + expressible in only one or two assembly instructions. + (3) Unrolling this loop is probably not a bad idea. + + ALGORITHM + The calculations are the base-two analogue of the square + root algorithm we all learned in grammar school. Since we're + in base 2, there is only one nontrivial trial multiplier. + + Notice that absolutely no multiplications or divisions are performed. + This means it'll be fast on a wide range of processors. +*/ + +void usqrt(unsigned long x, struct int_sqrt *q) +{ + unsigned long a = 0L; /* accumulator */ + unsigned long r = 0L; /* remainder */ + unsigned long e = 0L; /* trial product */ + + int i; + + for (i = 0; i < BITSPERLONG; i++) /* NOTE 1 */ + { + r = (r << 2) + TOP2BITS(x); x <<= 2; /* NOTE 2 */ + a <<= 1; + e = (a << 1) + 1; + if (r >= e) + { + r -= e; + a++; + } + } + memcpy(q, &a, sizeof(long)); +} + +#ifdef TEST + +#include +#include + +main(void) +{ + int i; + unsigned long l = 0x3fed0169L; + struct int_sqrt q; + + for (i = 0; i < 101; ++i) + { + usqrt(i, &q); + printf("sqrt(%3d) = %2d, remainder = %2d\n", + i, q.sqrt, q.frac); + } + usqrt(l, &q); + printf("\nsqrt(%lX) = %X, remainder = %X\n", l, q.sqrt, q.frac); + return 0; +} + +#endif /* TEST */ diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_small/pi.h b/pdl/riscv/tests/automotive-IMA/basicmath_small/pi.h new file mode 100755 index 0000000..d379b48 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_small/pi.h @@ -0,0 +1,13 @@ +/* +++Date last modified: 05-Jul-1997 */ + +#ifndef PI__H +#define PI__H + +#ifndef PI + #define PI (4*atan(1)) +#endif + +#define deg2rad(d) ((d)*PI/180) +#define rad2deg(r) ((r)*180/PI) + +#endif /* PI__H */ diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_small/rad2deg.c b/pdl/riscv/tests/automotive-IMA/basicmath_small/rad2deg.c new file mode 100755 index 0000000..5a20184 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_small/rad2deg.c @@ -0,0 +1,39 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** RAD2DEG.C - Functions to convert between radians and degrees +*/ + +#include +#include "snipmath.h" + +#undef rad2deg /* These are macros defined in PI.H */ +#undef deg2rad + +double rad2deg(double rad) +{ + return (180.0 * rad / (PI)); +} + +double deg2rad(double deg) +{ + return (PI * deg / 180.0); +} + +#ifdef TEST + +#include + +main() +{ + double X; + + for (X = 0.0; X <= 360.0; X += 45.0) + printf("%3.0f degrees = %.12f radians\n", X, deg2rad(X)); + puts(""); + for (X = 0.0; X <= (2 * PI + 1e-6); X += (PI / 6)) + printf("%.12f radians = %3.0f degrees\n", X, rad2deg(X)); + return 0; +} + +#endif /* TEST */ diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_small/round.h b/pdl/riscv/tests/automotive-IMA/basicmath_small/round.h new file mode 100755 index 0000000..9d31c60 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_small/round.h @@ -0,0 +1,55 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** rounding macros by Dave Knapp, Thad Smith, Jon Strayer, & Bob Stout +*/ + +#ifndef ROUND__H +#define ROUND__H + +#include + +#if defined(__cplusplus) && __cplusplus + +/* +** Safe C++ inline versions +*/ + +/* round to integer */ + +inline int iround(double x) +{ + return (int)floor(x + 0.5); +} + +/* round number n to d decimal points */ + +inline double fround(double n, unsigned d) +{ + return floor(n * pow(10., d) + .5) / pow(10., d); +} + +#else + +/* +** NOTE: These C macro versions are unsafe since arguments are referenced +** more than once. +** +** Avoid using these with expression arguments to be safe. +*/ + +/* +** round to integer +*/ + +#define iround(x) floor((x) + 0.5) + +/* +** round number n to d decimal points +*/ + +#define fround(n,d) (floor((n)*pow(10.,(d))+.5)/pow(10.,(d))) + +#endif + +#endif /* ROUND__H */ diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_small/snipmath.h b/pdl/riscv/tests/automotive-IMA/basicmath_small/snipmath.h new file mode 100755 index 0000000..ad046db --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_small/snipmath.h @@ -0,0 +1,75 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** SNIPMATH.H - Header file for SNIPPETS math functions and macros +*/ + +#ifndef SNIPMATH__H +#define SNIPMATH__H + +#include +#include "sniptype.h" +#include "round.h" + +/* +** Callable library functions begin here +*/ + +void SetBCDLen(int n); /* Bcdl.C */ +long BCDtoLong(char *BCDNum); /* Bcdl.C */ +void LongtoBCD(long num, char BCDNum[]); /* Bcdl.C */ +double bcd_to_double(void *buf, size_t len, /* Bcdd.C */ + int digits); +int double_to_bcd(double arg, char *buf, /* Bcdd.C */ + size_t length, size_t digits ); +DWORD ncomb1 (int n, int m); /* Combin.C */ +DWORD ncomb2 (int n, int m); /* Combin.C */ +void SolveCubic(double a, double b, double c, /* Cubic.C */ + double d, int *solutions, + double *x); +DWORD dbl2ulong(double t); /* Dbl2Long.C */ +long dbl2long(double t); /* Dbl2Long.C */ +double dround(double x); /* Dblround.C */ + +/* Use #defines for Permutations and Combinations -- Factoryl.C */ + +#define log10P(n,r) (log10factorial(n)-log10factorial((n)-(r))) +#define log10C(n,r) (log10P((n),(r))-log10factorial(r)) + +double log10factorial(double N); /* Factoryl.C */ + +double fibo(unsigned short term); /* Fibo.C */ +double frandom(int n); /* Frand.C */ +double ipow(double x, int n); /* Ipow.C */ +int ispow2(int x); /* Ispow2.C */ +long double ldfloor(long double a); /* Ldfloor.C */ +int initlogscale(long dmax, long rmax); /* Logscale.C */ +long logscale(long d); /* Logscale.C */ + +float MSBINToIEEE(float f); /* Msb2Ieee.C */ +float IEEEToMSBIN(float f); /* Msb2Ieee.C */ +int perm_index (char pit[], int size); /* Perm_Idx.C */ +int round_div(int n, int d); /* Rnd_Div.C */ +long round_ldiv(long n, long d); /* Rnd_Div.C */ +double rad2deg(double rad); /* Rad2Deg.C */ +double deg2rad(double deg); /* Rad2Deg.C */ + +#include "pi.h" +#ifndef PHI + #define PHI ((1.0+sqrt(5.0))/2.0) /* the golden number */ + #define INV_PHI (1.0/PHI) /* the golden ratio */ +#endif + +/* +** File: ISQRT.C +*/ + +struct int_sqrt { + unsigned sqrt, + frac; +}; + +void usqrt(unsigned long x, struct int_sqrt *q); + + +#endif /* SNIPMATH__H */ diff --git a/pdl/riscv/tests/automotive-IMA/basicmath_small/sniptype.h b/pdl/riscv/tests/automotive-IMA/basicmath_small/sniptype.h new file mode 100755 index 0000000..899ee5b --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/basicmath_small/sniptype.h @@ -0,0 +1,37 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** SNIPTYPE.H - Include file for SNIPPETS data types and commonly used macros +*/ + +#ifndef SNIPTYPE__H +#define SNIPTYPE__H + +#include /* For free() */ +#include /* For NULL & strlen() */ + +typedef enum {Error_ = -1, Success_, False_ = 0, True_} Boolean_T; + +/*#if !defined(WIN32) && !defined(_WIN32) && !defined(__NT__) \ + && !defined(_WINDOWS) + #if !defined(OS2)*/ + typedef unsigned char BYTE; + typedef unsigned long DWORD; +/* #endif*/ + typedef unsigned short WORD; +/*#else + #define WIN32_LEAN_AND_MEAN + #define NOGDI + #define NOSERVICE + #undef INC_OLE1 + #undef INC_OLE2 + #include + #define HUGE + #endif*/ + +#define NUL '\0' +#define LAST_CHAR(s) (((char *)s)[strlen(s) - 1]) +#define TOBOOL(x) (!(!(x))) +#define FREE(p) (free(p),(p)=NULL) + +#endif /* SNIPTYPE__H */ diff --git a/pdl/riscv/tests/automotive-IMA/bitcnts/Makefile b/pdl/riscv/tests/automotive-IMA/bitcnts/Makefile new file mode 100644 index 0000000..4284c03 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/bitcnts/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := bitcnt_1.c bitcnt_2.c bitcnt_3.c bitcnt_4.c bitcnts.c bitfiles.c bitstrng.c bstr_i.c +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET) + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET) -o bitcnts.run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) bitcnts.run > bitcnts.out + +clean: + rm bitcnts.run crt.o bitcnts.out diff --git a/pdl/riscv/tests/automotive-IMA/bitcnts/bitarray.c b/pdl/riscv/tests/automotive-IMA/bitcnts/bitarray.c new file mode 100755 index 0000000..b21e8fa --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/bitcnts/bitarray.c @@ -0,0 +1,34 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** Functions to maintain an arbitrary length array of bits +*/ + +#include "bitops.h" + +char *alloc_bit_array(size_t bits) +{ + char *set = calloc((bits + CHAR_BIT - 1) / CHAR_BIT, sizeof(char)); + + return set; +} + +int getbit(char *set, int number) +{ + set += number / CHAR_BIT; + return (*set & (1 << (number % CHAR_BIT))) != 0; /* 0 or 1 */ +} + +void setbit(char *set, int number, int value) +{ + set += number / CHAR_BIT; + if (value) + *set |= 1 << (number % CHAR_BIT); /* set bit */ + else *set &= ~(1 << (number % CHAR_BIT)); /* clear bit*/ +} + +void flipbit(char *set, int number) +{ + set += number / CHAR_BIT; + *set ^= 1 << (number % CHAR_BIT); /* flip bit */ +} diff --git a/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnt_1.c b/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnt_1.c new file mode 100755 index 0000000..d41f57f --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnt_1.c @@ -0,0 +1,43 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** Bit counter by Ratko Tomic +*/ + +#include "bitops.h" + +int CDECL bit_count(long x) +{ + int n = 0; +/* +** The loop will execute once for each bit of x set, this is in average +** twice as fast as the shift/test method. +*/ + if (x) do + n++; + while (0 != (x = x&(x-1))) ; + return(n); +} + +#ifdef TEST + +#include +#include "snip_str.h" /* For plural_text() macro */ + +main(int argc, char *argv[]) +{ + long n; + + while(--argc) + { + int i; + + n = atol(*++argv); + i = bit_count(n); + printf("%ld contains %d bit%s set\n", + n, i, plural_text(i)); + } + return 0; +} + +#endif /* TEST */ diff --git a/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnt_2.c b/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnt_2.c new file mode 100755 index 0000000..e34e119 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnt_2.c @@ -0,0 +1,40 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** Bit counter by Ratko Tomic +*/ + +#include "bitops.h" + +int CDECL bitcount(long i) +{ + i = ((i & 0xAAAAAAAAL) >> 1) + (i & 0x55555555L); + i = ((i & 0xCCCCCCCCL) >> 2) + (i & 0x33333333L); + i = ((i & 0xF0F0F0F0L) >> 4) + (i & 0x0F0F0F0FL); + i = ((i & 0xFF00FF00L) >> 8) + (i & 0x00FF00FFL); + i = ((i & 0xFFFF0000L) >> 16) + (i & 0x0000FFFFL); + return (int)i; +} + +#ifdef TEST + +#include +#include "snip_str.h" /* For plural_text() macro */ + +main(int argc, char *argv[]) +{ + long n; + + while(--argc) + { + int i; + + n = atol(*++argv); + i = bitcount(n); + printf("%ld contains %d bit%s set\n", + n, i, plural_text(i)); + } + return 0; +} + +#endif /* TEST */ diff --git a/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnt_3.c b/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnt_3.c new file mode 100755 index 0000000..f3d6088 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnt_3.c @@ -0,0 +1,117 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** BITCNT_3.C - Bit counting functions using table lookup +** +** public domain by Auke Reitsma and Bruce Wedding +*/ + +#include "bitops.h" /* from Snippets */ + +/* +** Bits table +*/ + +static char bits[256] = +{ + 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, /* 0 - 15 */ + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 16 - 31 */ + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 32 - 47 */ + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 48 - 63 */ + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 64 - 79 */ + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 80 - 95 */ + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 96 - 111 */ + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 112 - 127 */ + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 128 - 143 */ + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 144 - 159 */ + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 160 - 175 */ + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 176 - 191 */ + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 192 - 207 */ + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 208 - 223 */ + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 224 - 239 */ + 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8 /* 240 - 255 */ +}; + +/* +** Count bits in each nybble +** +** Note: Only the first 16 table entries are used, the rest could be +** omitted. +*/ + +int CDECL ntbl_bitcount(long int x) +{ + return + bits[ (int) (x & 0x0000000FUL) ] + + bits[ (int)((x & 0x000000F0UL) >> 4) ] + + bits[ (int)((x & 0x00000F00UL) >> 8) ] + + bits[ (int)((x & 0x0000F000UL) >> 12)] + + bits[ (int)((x & 0x000F0000UL) >> 16)] + + bits[ (int)((x & 0x00F00000UL) >> 20)] + + bits[ (int)((x & 0x0F000000UL) >> 24)] + + bits[ (int)((x & 0xF0000000UL) >> 28)]; +} + +/* +** Count bits in each byte +** +** by Bruce Wedding, works best on Watcom & Borland +*/ + +int CDECL BW_btbl_bitcount(long int x) +{ + union + { + unsigned char ch[4]; + long y; + } U; + + U.y = x; + + return bits[ U.ch[0] ] + bits[ U.ch[1] ] + + bits[ U.ch[3] ] + bits[ U.ch[2] ]; +} + +/* +** Count bits in each byte +** +** by Auke Reitsma, works best on Microsoft, Symantec, and others +*/ + +int CDECL AR_btbl_bitcount(long int x) +{ + unsigned char * Ptr = (unsigned char *) &x ; + int Accu ; + + Accu = bits[ *Ptr++ ]; + Accu += bits[ *Ptr++ ]; + Accu += bits[ *Ptr++ ]; + Accu += bits[ *Ptr ]; + return Accu; +} + +#ifdef TEST + +#include +#include "snip_str.h" /* For plural_text() macro */ + +main(int argc, char *argv[]) +{ + long n; + + while(--argc) + { + int i; + + n = atol(*++argv); + i = BW_btbl_bitcount(n); + printf("%ld contains %d bit%s set\n", + n, i, plural_text(i)); + i = AR_btbl_bitcount(n); + printf("%ld contains %d bit%s set\n", + n, i, plural_text(i)); + } + return 0; +} + +#endif /* TEST */ diff --git a/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnt_4.c b/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnt_4.c new file mode 100755 index 0000000..9f76cd0 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnt_4.c @@ -0,0 +1,82 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** BITCNT_4.C - Recursive bit counting functions using table lookup +** +** public domain by Bob Stout +*/ + +#include "bitops.h" /* from Snippets */ + +static char bits[256] = +{ + 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, /* 0 - 15 */ + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 16 - 31 */ + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 32 - 47 */ + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 48 - 63 */ + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 64 - 79 */ + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 80 - 95 */ + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 96 - 111 */ + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 112 - 127 */ + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 128 - 143 */ + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 144 - 159 */ + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 160 - 175 */ + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 176 - 191 */ + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 192 - 207 */ + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 208 - 223 */ + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 224 - 239 */ + 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8 /* 240 - 255 */ +}; + +/* +** Count bits in each nybble +** +** Note: Only the first 16 table entries are used, the rest could be +** omitted. +*/ + +int CDECL ntbl_bitcnt(long x) +{ + int cnt = bits[(int)(x & 0x0000000FL)]; + + if (0L != (x >>= 4)) + cnt += ntbl_bitcnt(x); + + return cnt; +} + +/* +** Count bits in each byte +*/ + +int CDECL btbl_bitcnt(long x) +{ + int cnt = bits[ ((char *)&x)[0] & 0xFF ]; + + if (0L != (x >>= 8)) + cnt += btbl_bitcnt(x); + return cnt; +} + +#ifdef TEST + +#include +#include "snip_str.h" /* For plural_text() macro */ + +main(int argc, char *argv[]) +{ + long n; + + while(--argc) + { + int i; + + n = atol(*++argv); + i = btbl_bitcnt(n); + printf("%ld contains %d bit%s set\n", + n, i, plural_text(i)); + } + return 0; +} + +#endif /* TEST */ diff --git a/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnts.c b/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnts.c new file mode 100755 index 0000000..381ecae --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/bitcnts/bitcnts.c @@ -0,0 +1,87 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** BITCNTS.C - Test program for bit counting functions +** +** public domain by Bob Stout & Auke Reitsma +*/ + +#include +#include +#include "conio.h" +#include +#include +#include +#include "bitops.h" + +#define FUNCS 7 + +static int CDECL bit_shifter(long int x); + +int main(int argc, char *argv[]) +{ + clock_t start, stop; + double ct, cmin = DBL_MAX, cmax = 0; + int i, cminix, cmaxix; + long j, n, seed; + int iterations; + static int (* CDECL pBitCntFunc[FUNCS])(long) = { + bit_count, + bitcount, + ntbl_bitcnt, + ntbl_bitcount, + /* btbl_bitcnt, DOESNT WORK*/ + BW_btbl_bitcount, + AR_btbl_bitcount, + bit_shifter + }; + static char *text[FUNCS] = { + "Optimized 1 bit/loop counter", + "Ratko's mystery algorithm", + "Recursive bit count by nybbles", + "Non-recursive bit count by nybbles", + /* "Recursive bit count by bytes",*/ + "Non-recursive bit count by bytes (BW)", + "Non-recursive bit count by bytes (AR)", + "Shift and count bits" + }; + //if (argc<2) { + //fprintf(stderr,"Usage: bitcnts \n"); + //exit(-1); + //} + //iterations=atoi(argv[1]); + iterations=75000; + puts("Bit counter algorithm benchmark\n"); + + for (i = 0; i < FUNCS; i++) { + start = clock(); + + for (j = n = 0, seed = rand(); j < iterations; j++, seed += 13) + n += pBitCntFunc[i](seed); + + stop = clock(); + ct = (stop - start) / (double)CLOCKS_PER_SEC; + if (ct < cmin) { + cmin = ct; + cminix = i; + } + if (ct > cmax) { + cmax = ct; + cmaxix = i; + } + + printf("%-38s> Time: %7.3f sec.; Bits: %ld\n", text[i], ct, n); + } + printf("\nBest > %s\n", text[cminix]); + printf("Worst > %s\n", text[cmaxix]); + return 0; +} + +static int CDECL bit_shifter(long int x) +{ + int i, n; + + for (i = n = 0; x && (i < (sizeof(long) * CHAR_BIT)); ++i, x >>= 1) + n += (int)(x & 1L); + return n; +} diff --git a/pdl/riscv/tests/automotive-IMA/bitcnts/bitfiles.c b/pdl/riscv/tests/automotive-IMA/bitcnts/bitfiles.c new file mode 100755 index 0000000..504d483 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/bitcnts/bitfiles.c @@ -0,0 +1,137 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** BITFILES.C - reading/writing bit files +** +** Public domain by Aare Tali +*/ + +#include +#include "bitops.h" + +bfile *bfopen(char *name, char *mode) +{ + bfile * bf; + + bf = malloc(sizeof(bfile)); + if (NULL == bf) + return NULL; + bf->file = fopen(name, mode); + if (NULL == bf->file) + { + free(bf); + return NULL; + } + bf->rcnt = 0; + bf->wcnt = 0; + return bf; +} + +int bfread(bfile *bf) +{ + if (0 == bf->rcnt) /* read new byte */ + { + bf->rbuf = (char)fgetc(bf->file); + bf->rcnt = 8; + } + bf->rcnt--; + return (bf->rbuf & (1 << bf->rcnt)) != 0; +} + +void bfwrite(int bit, bfile *bf) +{ + if (8 == bf->wcnt) /* write full byte */ + { + fputc(bf->wbuf, bf->file); + bf->wcnt = 0; + } + bf->wcnt++; + bf->wbuf <<= 1; + bf->wbuf |= bit & 1; +} + +void bfclose(bfile *bf) +{ + fclose(bf->file); + free(bf); +} + +#ifdef TEST + +void test1(void) +{ + bfile *out; + bfile *in; + FILE *in1; + FILE *in2; + + in = bfopen("bitfiles.c", "rb"); + out = bfopen("bitfiles.cc", "wb"); + if ((NULL == in) || (NULL == out)) + { + printf("Can't open/create test files\n"); + exit(1); + } + while (!feof(in->file)) + bfwrite(bfread(in), out); + bfclose(in); + bfclose(out); + in1 = fopen("bitfiles.c", "rb"); + in2 = fopen("bitfiles.cc", "rb"); + if ((NULL == in1) || (NULL == in2)) + { + printf("Can't open test files for verifying\n"); + exit(1); + } + while (!feof(in1) && !feof(in2)) + { + if (fgetc(in1) != fgetc(in2)) + { + printf("Files not identical, copy failed!\n"); + exit(1); + } + } + if (!feof(in1) || !feof(in2)) + { + printf("Not same size, copy failed!\n"); + exit(1); + } + fclose(in1); + fclose(in2); +} + +void test2(void) +{ + FILE *in1; + bfile *in2; + int ch; + + in1 = fopen("bitfiles.c", "rb"); + in2 = bfopen("bitfiles.cc", "rb"); + if ((NULL == in1) || (NULL == in2)) + { + printf("Can't open test files\n"); + exit(1); + } + while (!feof(in1) && !feof(in2->file)) + { + ch = fgetc(in1); + if (ch < ' ') + ch = '.'; + printf(" '%c' ", ch); + for (ch = 0; ch < 8; ch++) + printf("%c", "01"[bfread(in2)]); + printf(" "); + } + fclose(in1); + bfclose(in2); +} + +main() +{ + test1(); + test2(); + return 0; +} + +#endif /* TEST */ diff --git a/pdl/riscv/tests/automotive-IMA/bitcnts/bitops.h b/pdl/riscv/tests/automotive-IMA/bitcnts/bitops.h new file mode 100755 index 0000000..ae8e0ea --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/bitcnts/bitops.h @@ -0,0 +1,112 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** Macros and prototypes for bit operations +** +** public domain for SNIPPETS by: +** Scott Dudley +** Auke Reitsma +** Ratko Tomic +** Aare Tali +** J. Blauth +** Bruce Wedding +** Bob Stout +*/ + +#ifndef BITOPS__H +#define BITOPS__H + +#include +#include /* For size_t */ +#include /* For CHAR_BIT */ +#include "sniptype.h" /* For TOBOOL() */ +#include "extkword.h" /* For CDECL */ + +/* +** Macros to manipulate bits in any integral data type. +*/ + +#define BitSet(arg,posn) ((arg) | (1L << (posn))) +#define BitClr(arg,posn) ((arg) & ~(1L << (posn))) +#define BitFlp(arg,posn) ((arg) ^ (1L << (posn))) +#define BitTst(arg,posn) TOBOOL((arg) & (1L << (posn))) + +/* +** Macros to manipulate bits in an array of char. +** These macros assume CHAR_BIT is one of either 8, 16, or 32. +*/ + +#define MASK CHAR_BIT-1 +#define SHIFT ((CHAR_BIT==8)?3:(CHAR_BIT==16)?4:8) + +#define BitOff(a,x) ((void)((a)[(x)>>SHIFT] &= ~(1 << ((x)&MASK)))) +#define BitOn(a,x) ((void)((a)[(x)>>SHIFT] |= (1 << ((x)&MASK)))) +#define BitFlip(a,x) ((void)((a)[(x)>>SHIFT] ^= (1 << ((x)&MASK)))) +#define IsBit(a,x) ((a)[(x)>>SHIFT] & (1 << ((x)&MASK))) + +/* +** BITARRAY.C +*/ + +char *alloc_bit_array(size_t bits); +int getbit(char *set, int number); +void setbit(char *set, int number, int value); +void flipbit(char *set, int number); + +/* +** BITFILES.C +*/ + +typedef struct { + FILE * file; /* for stream I/O */ + char rbuf; /* read bit buffer */ + char rcnt; /* read bit count */ + char wbuf; /* write bit buffer */ + char wcnt; /* write bit count */ +} bfile; + +bfile * bfopen(char *name, char *mode); +int bfread(bfile *bf); +void bfwrite(int bit, bfile *bf); +void bfclose(bfile *bf); + +/* +** BITSTRNG.C +*/ + +void bitstring(char *str, long byze, int biz, int strwid); + +/* +** BSTR_I.C +*/ + +unsigned int bstr_i(char *cptr); + +/* +** BITCNT_1.C +*/ + +int CDECL bit_count(long x); + +/* +** BITCNT_2.C +*/ + +int CDECL bitcount(long i); + +/* +** BITCNT_3.C +*/ + +int CDECL ntbl_bitcount(long int x); +int CDECL BW_btbl_bitcount(long int x); +int CDECL AR_btbl_bitcount(long int x); + +/* +** BITCNT_4.C +*/ + +int CDECL ntbl_bitcnt(long x); +int CDECL btbl_bitcnt(long x); + +#endif /* BITOPS__H */ diff --git a/pdl/riscv/tests/automotive-IMA/bitcnts/bitstrng.c b/pdl/riscv/tests/automotive-IMA/bitcnts/bitstrng.c new file mode 100755 index 0000000..c9f326a --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/bitcnts/bitstrng.c @@ -0,0 +1,62 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** bitstring(): print bit pattern of bytes formatted to string. +** +** By J. Blauth, Sept. 1992. Hereby placed into the public domain. +** +** byze: value to transform to bitstring. +** biz: count of bits to be shown (counted from lowest bit, can be any +** even or odd number). +** strwid: total width the string shall have. Since between every 4 bits a +** blank (0x20) is inserted (not added after lowest bit), width of +** bitformat only is (biz+(biz/4-1)). Bits are printed right aligned, +** positions from highest bit to start of string filled with blanks. +** If value of strwid smaller than space needed to print all bits, +** strwid is ignored (e.g.: +** bitstr(s,b,16,5) results in 19 chars +'\0'). +** +** EXAMPLE: +** for (j = 1; j <= 16; j++) { bitstring(s, j, j, 16); puts(s); } +** 1: 1 +** 2: 10 +** 3: 011 +** d: 0 0000 0000 1101 +** e: 00 0000 0000 1110 +** f: 000 0000 0000 1111 +*/ + +#include "bitops.h" + +void bitstring(char *str, long byze, int biz, int strwid) +{ + int i, j; + + j = strwid - (biz + (biz >> 2)- (biz % 4 ? 0 : 1)); + for (i = 0; i < j; i++) + *str++ = ' '; + while (--biz >= 0) + { + *str++ = ((byze >> biz) & 1) + '0'; + if (!(biz % 4) && biz) + *str++ = ' '; + } + *str = '\0'; +} + +#ifdef TEST + +#include + +int main(void) +{ + char s[80]; long j; + for (j = 1L; j <= 16L; j++) + { + bitstring(s, (long)j, (int)j, 16); + printf("%2ld: %s\n", j, s); + } + return EXIT_SUCCESS; +} + +#endif /* TEST */ diff --git a/pdl/riscv/tests/automotive-IMA/bitcnts/bstr_i.c b/pdl/riscv/tests/automotive-IMA/bitcnts/bstr_i.c new file mode 100755 index 0000000..b4bfc73 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/bitcnts/bstr_i.c @@ -0,0 +1,42 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** Make an ascii binary string into an integer. +** +** Public domain by Bob Stout +*/ + +#include +#include "bitops.h" + +unsigned int bstr_i(char *cptr) +{ + unsigned int i, j = 0; + + while (cptr && *cptr && strchr("01", *cptr)) + { + i = *cptr++ - '0'; + j <<= 1; + j |= (i & 0x01); + } + return(j); +} + +#ifdef TEST + +#include + +int main(int argc, char *argv[]) +{ + char *arg; + unsigned int x; + + while (--argc) + { + x = bstr_i(arg = *++argv); + printf("Binary %s = %d = %04Xh\n", arg, x, x); + } + return EXIT_SUCCESS; +} + +#endif /* TEST */ diff --git a/pdl/riscv/tests/automotive-IMA/bitcnts/conio.h b/pdl/riscv/tests/automotive-IMA/bitcnts/conio.h new file mode 100755 index 0000000..dba7d92 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/bitcnts/conio.h @@ -0,0 +1,22 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** UNXCONIO.H - Port crucial DOS|Win|OS/2 non-blocking console I/O +** functions to Unix/Posix. +** +** public domain SNIPPETS header for use with Steve Poole's TERM_OPT.C +*/ + +#ifndef UNXCONIO__H +#define UNXCONIO__H + +#include +#include + +#define echo_on() term_option(0) +#define echo_off() term_option(1) + +int term_option(); +int getch(); + +#endif /* UNXCONIO__H */ diff --git a/pdl/riscv/tests/automotive-IMA/bitcnts/extkword.h b/pdl/riscv/tests/automotive-IMA/bitcnts/extkword.h new file mode 100755 index 0000000..ca0e2b9 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/bitcnts/extkword.h @@ -0,0 +1,102 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/*==================================================================== + + _MSC_VER Microsoft C 6.0 and later + _QC Microsoft Quick C 2.51 and later + __TURBOC__ Borland Turbo C, Turbo C++ and BC++ + __BORLANDC__ Borland C++ + __ZTC__ Zortech C and C++ + __SC__ Symantec C++ + __WATCOMC__ WATCOM C + __POWERC Mix Power C + __GNUC__ Gnu C + + Revised: + + 25-Sep-95 Bob Stout Original from PC-PORT.H + 30-Mar-96 Ed Blackman OS/2 mods for OS/2 ver 2.0 and up + 30-May-96 Andrew Clarke Added support for WATCOM C/C++ __NT__ macro. + 17-Jun-96 Bob Stout Added __FLAT__ macros support + 20-Aug-96 Bob Stout Eliminate Win32 conflicts +======================================================================*/ + + +/* prevent multiple inclusions of this header file */ + +#ifndef EXTKWORD__H +#define EXTKWORD__H + +#include /* For INT_MAX, LONG_MAX */ + +/* +** Watcom defines __FLAT__ for 32-bit environments and so will we +*/ + +#if !defined(__FLAT__) && !defined(__WATCOMC__) && !defined(_MSC_VER) + #if defined(__GNUC__) + #define __FLAT__ 1 + #elif defined (_WIN32) || defined(WIN32) || defined(__NT__) + #define __FLAT__ 1 + #elif defined(__INTSIZE) + #if (4 == __INTSIZE) + #define __FLAT__ 1 + #endif + #elif (defined(__ZTC__) && !defined(__SC__)) || defined(__TURBOC__) + #if ((INT_MAX != SHRT_MAX) && (SHRT_MAX == 32767)) + #define __FLAT__ 1 + #endif + #endif +#endif + +/* +** Correct extended keywords syntax +*/ + +#if defined(__OS2__) /* EBB: not sure this works for OS/2 1.x */ + #include + #define INTERRUPT + #define HUGE +#elif defined(_WIN32) || defined(WIN32) || defined(__NT__) + #define WIN32_LEAN_AND_MEAN + #define NOGDI + #define NOSERVICE + #undef INC_OLE1 + #undef INC_OLE2 + #include + #define INTERRUPT + #define HUGE +#else /* ! Win 32 or OS/2 */ +/* #if (defined(__POWERC) || (defined(__TURBOC__) && !defined(__BORLANDC__)) \ + || (defined(__ZTC__) && !defined(__SC__))) && !defined(__FLAT__) + #define FAR far + #define NEAR near + #define PASCAL pascal + #define CDECL cdecl + #if (defined(__ZTC__) && !defined(__SC__)) || (defined(__SC__) && \ + (__SC__ < 0x700)) + #define HUGE far + #define INTERRUPT + #else + #define HUGE huge + #define INTERRUPT interrupt + #endif*/ +/* #else + #if (defined(__MSDOS__) || defined(MSDOS)) && !defined(__FLAT__) + #define FAR _far + #define NEAR _near + #define HUGE _huge + #define PASCAL _pascal + #define CDECL _cdecl + #define INTERRUPT _interrupt + #else*/ + #define FAR + #define NEAR + #define HUGE + #define PASCAL + #define CDECL + #endif +/* #endif + #endif*/ + +#endif /* EXTKWORD__H */ diff --git a/pdl/riscv/tests/automotive-IMA/bitcnts/sniptype.h b/pdl/riscv/tests/automotive-IMA/bitcnts/sniptype.h new file mode 100755 index 0000000..399935d --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/bitcnts/sniptype.h @@ -0,0 +1,37 @@ +/* +++Date last modified: 05-Jul-1997 */ + +/* +** SNIPTYPE.H - Include file for SNIPPETS data types and commonly used macros +*/ + +#ifndef SNIPTYPE__H +#define SNIPTYPE__H + +#include /* For free() */ +#include /* For NULL & strlen() */ + +typedef enum {Error_ = -1, Success_, False_ = 0, True_} Boolean_T; + +/*#if !defined(WIN32) && !defined(_WIN32) && !defined(__NT__) \ + && !defined(_WINDOWS) + #if !defined(OS2)*/ + typedef unsigned char BYTE; + typedef unsigned long DWORD; +/* #endif*/ + typedef unsigned short WORD; +/*#else + #define WIN32_LEAN_AND_MEAN + #define NOGDI + #define NOSERVICE + #undef INC_OLE1 + #undef INC_OLE2 + #include + #define HUGE + #endif*/ + +#define NUL '\0' +#define LAST_CHAR(s) (((char *)s)[strlen(s) - 1]) +#define TOBOOL(x) (!(!(x))) +#define FREE(p) (free(p),(p)=NULL) + +#endif /* SNIPTYPE__H */ diff --git a/pdl/riscv/tests/automotive-IMA/qsort_large/Makefile b/pdl/riscv/tests/automotive-IMA/qsort_large/Makefile new file mode 100644 index 0000000..7146bf2 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/qsort_large/Makefile @@ -0,0 +1,18 @@ +CC := riscv64-unknown-elf-gcc +OBJDUMP := riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data + +TARGET := qsort_large.c +GCC_OPTS = -m32 -Wa,-march=RV32IMA -std=gnu99 -msoft-float +LINK_OPTS = -m32 -nostartfiles -lc -lm +LIB_DIR := -L../libac_sysc +LIBS := -lc -lac_sysc +HAL := ../rv_hal/get_id.S +SRCS := + +all: $(TARGET) + $(CC) -c ../rv_hal/crt.S -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float + $(CC) $(TARGET) -o qsort_large.run $(SRCS) $(HAL) $(LIB_DIR) $(LIBS) -T ../rv_hal/test.ld $(GCC_OPTS) $(LINK_OPTS) + $(OBJDUMP) qsort_large.run > qsort_large.out + +clean: + rm qsort_large.run crt.o qsort_large.out diff --git a/pdl/riscv/tests/automotive-IMA/qsort_large/input_large.dat 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a/pdl/riscv/tests/automotive-IMA/qsort_large/qsort_large.c b/pdl/riscv/tests/automotive-IMA/qsort_large/qsort_large.c new file mode 100755 index 0000000..fd9e557 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/qsort_large/qsort_large.c @@ -0,0 +1,58 @@ +#include +#include +#include + +#define UNLIMIT +#define MAXARRAY 6000 /* this number, if too large, will cause a seg. fault!! */ + +struct my3DVertexStruct { + int x, y, z; + double distance; +}; + +int compare(const void *elem1, const void *elem2) +{ + /* D = [(x1 - x2)^2 + (y1 - y2)^2 + (z1 - z2)^2]^(1/2) */ + /* sort based on distances from the origin... */ + + double distance1, distance2; + + distance1 = (*((struct my3DVertexStruct *)elem1)).distance; + distance2 = (*((struct my3DVertexStruct *)elem2)).distance; + + return (distance1 > distance2) ? 1 : ((distance1 == distance2) ? 0 : -1); +} + + +int +main(int argc, char *argv[]) { + struct my3DVertexStruct array[MAXARRAY]; + FILE *fp; + int i,count=0; + int x, y, z; + + char *path; + path = "/Desktop/RISC-V/riscv-sw-master/qsort_large/input_large.dat"; + + if (argc<2) { + fprintf(stderr,"Usage: qsort_large \n"); + exit(-1); + } + else { + fp = fopen(path,"r"); + + while((fscanf(fp, "%d", &x) == 1) && (fscanf(fp, "%d", &y) == 1) && (fscanf(fp, "%d", &z) == 1) && (count < MAXARRAY)) { + array[count].x = x; + array[count].y = y; + array[count].z = z; + array[count].distance = sqrt(pow(x, 2) + pow(y, 2) + pow(z, 2)); + count++; + } + } + printf("\nSorting %d vectors based on distance from the origin.\n\n",count); + qsort(array,count,sizeof(struct my3DVertexStruct),compare); + + for(i=0;i qsort_small.out + +clean: + rm qsort_small.run crt.o qsort_small.out diff --git a/pdl/riscv/tests/automotive-IMA/qsort_small/input_small.dat b/pdl/riscv/tests/automotive-IMA/qsort_small/input_small.dat new file mode 100755 index 0000000..d1b982d --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/qsort_small/input_small.dat @@ -0,0 +1,10000 @@ +Kurt +Vonneguts +Commencement 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+elses +Enjoy +your +body +Use +it +every +way +you +can +Dont +be +afraid +of +it +or +of +what +other +people +think +of +it +Its +the +greatest +instrument +youll +ever +own +Dance +even +if +you +have +nowhere +to +do +it +but +your +living +room +Read +the +directions +even +if +you +dont +follow +them +Do +not +read +beauty +magazines +They +will +only +make +you +feel +ugly +Get +to +know +your +parents +You +never +know +when +theyll +be +gone +for +good +Be +nice +to +your +siblings +Theyre +your +best +link +to +your +past +and +the +people +most +likely +to diff --git a/pdl/riscv/tests/automotive-IMA/qsort_small/qsort_small.c b/pdl/riscv/tests/automotive-IMA/qsort_small/qsort_small.c new file mode 100755 index 0000000..5e7bb37 --- /dev/null +++ b/pdl/riscv/tests/automotive-IMA/qsort_small/qsort_small.c @@ -0,0 +1,47 @@ +#include +#include +#include + +#define UNLIMIT +#define MAXARRAY 6000 /* this number, if too large, will cause a seg. fault!! */ + +struct myStringStruct { + char qstring[128]; +}; + +int compare(const void *elem1, const void *elem2) +{ + int result; + + result = strcmp((*((struct myStringStruct *)elem1)).qstring, (*((struct myStringStruct *)elem2)).qstring); + + return (result < 0) ? 1 : ((result == 0) ? 0 : -1); +} + + +int main(int argc, char *argv[]) { + struct myStringStruct array[MAXARRAY]; + FILE *fp; + int i,count=0; + char *path; + path = "/Desktop/RISC-V/riscv-sw-master/qsort_small/input_small.dat"; + + if (argc<2) { + fprintf(stderr,"Usage: qsort_small \n"); + exit(-1); + } + else { + fp = fopen(path,"r"); + fscanf(fp, "%s", &array[count].qstring); + printf("%s\n", array[count].qstring); + while((fscanf(fp, "%s", &array[count].qstring) == 1) && (count < MAXARRAY)) { + count++; + } + } + printf("\nSorting %d elements.\n\n",count); + qsort(array,count,sizeof(struct myStringStruct),compare); + + for(i=0;i susan.out + +clean: + rm susan.run crt.o susan.out diff --git a/pdl/riscv/tests/automotive-IMA/susan/input_large.pgm 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Proprietor: + Secretary of State for Defence, UK. 15 January 1997 + + This code is issued for research purposes only and remains the + property of the UK Secretary of State for Defence. This code must + not be passed on without this header information being kept + intact. This code must not be sold. + +\**********************************************************************/ + +/* }}} */ +/* {{{ Readme First */ + +/**********************************************************************\ + + SUSAN Version 2l + SUSAN = Smallest Univalue Segment Assimilating Nucleus + + Email: steve@fmrib.ox.ac.uk + WWW: http://www.fmrib.ox.ac.uk/~steve + + Related paper: + @article{Smith97, + author = "Smith, S.M. and Brady, J.M.", + title = "{SUSAN} - A New Approach to Low Level Image Processing", + journal = "Int. Journal of Computer Vision", + pages = "45--78", + volume = "23", + number = "1", + month = "May", + year = 1997} + + To be registered for automatic (bug) updates of SUSAN, send an email. + + Compile with: + gcc -O4 -o susan susan2l.c -lm + + See following section for different machine information. Please + report any bugs (and fixes). There are a few optional changes that + can be made in the "defines" section which follows shortly. + + Usage: type "susan" to get usage. Only PGM format files can be input + and output. Utilities such as the netpbm package and XV can be used + to convert to and from other formats. Any size of image can be + processed. + + This code is written using an emacs folding mode, making moving + around the different sections very easy. This is why there are + various marks within comments and why comments are indented. + + + SUSAN QUICK: + + This version of the SUSAN corner finder does not do all the + false-corner suppression and thus is faster and produced some false + positives, particularly on strong edges. However, because there are + less stages involving thresholds etc., the corners that are + correctly reported are usually more stable than those reported with + the full algorithm. Thus I recommend at least TRYING this algorithm + for applications where stability is important, e.g., tracking. + + THRESHOLDS: + + There are two thresholds which can be set at run-time. These are the + brightness threshold (t) and the distance threshold (d). + + SPATIAL CONTROL: d + + In SUSAN smoothing d controls the size of the Gaussian mask; its + default is 4.0. Increasing d gives more smoothing. In edge finding, + a fixed flat mask is used, either 37 pixels arranged in a "circle" + (default), or a 3 by 3 mask which gives finer detail. In corner + finding, only the larger 37 pixel mask is used; d is not + variable. In smoothing, the flat 3 by 3 mask can be used instead of + a larger Gaussian mask; this gives low smoothing and fast operation. + + BRIGHTNESS CONTROL: t + + In all three algorithms, t can be varied (default=20); this is the + main threshold to be varied. It determines the maximum difference in + greylevels between two pixels which allows them to be considered + part of the same "region" in the image. Thus it can be reduced to + give more edges or corners, i.e. to be more sensitive, and vice + versa. In smoothing, reducing t gives less smoothing, and vice + versa. Set t=10 for the test image available from the SUSAN web + page. + + ITERATIONS: + + With SUSAN smoothing, more smoothing can also be obtained by + iterating the algorithm several times. This has a different effect + from varying d or t. + + FIXED MASKS: + + 37 pixel mask: ooo 3 by 3 mask: ooo + ooooo ooo + ooooooo ooo + ooooooo + ooooooo + ooooo + ooo + + CORNER ATTRIBUTES dx, dy and I + (Only read this if you are interested in the C implementation or in + using corner attributes, e.g., for corner matching) + + Corners reported in the corner list have attributes associated with + them as well as positions. This is useful, for example, when + attempting to match corners from one image to another, as these + attributes can often be fairly unchanged between images. The + attributes are dx, dy and I. I is the value of image brightness at + the position of the corner. In the case of susan_corners_quick, dx + and dy are the first order derivatives (differentials) of the image + brightness in the x and y directions respectively, at the position + of the corner. In the case of normal susan corner finding, dx and dy + are scaled versions of the position of the centre of gravity of the + USAN with respect to the centre pixel (nucleus). + + BRIGHTNESS FUNCTION LUT IMPLEMENTATION: + (Only read this if you are interested in the C implementation) + + The SUSAN brightness function is implemented as a LUT + (Look-Up-Table) for speed. The resulting pointer-based code is a + little hard to follow, so here is a brief explanation. In + setup_brightness_lut() the LUT is setup. This mallocs enough space + for *bp and then repositions the pointer to the centre of the + malloced space. The SUSAN function e^-(x^6) or e^-(x^2) is + calculated and converted to a uchar in the range 0-100, for all + possible image brightness differences (including negative + ones). Thus bp[23] is the output for a brightness difference of 23 + greylevels. In the SUSAN algorithms this LUT is used as follows: + + p=in + (i-3)*x_size + j - 1; + p points to the first image pixel in the circular mask surrounding + point (x,y). + + cp=bp + in[i*x_size+j]; + cp points to a position in the LUT corresponding to the brightness + of the centre pixel (x,y). + + now for every pixel within the mask surrounding (x,y), + n+=*(cp-*p++); + the brightness difference function is found by moving the cp pointer + down by an amount equal to the value of the pixel pointed to by p, + thus subtracting the two brightness values and performing the + exponential function. This value is added to n, the running USAN + area. + + in SUSAN smoothing, the variable height mask is implemented by + multiplying the above by the moving mask pointer, reset for each new + centre pixel. + tmp = *dpt++ * *(cp-brightness); + +\**********************************************************************/ + +/* }}} */ +/* {{{ Machine Information */ + +/**********************************************************************\ + + Success has been reported with the following: + + MACHINE OS COMPILER + + Sun 4.1.4 bundled C, gcc + + Next + + SGI IRIX SGI cc + + DEC Unix V3.2+ + + IBM RISC AIX gcc + + PC Borland 5.0 + + PC Linux gcc-2.6.3 + + PC Win32 Visual C++ 4.0 (Console Application) + + PC Win95 Visual C++ 5.0 (Console Application) + Thanks to Niu Yongsheng : + Use the FOPENB option below + + PC DOS djgpp gnu C + Thanks to Mark Pettovello : + Use the FOPENB option below + + HP HP-UX bundled cc + Thanks to Brian Dixon : + in ksh: + export CCOPTS="-Aa -D_HPUX_SOURCE | -lM" + cc -O3 -o susan susan2l.c + +\**********************************************************************/ + +/* }}} */ +/* {{{ History */ + +/**********************************************************************\ + + SUSAN Version 2l, 12/2/99 + Changed GNUDOS option to FOPENB. + (Thanks to Niu Yongsheng .) + Took out redundant "sq=sq/2;". + + SUSAN Version 2k, 19/8/98: + In corner finding: + Changed if(yyx_size) etc. tests in smoothing. + Added a couple of free() calls for cgx and cgy. + (Thanks to geoffb@ucs.ed.ac.uk - Geoff Browitt.) + + SUSAN Version 2i, 21/7/97: + Added information about corner attributes. + + SUSAN Version 2h, 16/12/96: + Added principle (initial enhancement) option. + + SUSAN Version 2g, 2/7/96: + Minor superficial changes to code. + + SUSAN Version 2f, 16/1/96: + Added GNUDOS option (now called FOPENB; see options below). + + SUSAN Version 2e, 9/1/96: + Added -b option. + Fixed 1 pixel horizontal offset error for drawing edges. + + SUSAN Version 2d, 27/11/95: + Fixed loading of certain PGM files in get_image (again!) + + SUSAN Version 2c, 22/11/95: + Fixed loading of certain PGM files in get_image. + (Thanks to qu@San-Jose.ate.slb.com - Gongyuan Qu.) + + SUSAN Version 2b, 9/11/95: + removed "z==" error in edges routines. + + SUSAN Version 2a, 6/11/95: + Removed a few unnecessary variable declarations. + Added different machine information. + Changed "header" in get_image to char. + + SUSAN Version 2, 1/11/95: first combined version able to take any + image sizes. + + SUSAN "Versions 1", circa 1992: the various SUSAN algorithms were + developed during my doctorate within different programs and for + fixed image sizes. The algorithms themselves are virtually unaltered + between "versions 1" and the combined program, version 2. + +\**********************************************************************/ + +/* }}} */ +/* {{{ defines, includes and typedefs */ + +/* ********** Optional settings */ + +#ifndef PPC +typedef int TOTAL_TYPE; /* this is faster for "int" but should be "float" for large d masks */ +#else +typedef float TOTAL_TYPE; /* for my PowerPC accelerator only */ +#endif + +/*#define FOPENB*/ /* uncomment if using djgpp gnu C for DOS or certain Win95 compilers */ +#define SEVEN_SUPP /* size for non-max corner suppression; SEVEN_SUPP or FIVE_SUPP */ +#define MAX_CORNERS 15000 /* max corners per frame */ + +/* ********** Leave the rest - but you may need to remove one or both of sys/file.h and malloc.h lines */ + +#include +#include +#include +#include +#include /* may want to remove this line */ +#include /* may want to remove this line */ +#define exit_error(IFB,IFC) { fprintf(stderr,IFB,IFC); exit(0); } +#define FTOI(a) ( (a) < 0 ? ((int)(a-0.5)) : ((int)(a+0.5)) ) +typedef unsigned char uchar; +typedef struct {int x,y,info, dx, dy, I;} CORNER_LIST[MAX_CORNERS]; + +/* }}} */ +/* {{{ usage() */ + +usage() +{ + printf("Usage: susan [options]\n\n"); + + printf("-s : Smoothing mode (default)\n"); + printf("-e : Edges mode\n"); + printf("-c : Corners mode\n\n"); + + printf("See source code for more information about setting the thresholds\n"); + printf("-t : Brightness threshold, all modes (default=20)\n"); + printf("-d : Distance threshold, smoothing mode, (default=4) (use next option instead for flat 3x3 mask)\n"); + printf("-3 : Use flat 3x3 mask, edges or smoothing mode\n"); + printf("-n : No post-processing on the binary edge map (runs much faster); edges mode\n"); + printf("-q : Use faster (and usually stabler) corner mode; edge-like corner suppression not carried out; corners mode\n"); + printf("-b : Mark corners/edges with single black points instead of black with white border; corners or edges mode\n"); + printf("-p : Output initial enhancement image only; corners or edges mode (default is edges mode)\n"); + + printf("\nSUSAN Version 2l (C) 1995-1997 Stephen Smith, DRA UK. steve@fmrib.ox.ac.uk\n"); + + exit(0); +} + +/* }}} */ +/* {{{ get_image(filename,in,x_size,y_size) */ + +/* {{{ int getint(fp) derived from XV */ + +int getint(fd) + FILE *fd; +{ + int c, i; + char dummy[10000]; + + c = getc(fd); + while (1) /* find next integer */ + { + if (c=='#') /* if we're at a comment, read to end of line */ + fgets(dummy,9000,fd); + if (c==EOF) + exit_error("Image %s not binary PGM.\n","is"); + if (c>='0' && c<='9') + break; /* found what we were looking for */ + c = getc(fd); + } + + /* we're at the start of a number, continue until we hit a non-number */ + i = 0; + while (1) { + i = (i*10) + (c - '0'); + c = getc(fd); + if (c==EOF) return (i); + if (c<'0' || c>'9') break; + } + + return (i); +} + +/* }}} */ + +void get_image(filename,in,x_size,y_size) + char filename[200]; + unsigned char **in; + int *x_size, *y_size; +{ +FILE *fd; +char header [100]; +int tmp; + +#ifdef FOPENB + if ((fd=fopen(filename,"rb")) == NULL) +#else + if ((fd=fopen(filename,"r")) == NULL) +#endif + exit_error("Can't input image %s.\n",filename); + + /* {{{ read header */ + + header[0]=fgetc(fd); + header[1]=fgetc(fd); + if(!(header[0]=='P' && header[1]=='5')) + exit_error("Image %s does not have binary PGM header.\n",filename); + + *x_size = getint(fd); + *y_size = getint(fd); + tmp = getint(fd); + +/* }}} */ + + *in = (uchar *) malloc(*x_size * *y_size); + + if (fread(*in,1,*x_size * *y_size,fd) == 0) + exit_error("Image %s is wrong size.\n",filename); + + fclose(fd); +} + +/* }}} */ +/* {{{ put_image(filename,in,x_size,y_size) */ + +put_image(filename,in,x_size,y_size) + char filename [100], + *in; + int x_size, + y_size; +{ +FILE *fd; + +#ifdef FOPENB + if ((fd=fopen(filename,"wb")) == NULL) +#else + if ((fd=fopen(filename,"w")) == NULL) +#endif + exit_error("Can't output image%s.\n",filename); + + fprintf(fd,"P5\n"); + fprintf(fd,"%d %d\n",x_size,y_size); + fprintf(fd,"255\n"); + + if (fwrite(in,x_size*y_size,1,fd) != 1) + exit_error("Can't write image %s.\n",filename); + + fclose(fd); +} + +/* }}} */ +/* {{{ int_to_uchar(r,in,size) */ + +int_to_uchar(r,in,size) + uchar *in; + int *r, size; +{ +int i, + max_r=r[0], + min_r=r[0]; + + for (i=0; i max_r ) + max_r=r[i]; + if ( r[i] < min_r ) + min_r=r[i]; + } + + /*printf("min=%d max=%d\n",min_r,max_r);*/ + + max_r-=min_r; + + for (i=0; ip[l+1]) + { + tmp=p[l]; p[l]=p[l+1]; p[l+1]=tmp; + } + + return( (p[3]+p[4]) / 2 ); +} + +/* }}} */ +/* {{{ enlarge(in,tmp_image,x_size,y_size,border) */ + +/* this enlarges "in" so that borders can be dealt with easily */ + +enlarge(in,tmp_image,x_size,y_size,border) + uchar **in; + uchar *tmp_image; + int *x_size, *y_size, border; +{ +int i, j; + + for(i=0; i<*y_size; i++) /* copy *in into tmp_image */ + memcpy(tmp_image+(i+border)*(*x_size+2*border)+border, *in+i* *x_size, *x_size); + + for(i=0; i15) && (total==0) ) + { + printf("Distance_thresh (%f) too big for integer arithmetic.\n",dt); + printf("Either reduce it to <=15 or recompile with variable \"total\"\n"); + printf("as a float: see top \"defines\" section.\n"); + exit(0); + } + + if ( (2*mask_size+1>x_size) || (2*mask_size+1>y_size) ) + { + printf("Mask size (1.5*distance_thresh+1=%d) too big for image (%dx%d).\n",mask_size,x_size,y_size); + exit(0); + } + + tmp_image = (uchar *) malloc( (x_size+mask_size*2) * (y_size+mask_size*2) ); + enlarge(&in,tmp_image,&x_size,&y_size,mask_size); + +/* }}} */ + + if (three_by_three==0) + { /* large Gaussian masks */ + /* {{{ setup distance lut */ + + n_max = (mask_size*2) + 1; + + increment = x_size - n_max; + + dp = (unsigned char *)malloc(n_max*n_max); + dpt = dp; + temp = -(dt*dt); + + for(i=-mask_size; i<=mask_size; i++) + for(j=-mask_size; j<=mask_size; j++) + { + x = (int) (100.0 * exp( ((float)((i*i)+(j*j))) / temp )); + *dpt++ = (unsigned char)x; + } + +/* }}} */ + /* {{{ main section */ + + for (i=mask_size;im) { m=l[y+y+y+x]; a=y; b=x; } + + if (m>0) + { + if (mid[i*x_size+j]<4) + mid[(i+a-1)*x_size+j+b-1] = 4; + else + mid[(i+a-1)*x_size+j+b-1] = mid[i*x_size+j]+1; + if ( (a+a+b) < 3 ) /* need to jump back in image */ + { + i+=a-1; + j+=b-2; + if (i<4) i=4; + if (j<4) j=4; + } + } + } + +/* }}} */ + /* {{{ n==2 */ + + if (n==2) + { + /* put in a bit here to straighten edges */ + b00 = mid[(i-1)*x_size+j-1]<8; /* corners of 3x3 */ + b02 = mid[(i-1)*x_size+j+1]<8; + b20 = mid[(i+1)*x_size+j-1]<8; + b22 = mid[(i+1)*x_size+j+1]<8; + if ( ((b00+b02+b20+b22)==2) && ((b00|b22)&(b02|b20))) + { /* case: move a point back into line. + e.g. X O X CAN become X X X + O X O O O O + O O O O O O */ + if (b00) + { + if (b02) { x=0; y=-1; } + else { x=-1; y=0; } + } + else + { + if (b02) { x=1; y=0; } + else { x=0; y=1; } + } + if (((float)r[(i+y)*x_size+j+x]/(float)centre) > 0.7) + { + if ( ( (x==0) && (mid[(i+(2*y))*x_size+j]>7) && (mid[(i+(2*y))*x_size+j-1]>7) && (mid[(i+(2*y))*x_size+j+1]>7) ) || + ( (y==0) && (mid[(i)*x_size+j+(2*x)]>7) && (mid[(i+1)*x_size+j+(2*x)]>7) && (mid[(i-1)*x_size+j+(2*x)]>7) ) ) + { + mid[(i)*x_size+j]=100; + mid[(i+y)*x_size+j+x]=3; /* no jumping needed */ + } + } + } + else + { + b01 = mid[(i-1)*x_size+j ]<8; + b12 = mid[(i )*x_size+j+1]<8; + b21 = mid[(i+1)*x_size+j ]<8; + b10 = mid[(i )*x_size+j-1]<8; + /* {{{ right angle ends - not currently used */ + +#ifdef IGNORETHIS + if ( (b00&b01)|(b00&b10)|(b02&b01)|(b02&b12)|(b20&b10)|(b20&b21)|(b22&b21)|(b22&b12) ) + { /* case; right angle ends. clean up. + e.g.; X X O CAN become X X O + O X O O O O + O O O O O O */ + if ( ((b01)&(mid[(i-2)*x_size+j-1]>7)&(mid[(i-2)*x_size+j]>7)&(mid[(i-2)*x_size+j+1]>7)& + ((b00&((2*r[(i-1)*x_size+j+1])>centre))|(b02&((2*r[(i-1)*x_size+j-1])>centre)))) | + ((b10)&(mid[(i-1)*x_size+j-2]>7)&(mid[(i)*x_size+j-2]>7)&(mid[(i+1)*x_size+j-2]>7)& + ((b00&((2*r[(i+1)*x_size+j-1])>centre))|(b20&((2*r[(i-1)*x_size+j-1])>centre)))) | + ((b12)&(mid[(i-1)*x_size+j+2]>7)&(mid[(i)*x_size+j+2]>7)&(mid[(i+1)*x_size+j+2]>7)& + ((b02&((2*r[(i+1)*x_size+j+1])>centre))|(b22&((2*r[(i-1)*x_size+j+1])>centre)))) | + ((b21)&(mid[(i+2)*x_size+j-1]>7)&(mid[(i+2)*x_size+j]>7)&(mid[(i+2)*x_size+j+1]>7)& + ((b20&((2*r[(i+1)*x_size+j+1])>centre))|(b22&((2*r[(i+1)*x_size+j-1])>centre)))) ) + { + mid[(i)*x_size+j]=100; + if (b10&b20) j-=2; + if (b00|b01|b02) { i--; j-=2; } + } + } +#endif + +/* }}} */ + if ( ((b01+b12+b21+b10)==2) && ((b10|b12)&(b01|b21)) && + ((b01&((mid[(i-2)*x_size+j-1]<8)|(mid[(i-2)*x_size+j+1]<8)))|(b10&((mid[(i-1)*x_size+j-2]<8)|(mid[(i+1)*x_size+j-2]<8)))| + (b12&((mid[(i-1)*x_size+j+2]<8)|(mid[(i+1)*x_size+j+2]<8)))|(b21&((mid[(i+2)*x_size+j-1]<8)|(mid[(i+2)*x_size+j+1]<8)))) ) + { /* case; clears odd right angles. + e.g.; O O O becomes O O O + X X O X O O + O X O O X O */ + mid[(i)*x_size+j]=100; + i--; /* jump back */ + j-=2; + if (i<4) i=4; + if (j<4) j=4; + } + } + } + +/* }}} */ + /* {{{ n>2 the thinning is done here without breaking connectivity */ + + if (n>2) + { + b01 = mid[(i-1)*x_size+j ]<8; + b12 = mid[(i )*x_size+j+1]<8; + b21 = mid[(i+1)*x_size+j ]<8; + b10 = mid[(i )*x_size+j-1]<8; + if((b01+b12+b21+b10)>1) + { + b00 = mid[(i-1)*x_size+j-1]<8; + b02 = mid[(i-1)*x_size+j+1]<8; + b20 = mid[(i+1)*x_size+j-1]<8; + b22 = mid[(i+1)*x_size+j+1]<8; + p1 = b00 | b01; + p2 = b02 | b12; + p3 = b22 | b21; + p4 = b20 | b10; + + if( ((p1 + p2 + p3 + p4) - ((b01 & p2)+(b12 & p3)+(b21 & p4)+(b10 & p1))) < 2) + { + mid[(i)*x_size+j]=100; + i--; + j-=2; + if (i<4) i=4; + if (j<4) j=4; + } + } + } + +/* }}} */ + } +} + +/* }}} */ +/* {{{ susan_edges(in,r,sf,max_no,out) */ + +susan_edges(in,r,mid,bp,max_no,x_size,y_size) + uchar *in, *bp, *mid; + int *r, max_no, x_size, y_size; +{ +float z; +int do_symmetry, i, j, m, n, a, b, x, y, w; +uchar c,*p,*cp; + + memset (r,0,x_size * y_size * sizeof(int)); + + for (i=3;i0) + { + m=r[i*x_size+j]; + n=max_no - m; + cp=bp + in[i*x_size+j]; + + if (n>600) + { + p=in + (i-3)*x_size + j - 1; + x=0;y=0; + + c=*(cp-*p++);x-=c;y-=3*c; + c=*(cp-*p++);y-=3*c; + c=*(cp-*p);x+=c;y-=3*c; + p+=x_size-3; + + c=*(cp-*p++);x-=2*c;y-=2*c; + c=*(cp-*p++);x-=c;y-=2*c; + c=*(cp-*p++);y-=2*c; + c=*(cp-*p++);x+=c;y-=2*c; + c=*(cp-*p);x+=2*c;y-=2*c; + p+=x_size-5; + + c=*(cp-*p++);x-=3*c;y-=c; + c=*(cp-*p++);x-=2*c;y-=c; + c=*(cp-*p++);x-=c;y-=c; + c=*(cp-*p++);y-=c; + c=*(cp-*p++);x+=c;y-=c; + c=*(cp-*p++);x+=2*c;y-=c; + c=*(cp-*p);x+=3*c;y-=c; + p+=x_size-6; + + c=*(cp-*p++);x-=3*c; + c=*(cp-*p++);x-=2*c; + c=*(cp-*p);x-=c; + p+=2; + c=*(cp-*p++);x+=c; + c=*(cp-*p++);x+=2*c; + c=*(cp-*p);x+=3*c; + p+=x_size-6; + + c=*(cp-*p++);x-=3*c;y+=c; + c=*(cp-*p++);x-=2*c;y+=c; + c=*(cp-*p++);x-=c;y+=c; + c=*(cp-*p++);y+=c; + c=*(cp-*p++);x+=c;y+=c; + c=*(cp-*p++);x+=2*c;y+=c; + c=*(cp-*p);x+=3*c;y+=c; + p+=x_size-5; + + c=*(cp-*p++);x-=2*c;y+=2*c; + c=*(cp-*p++);x-=c;y+=2*c; + c=*(cp-*p++);y+=2*c; + c=*(cp-*p++);x+=c;y+=2*c; + c=*(cp-*p);x+=2*c;y+=2*c; + p+=x_size-3; + + c=*(cp-*p++);x-=c;y+=3*c; + c=*(cp-*p++);y+=3*c; + c=*(cp-*p);x+=c;y+=3*c; + + z = sqrt((float)((x*x) + (y*y))); + if (z > (0.9*(float)n)) /* 0.5 */ + { + do_symmetry=0; + if (x==0) + z=1000000.0; + else + z=((float)y) / ((float)x); + if (z < 0) { z=-z; w=-1; } + else w=1; + if (z < 0.5) { /* vert_edge */ a=0; b=1; } + else { if (z > 2.0) { /* hor_edge */ a=1; b=0; } + else { /* diag_edge */ if (w>0) { a=1; b=1; } + else { a=-1; b=1; }}} + if ( (m > r[(i+a)*x_size+j+b]) && (m >= r[(i-a)*x_size+j-b]) && + (m > r[(i+(2*a))*x_size+j+(2*b)]) && (m >= r[(i-(2*a))*x_size+j-(2*b)]) ) + mid[i*x_size+j] = 1; + } + else + do_symmetry=1; + } + else + do_symmetry=1; + + if (do_symmetry==1) + { + p=in + (i-3)*x_size + j - 1; + x=0; y=0; w=0; + + /* | \ + y -x- w + | \ */ + + c=*(cp-*p++);x+=c;y+=9*c;w+=3*c; + c=*(cp-*p++);y+=9*c; + c=*(cp-*p);x+=c;y+=9*c;w-=3*c; + p+=x_size-3; + + c=*(cp-*p++);x+=4*c;y+=4*c;w+=4*c; + c=*(cp-*p++);x+=c;y+=4*c;w+=2*c; + c=*(cp-*p++);y+=4*c; + c=*(cp-*p++);x+=c;y+=4*c;w-=2*c; + c=*(cp-*p);x+=4*c;y+=4*c;w-=4*c; + p+=x_size-5; + + c=*(cp-*p++);x+=9*c;y+=c;w+=3*c; + c=*(cp-*p++);x+=4*c;y+=c;w+=2*c; + c=*(cp-*p++);x+=c;y+=c;w+=c; + c=*(cp-*p++);y+=c; + c=*(cp-*p++);x+=c;y+=c;w-=c; + c=*(cp-*p++);x+=4*c;y+=c;w-=2*c; + c=*(cp-*p);x+=9*c;y+=c;w-=3*c; + p+=x_size-6; + + c=*(cp-*p++);x+=9*c; + c=*(cp-*p++);x+=4*c; + c=*(cp-*p);x+=c; + p+=2; + c=*(cp-*p++);x+=c; + c=*(cp-*p++);x+=4*c; + c=*(cp-*p);x+=9*c; + p+=x_size-6; + + c=*(cp-*p++);x+=9*c;y+=c;w-=3*c; + c=*(cp-*p++);x+=4*c;y+=c;w-=2*c; + c=*(cp-*p++);x+=c;y+=c;w-=c; + c=*(cp-*p++);y+=c; + c=*(cp-*p++);x+=c;y+=c;w+=c; + c=*(cp-*p++);x+=4*c;y+=c;w+=2*c; + c=*(cp-*p);x+=9*c;y+=c;w+=3*c; + p+=x_size-5; + + c=*(cp-*p++);x+=4*c;y+=4*c;w-=4*c; + c=*(cp-*p++);x+=c;y+=4*c;w-=2*c; + c=*(cp-*p++);y+=4*c; + c=*(cp-*p++);x+=c;y+=4*c;w+=2*c; + c=*(cp-*p);x+=4*c;y+=4*c;w+=4*c; + p+=x_size-3; + + c=*(cp-*p++);x+=c;y+=9*c;w-=3*c; + c=*(cp-*p++);y+=9*c; + c=*(cp-*p);x+=c;y+=9*c;w+=3*c; + + if (y==0) + z = 1000000.0; + else + z = ((float)x) / ((float)y); + if (z < 0.5) { /* vertical */ a=0; b=1; } + else { if (z > 2.0) { /* horizontal */ a=1; b=0; } + else { /* diagonal */ if (w>0) { a=-1; b=1; } + else { a=1; b=1; }}} + if ( (m > r[(i+a)*x_size+j+b]) && (m >= r[(i-a)*x_size+j-b]) && + (m > r[(i+(2*a))*x_size+j+(2*b)]) && (m >= r[(i-(2*a))*x_size+j-(2*b)]) ) + mid[i*x_size+j] = 2; + } + } + } +} + +/* }}} */ +/* {{{ susan_edges_small(in,r,sf,max_no,out) */ + +susan_edges_small(in,r,mid,bp,max_no,x_size,y_size) + uchar *in, *bp, *mid; + int *r, max_no, x_size, y_size; +{ +float z; +int do_symmetry, i, j, m, n, a, b, x, y, w; +uchar c,*p,*cp; + + memset (r,0,x_size * y_size * sizeof(int)); + + max_no = 730; /* ho hum ;) */ + + for (i=1;i0) + { + m=r[i*x_size+j]; + n=max_no - m; + cp=bp + in[i*x_size+j]; + + if (n>250) + { + p=in + (i-1)*x_size + j - 1; + x=0;y=0; + + c=*(cp-*p++);x-=c;y-=c; + c=*(cp-*p++);y-=c; + c=*(cp-*p);x+=c;y-=c; + p+=x_size-2; + + c=*(cp-*p);x-=c; + p+=2; + c=*(cp-*p);x+=c; + p+=x_size-2; + + c=*(cp-*p++);x-=c;y+=c; + c=*(cp-*p++);y+=c; + c=*(cp-*p);x+=c;y+=c; + + z = sqrt((float)((x*x) + (y*y))); + if (z > (0.4*(float)n)) /* 0.6 */ + { + do_symmetry=0; + if (x==0) + z=1000000.0; + else + z=((float)y) / ((float)x); + if (z < 0) { z=-z; w=-1; } + else w=1; + if (z < 0.5) { /* vert_edge */ a=0; b=1; } + else { if (z > 2.0) { /* hor_edge */ a=1; b=0; } + else { /* diag_edge */ if (w>0) { a=1; b=1; } + else { a=-1; b=1; }}} + if ( (m > r[(i+a)*x_size+j+b]) && (m >= r[(i-a)*x_size+j-b]) ) + mid[i*x_size+j] = 1; + } + else + do_symmetry=1; + } + else + do_symmetry=1; + + if (do_symmetry==1) + { + p=in + (i-1)*x_size + j - 1; + x=0; y=0; w=0; + + /* | \ + y -x- w + | \ */ + + c=*(cp-*p++);x+=c;y+=c;w+=c; + c=*(cp-*p++);y+=c; + c=*(cp-*p);x+=c;y+=c;w-=c; + p+=x_size-2; + + c=*(cp-*p);x+=c; + p+=2; + c=*(cp-*p);x+=c; + p+=x_size-2; + + c=*(cp-*p++);x+=c;y+=c;w-=c; + c=*(cp-*p++);y+=c; + c=*(cp-*p);x+=c;y+=c;w+=c; + + if (y==0) + z = 1000000.0; + else + z = ((float)x) / ((float)y); + if (z < 0.5) { /* vertical */ a=0; b=1; } + else { if (z > 2.0) { /* horizontal */ a=1; b=0; } + else { /* diagonal */ if (w>0) { a=-1; b=1; } + else { a=1; b=1; }}} + if ( (m > r[(i+a)*x_size+j+b]) && (m >= r[(i-a)*x_size+j-b]) ) + mid[i*x_size+j] = 2; + } + } + } +} + +/* }}} */ + +/* }}} */ +/* {{{ corners */ + +/* {{{ corner_draw(in,corner_list,drawing_mode) */ + +corner_draw(in,corner_list,x_size,drawing_mode) + uchar *in; + CORNER_LIST corner_list; + int x_size, drawing_mode; +{ +uchar *p; +int n=0; + + while(corner_list[n].info != 7) + { + if (drawing_mode==0) + { + p = in + (corner_list[n].y-1)*x_size + corner_list[n].x - 1; + *p++=255; *p++=255; *p=255; p+=x_size-2; + *p++=255; *p++=0; *p=255; p+=x_size-2; + *p++=255; *p++=255; *p=255; + n++; + } + else + { + p = in + corner_list[n].y*x_size + corner_list[n].x; + *p=0; + n++; + } + } +} + +/* }}} */ +/* {{{ susan(in,r,sf,max_no,corner_list) */ + +susan_corners(in,r,bp,max_no,corner_list,x_size,y_size) + uchar *in, *bp; + int *r, max_no, x_size, y_size; + CORNER_LIST corner_list; +{ +int n,x,y,sq,xx,yy, + i,j,*cgx,*cgy; +float divide; +uchar c,*p,*cp; + + memset (r,0,x_size * y_size * sizeof(int)); + + cgx=(int *)malloc(x_size*y_size*sizeof(int)); + cgy=(int *)malloc(x_size*y_size*sizeof(int)); + + for (i=5;i ((n*n)/2) ) + { + if(yy290){ + r[i*x_size+j] = max_no-n; + cgx[i*x_size+j] = (51*x)/n; + cgy[i*x_size+j] = (51*y)/n;} + } + } +}}}}}}}}}}}}}}}}}}} + + /* to locate the local maxima */ + n=0; + for (i=5;i0) { + /* 5x5 mask */ +#ifdef FIVE_SUPP + if ( + (x>r[(i-1)*x_size+j+2]) && + (x>r[(i )*x_size+j+1]) && + (x>r[(i )*x_size+j+2]) && + (x>r[(i+1)*x_size+j-1]) && + (x>r[(i+1)*x_size+j ]) && + (x>r[(i+1)*x_size+j+1]) && + (x>r[(i+1)*x_size+j+2]) && + (x>r[(i+2)*x_size+j-2]) && + (x>r[(i+2)*x_size+j-1]) && + (x>r[(i+2)*x_size+j ]) && + (x>r[(i+2)*x_size+j+1]) && + (x>r[(i+2)*x_size+j+2]) && + (x>=r[(i-2)*x_size+j-2]) && + (x>=r[(i-2)*x_size+j-1]) && + (x>=r[(i-2)*x_size+j ]) && + (x>=r[(i-2)*x_size+j+1]) && + (x>=r[(i-2)*x_size+j+2]) && + (x>=r[(i-1)*x_size+j-2]) && + (x>=r[(i-1)*x_size+j-1]) && + (x>=r[(i-1)*x_size+j ]) && + (x>=r[(i-1)*x_size+j+1]) && + (x>=r[(i )*x_size+j-2]) && + (x>=r[(i )*x_size+j-1]) && + (x>=r[(i+1)*x_size+j-2]) ) +#endif +#ifdef SEVEN_SUPP + if ( + (x>r[(i-3)*x_size+j-3]) && + (x>r[(i-3)*x_size+j-2]) && + (x>r[(i-3)*x_size+j-1]) && + (x>r[(i-3)*x_size+j ]) && + (x>r[(i-3)*x_size+j+1]) && + (x>r[(i-3)*x_size+j+2]) && + (x>r[(i-3)*x_size+j+3]) && + + (x>r[(i-2)*x_size+j-3]) && + (x>r[(i-2)*x_size+j-2]) && + (x>r[(i-2)*x_size+j-1]) && + (x>r[(i-2)*x_size+j ]) && + (x>r[(i-2)*x_size+j+1]) && + (x>r[(i-2)*x_size+j+2]) && + (x>r[(i-2)*x_size+j+3]) && + + (x>r[(i-1)*x_size+j-3]) && + (x>r[(i-1)*x_size+j-2]) && + (x>r[(i-1)*x_size+j-1]) && + (x>r[(i-1)*x_size+j ]) && + (x>r[(i-1)*x_size+j+1]) && + (x>r[(i-1)*x_size+j+2]) && + (x>r[(i-1)*x_size+j+3]) && + + (x>r[(i)*x_size+j-3]) && + (x>r[(i)*x_size+j-2]) && + (x>r[(i)*x_size+j-1]) && + (x>=r[(i)*x_size+j+1]) && + (x>=r[(i)*x_size+j+2]) && + (x>=r[(i)*x_size+j+3]) && + + (x>=r[(i+1)*x_size+j-3]) && + (x>=r[(i+1)*x_size+j-2]) && + (x>=r[(i+1)*x_size+j-1]) && + (x>=r[(i+1)*x_size+j ]) && + (x>=r[(i+1)*x_size+j+1]) && + (x>=r[(i+1)*x_size+j+2]) && + (x>=r[(i+1)*x_size+j+3]) && + + (x>=r[(i+2)*x_size+j-3]) && + (x>=r[(i+2)*x_size+j-2]) && + (x>=r[(i+2)*x_size+j-1]) && + (x>=r[(i+2)*x_size+j ]) && + (x>=r[(i+2)*x_size+j+1]) && + (x>=r[(i+2)*x_size+j+2]) && + (x>=r[(i+2)*x_size+j+3]) && + + (x>=r[(i+3)*x_size+j-3]) && + (x>=r[(i+3)*x_size+j-2]) && + (x>=r[(i+3)*x_size+j-1]) && + (x>=r[(i+3)*x_size+j ]) && + (x>=r[(i+3)*x_size+j+1]) && + (x>=r[(i+3)*x_size+j+2]) && + (x>=r[(i+3)*x_size+j+3]) ) +#endif +{ +corner_list[n].info=0; +corner_list[n].x=j; +corner_list[n].y=i; +corner_list[n].dx=cgx[i*x_size+j]; +corner_list[n].dy=cgy[i*x_size+j]; +corner_list[n].I=in[i*x_size+j]; +n++; +if(n==MAX_CORNERS){ + fprintf(stderr,"Too many corners.\n"); + exit(1); + }}}} +corner_list[n].info=7; + +free(cgx); +free(cgy); + +} + +/* }}} */ +/* {{{ susan_quick(in,r,sf,max_no,corner_list) */ + +susan_corners_quick(in,r,bp,max_no,corner_list,x_size,y_size) + uchar *in, *bp; + int *r, max_no, x_size, y_size; + CORNER_LIST corner_list; +{ +int n,x,y,i,j; +uchar *p,*cp; + + memset (r,0,x_size * y_size * sizeof(int)); + + for (i=7;i0) { + /* 5x5 mask */ +#ifdef FIVE_SUPP + if ( + (x>r[(i-1)*x_size+j+2]) && + (x>r[(i )*x_size+j+1]) && + (x>r[(i )*x_size+j+2]) && + (x>r[(i+1)*x_size+j-1]) && + (x>r[(i+1)*x_size+j ]) && + (x>r[(i+1)*x_size+j+1]) && + (x>r[(i+1)*x_size+j+2]) && + (x>r[(i+2)*x_size+j-2]) && + (x>r[(i+2)*x_size+j-1]) && + (x>r[(i+2)*x_size+j ]) && + (x>r[(i+2)*x_size+j+1]) && + (x>r[(i+2)*x_size+j+2]) && + (x>=r[(i-2)*x_size+j-2]) && + (x>=r[(i-2)*x_size+j-1]) && + (x>=r[(i-2)*x_size+j ]) && + (x>=r[(i-2)*x_size+j+1]) && + (x>=r[(i-2)*x_size+j+2]) && + (x>=r[(i-1)*x_size+j-2]) && + (x>=r[(i-1)*x_size+j-1]) && + (x>=r[(i-1)*x_size+j ]) && + (x>=r[(i-1)*x_size+j+1]) && + (x>=r[(i )*x_size+j-2]) && + (x>=r[(i )*x_size+j-1]) && + (x>=r[(i+1)*x_size+j-2]) ) +#endif +#ifdef SEVEN_SUPP + if ( + (x>r[(i-3)*x_size+j-3]) && + (x>r[(i-3)*x_size+j-2]) && + (x>r[(i-3)*x_size+j-1]) && + (x>r[(i-3)*x_size+j ]) && + (x>r[(i-3)*x_size+j+1]) && + (x>r[(i-3)*x_size+j+2]) && + (x>r[(i-3)*x_size+j+3]) && + + (x>r[(i-2)*x_size+j-3]) && + (x>r[(i-2)*x_size+j-2]) && + (x>r[(i-2)*x_size+j-1]) && + (x>r[(i-2)*x_size+j ]) && + (x>r[(i-2)*x_size+j+1]) && + (x>r[(i-2)*x_size+j+2]) && + (x>r[(i-2)*x_size+j+3]) && + + (x>r[(i-1)*x_size+j-3]) && + (x>r[(i-1)*x_size+j-2]) && + (x>r[(i-1)*x_size+j-1]) && + (x>r[(i-1)*x_size+j ]) && + (x>r[(i-1)*x_size+j+1]) && + (x>r[(i-1)*x_size+j+2]) && + (x>r[(i-1)*x_size+j+3]) && + + (x>r[(i)*x_size+j-3]) && + (x>r[(i)*x_size+j-2]) && + (x>r[(i)*x_size+j-1]) && + (x>=r[(i)*x_size+j+1]) && + (x>=r[(i)*x_size+j+2]) && + (x>=r[(i)*x_size+j+3]) && + + (x>=r[(i+1)*x_size+j-3]) && + (x>=r[(i+1)*x_size+j-2]) && + (x>=r[(i+1)*x_size+j-1]) && + (x>=r[(i+1)*x_size+j ]) && + (x>=r[(i+1)*x_size+j+1]) && + (x>=r[(i+1)*x_size+j+2]) && + (x>=r[(i+1)*x_size+j+3]) && + + (x>=r[(i+2)*x_size+j-3]) && + (x>=r[(i+2)*x_size+j-2]) && + (x>=r[(i+2)*x_size+j-1]) && + (x>=r[(i+2)*x_size+j ]) && + (x>=r[(i+2)*x_size+j+1]) && + (x>=r[(i+2)*x_size+j+2]) && + (x>=r[(i+2)*x_size+j+3]) && + + (x>=r[(i+3)*x_size+j-3]) && + (x>=r[(i+3)*x_size+j-2]) && + (x>=r[(i+3)*x_size+j-1]) && + (x>=r[(i+3)*x_size+j ]) && + (x>=r[(i+3)*x_size+j+1]) && + (x>=r[(i+3)*x_size+j+2]) && + (x>=r[(i+3)*x_size+j+3]) ) +#endif +{ +corner_list[n].info=0; +corner_list[n].x=j; +corner_list[n].y=i; +x = in[(i-2)*x_size+j-2] + in[(i-2)*x_size+j-1] + in[(i-2)*x_size+j] + in[(i-2)*x_size+j+1] + in[(i-2)*x_size+j+2] + + in[(i-1)*x_size+j-2] + in[(i-1)*x_size+j-1] + in[(i-1)*x_size+j] + in[(i-1)*x_size+j+1] + in[(i-1)*x_size+j+2] + + in[(i )*x_size+j-2] + in[(i )*x_size+j-1] + in[(i )*x_size+j] + in[(i )*x_size+j+1] + in[(i )*x_size+j+2] + + in[(i+1)*x_size+j-2] + in[(i+1)*x_size+j-1] + in[(i+1)*x_size+j] + in[(i+1)*x_size+j+1] + in[(i+1)*x_size+j+2] + + in[(i+2)*x_size+j-2] + in[(i+2)*x_size+j-1] + in[(i+2)*x_size+j] + in[(i+2)*x_size+j+1] + in[(i+2)*x_size+j+2]; + +corner_list[n].I=x/25; +/*corner_list[n].I=in[i*x_size+j];*/ +x = in[(i-2)*x_size+j+2] + in[(i-1)*x_size+j+2] + in[(i)*x_size+j+2] + in[(i+1)*x_size+j+2] + in[(i+2)*x_size+j+2] - + (in[(i-2)*x_size+j-2] + in[(i-1)*x_size+j-2] + in[(i)*x_size+j-2] + in[(i+1)*x_size+j-2] + in[(i+2)*x_size+j-2]); +x += x + in[(i-2)*x_size+j+1] + in[(i-1)*x_size+j+1] + in[(i)*x_size+j+1] + in[(i+1)*x_size+j+1] + in[(i+2)*x_size+j+1] - + (in[(i-2)*x_size+j-1] + in[(i-1)*x_size+j-1] + in[(i)*x_size+j-1] + in[(i+1)*x_size+j-1] + in[(i+2)*x_size+j-1]); + +y = in[(i+2)*x_size+j-2] + in[(i+2)*x_size+j-1] + in[(i+2)*x_size+j] + in[(i+2)*x_size+j+1] + in[(i+2)*x_size+j+2] - + (in[(i-2)*x_size+j-2] + in[(i-2)*x_size+j-1] + in[(i-2)*x_size+j] + in[(i-2)*x_size+j+1] + in[(i-2)*x_size+j+2]); +y += y + in[(i+1)*x_size+j-2] + in[(i+1)*x_size+j-1] + in[(i+1)*x_size+j] + in[(i+1)*x_size+j+1] + in[(i+1)*x_size+j+2] - + (in[(i-1)*x_size+j-2] + in[(i-1)*x_size+j-1] + in[(i-1)*x_size+j] + in[(i-1)*x_size+j+1] + in[(i-1)*x_size+j+2]); +corner_list[n].dx=x/15; +corner_list[n].dy=y/15; +n++; +if(n==MAX_CORNERS){ + fprintf(stderr,"Too many corners.\n"); + exit(1); + }}}} +corner_list[n].info=7; +} + +/* }}} */ + +/* }}} */ +/* {{{ main(argc, argv) */ + +main(argc, argv) + int argc; + char *argv []; +{ +/* {{{ vars */ + +FILE *ofp; +char filename [80], + *tcp; +uchar *in, *bp, *mid; +float dt=4.0; +int *r, + argindex=3, + bt=20, + principle=0, + thin_post_proc=1, + three_by_three=0, + drawing_mode=0, + susan_quick=0, + max_no_corners=1850, + max_no_edges=2650, + mode = 0, i, + x_size, y_size; +CORNER_LIST corner_list; + +/* }}} */ + +char *path_in, *path_out; +path_in = "/Desktop/input_small.pgm"; +path_out = "/Desktop/output_small.pgm"; + + if (argc<3) + usage(); + + get_image(path_in,&in,&x_size,&y_size); + + /* {{{ look at options */ + + while (argindex < argc) + { + tcp = argv[argindex]; + if (*tcp == '-') + switch (*++tcp) + { + case 's': /* smoothing */ + mode=0; + break; + case 'e': /* edges */ + mode=1; + break; + case 'c': /* corners */ + mode=2; + break; + case 'p': /* principle */ + principle=1; + break; + case 'n': /* thinning post processing */ + thin_post_proc=0; + break; + case 'b': /* simple drawing mode */ + drawing_mode=1; + break; + case '3': /* 3x3 flat mask */ + three_by_three=1; + break; + case 'q': /* quick susan mask */ + susan_quick=1; + break; + case 'd': /* distance threshold */ + if (++argindex >= argc){ + printf ("No argument following -d\n"); + exit(0);} + dt=atof(argv[argindex]); + if (dt<0) three_by_three=1; + break; + case 't': /* brightness threshold */ + if (++argindex >= argc){ + printf ("No argument following -t\n"); + exit(0);} + bt=atoi(argv[argindex]); + break; + } + else + usage(); + argindex++; + } + + if ( (principle==1) && (mode==0) ) + mode=1; + +/* }}} */ + /* {{{ main processing */ + + switch (mode) + { + case 0: + /* {{{ smoothing */ + + setup_brightness_lut(&bp,bt,2); + susan_smoothing(three_by_three,in,dt,x_size,y_size,bp); + break; + +/* }}} */ + case 1: + /* {{{ edges */ + + r = (int *) malloc(x_size * y_size * sizeof(int)); + setup_brightness_lut(&bp,bt,6); + + if (principle) + { + if (three_by_three) + susan_principle_small(in,r,bp,max_no_edges,x_size,y_size); + else + susan_principle(in,r,bp,max_no_edges,x_size,y_size); + int_to_uchar(r,in,x_size*y_size); + } + else + { + mid = (uchar *)malloc(x_size*y_size); + memset (mid,100,x_size * y_size); /* note not set to zero */ + + if (three_by_three) + susan_edges_small(in,r,mid,bp,max_no_edges,x_size,y_size); + else + susan_edges(in,r,mid,bp,max_no_edges,x_size,y_size); + if(thin_post_proc) + susan_thin(r,mid,x_size,y_size); + edge_draw(in,mid,x_size,y_size,drawing_mode); + } + + break; + +/* }}} */ + case 2: + /* {{{ corners */ + + r = (int *) malloc(x_size * y_size * sizeof(int)); + setup_brightness_lut(&bp,bt,6); + + if (principle) + { + susan_principle(in,r,bp,max_no_corners,x_size,y_size); + int_to_uchar(r,in,x_size*y_size); + } + else + { + if(susan_quick) + susan_corners_quick(in,r,bp,max_no_corners,corner_list,x_size,y_size); + else + susan_corners(in,r,bp,max_no_corners,corner_list,x_size,y_size); + corner_draw(in,corner_list,x_size,drawing_mode); + } + + break; + +/* }}} */ + } + +/* }}} */ + + put_image(path_out,in,x_size,y_size); +} + +/* }}} */ diff --git a/pdl/riscv/tests/libac_sysc/Makefile b/pdl/riscv/tests/libac_sysc/Makefile new file mode 100644 index 0000000..b6569d2 --- /dev/null +++ b/pdl/riscv/tests/libac_sysc/Makefile @@ -0,0 +1,41 @@ +# Use: make TARGET= +# It looks for the following commands for this target: +CC = riscv64-unknown-elf-gcc +AR = riscv64-unknown-elf-ar +RANLIB = riscv64-unknown-elf-ranlib + +# Flags +CFLAGS = -O2 -g -I. -I.. -m32 -Wa,-march=RV32IM -std=gnu99 -msoft-float +ARFLAGS = cr +RM = rm +RMFLAGS = -rf +TARGET = riscv64-unknown-elf + + +ifneq (,$(findstring arm,$(TARGET))) +CFLAGS+=-DARM +endif + +# Targets +LIBSYSC = libac_sysc.a + +# Sources +LIBSYSC_SOURCES = $(wildcard *.c) + +# Object files +LIBSYSC_OBJECTS = $(patsubst %.c,%.o,$(notdir $(LIBSYSC_SOURCES))) + +# Target rules + +all: $(LIBSYSC) + +%.o: $(LIBSYSC_DIR)/%.c + +$(LIBSYSC): $(LIBSYSC_OBJECTS) + $(AR) $(ARFLAGS) $(LIBSYSC) $(LIBSYSC_OBJECTS) + $(RANLIB) $(LIBSYSC) + -$(RM) $(RMFLAGS) $(LIBSYSC_OBJECTS) + +# Clean +clean: + -$(RM) $(RMFLAGS) $(LIBSYSC) $(LIBSYSC_OBJECTS) diff --git a/pdl/riscv/tests/libac_sysc/README b/pdl/riscv/tests/libac_sysc/README new file mode 100644 index 0000000..826485f --- /dev/null +++ b/pdl/riscv/tests/libac_sysc/README @@ -0,0 +1,28 @@ +Overview +-------- + +The ArchC system calls library (libac_sysc.a) instruments the +aplications to interface virtual calls with real host system calls. + +The GCC cross-compiled to the target architecture must be generated +and added to PATH environment. Compiling the library: + + make TARGET=mips-newlib-elf + +The output file (libac_sysc.a) must be moved to: + +$(CROSS_PATH)/$(CROSS_TUPLE)/lib/ + +Where CROSS_TUPLE could be 'mips-newlib-elf', 'powerpc-newlib-elf', etc. + +How to create/configure a cross-compiler for an ArchC description +----------------------------------------------------------------- + +Unfortunately at this point it is not possible to automatically +generate a cross-compiler back-end from an ArchC description. A GCC +cross-compiler can only be generated for architectures already +supported by GCC. + +Thanks for using ArchC! +The ArchC Team +www.archc.org diff --git a/pdl/riscv/tests/libac_sysc/ac_arm.h b/pdl/riscv/tests/libac_sysc/ac_arm.h new file mode 100644 index 0000000..ea1451b --- /dev/null +++ b/pdl/riscv/tests/libac_sysc/ac_arm.h @@ -0,0 +1,15 @@ +#define open _open +#define close _close +#define read _read +#define write _write +#define isatty _isatty +#define sbrk _sbrk +#define lseek _lseek +#define exit _exit +#define times _times +#define stat _stat +#define kill _kill +#define fstat _fstat +#define __NR__unlink __NR_unlink +#define __NR__getpid __NR_getpid + diff --git a/pdl/riscv/tests/libac_sysc/ac_real_sysc.c b/pdl/riscv/tests/libac_sysc/ac_real_sysc.c new file mode 100644 index 0000000..85c708b --- /dev/null +++ b/pdl/riscv/tests/libac_sysc/ac_real_sysc.c @@ -0,0 +1,44 @@ +/** + * @file ac_real_sysc.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:20 -0300 + * + * @brief + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* some syscalls that trap to simulator functions */ + +#ifdef ARM +#include "ac_arm.h" +#endif + +#define AC_SYSC(NAME,LOCATION) \ +int NAME() { \ + goto *LOCATION; \ +} + +#include "ac_syscall.def" diff --git a/pdl/riscv/tests/libac_sysc/ac_specs b/pdl/riscv/tests/libac_sysc/ac_specs new file mode 100644 index 0000000..bf47e4d --- /dev/null +++ b/pdl/riscv/tests/libac_sysc/ac_specs @@ -0,0 +1,11 @@ +*link: +-Ttext 0x100 + +*startfile: +ac_start.o%s + +*endfile: + + +*lib: +-lc -lac_sysc -lc diff --git a/pdl/riscv/tests/libac_sysc/ac_syscall.def b/pdl/riscv/tests/libac_sysc/ac_syscall.def new file mode 100644 index 0000000..7e03604 --- /dev/null +++ b/pdl/riscv/tests/libac_sysc/ac_syscall.def @@ -0,0 +1,25 @@ +AC_SYSC(ac_forbidden, 0x3c); +AC_SYSC(open, 0x40); +AC_SYSC(creat, 0x44); +AC_SYSC(close, 0x48); +AC_SYSC(read, 0x4c); +AC_SYSC(write, 0x50); +AC_SYSC(isatty, 0x54); +AC_SYSC(sbrk, 0x58); +AC_SYSC(lseek, 0x5c); +AC_SYSC(_exit, 0x64); +AC_SYSC(times, 0x68); +AC_SYSC(time, 0x6c); +AC_SYSC(random, 0x70); +AC_SYSC(ac_syscall_wrapper, 0x74); +AC_SYSC(ac_syscall_geterrno, 0x78); +AC_SYSC(ac_syscall_stat_mode, 0x7c); +AC_SYSC(ac_rtld_init, 0x80); +AC_SYSC(ac_rtld_fini, 0x84); +AC_SYSC(ac_rtld_dummy, 0x88); +AC_SYSC(getcwd, 0x8c); +AC_SYSC(getpagesize,0x90); +AC_SYSC(execve,0x94); +AC_SYSC(fork,0x98); +AC_SYSC(wait,0x9c); + diff --git a/pdl/riscv/tests/libac_sysc/ac_syscall_codes.h b/pdl/riscv/tests/libac_sysc/ac_syscall_codes.h new file mode 100644 index 0000000..12b7fea --- /dev/null +++ b/pdl/riscv/tests/libac_sysc/ac_syscall_codes.h @@ -0,0 +1,319 @@ +/** + * @file ac_syscall_codes.h + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:20 -0300 + * + * @brief This file contains the system call numbers. + * System calls codes copied from include/asm/unistd.h + * at a Linux Red Hat 9 machine + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#ifndef _AC_SYSCALL_CODES_ +#define _AC_SYSCALL_CODES_ + +#define __NR_exit 1 +#define __NR_fork 2 +#define __NR_read 3 +#define __NR_write 4 +#define __NR_open 5 +#define __NR_close 6 +#define __NR_waitpid 7 +#define __NR_creat 8 +#define __NR_link 9 +#define __NR_unlink 10 +#define __NR_execve 11 +#define __NR_chdir 12 +#define __NR_time 13 +#define __NR_mknod 14 +#define __NR_chmod 15 +#define __NR_lchown 16 +#define __NR_break 17 +#define __NR_oldstat 18 +#define __NR_lseek 19 +#define __NR_getpid 20 +#define __NR_mount 21 +#define __NR_umount 22 +#define __NR_setuid 23 +#define __NR_getuid 24 +#define __NR_stime 25 +#define __NR_ptrace 26 +#define __NR_alarm 27 +#define __NR_oldfstat 28 +#define __NR_pause 29 +#define __NR_utime 30 +#define __NR_stty 31 +#define __NR_gtty 32 +#define __NR_access 33 +#define __NR_nice 34 +#define __NR_ftime 35 +#define __NR_sync 36 +#define __NR_kill 37 +#define __NR_rename 38 +#define __NR_mkdir 39 +#define __NR_rmdir 40 +#define __NR_dup 41 +#define __NR_pipe 42 +#define __NR_times 43 +#define __NR_prof 44 +#define __NR_brk 45 +#define __NR_setgid 46 +#define __NR_getgid 47 +#define __NR_signal 48 +#define __NR_geteuid 49 +#define __NR_getegid 50 +#define __NR_acct 51 +#define __NR_umount2 52 +#define __NR_lock 53 +#define __NR_ioctl 54 +#define __NR_fcntl 55 +#define __NR_mpx 56 +#define __NR_setpgid 57 +#define __NR_ulimit 58 +#define __NR_oldolduname 59 +#define __NR_umask 60 +#define __NR_chroot 61 +#define __NR_ustat 62 +#define __NR_dup2 63 +#define __NR_getppid 64 +#define __NR_getpgrp 65 +#define __NR_setsid 66 +#define __NR_sigaction 67 +#define __NR_sgetmask 68 +#define __NR_ssetmask 69 +#define __NR_setreuid 70 +#define __NR_setregid 71 +#define __NR_sigsuspend 72 +#define __NR_sigpending 73 +#define __NR_sethostname 74 +#define __NR_setrlimit 75 +#define __NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */ +#define __NR_getrusage 77 +#define __NR_gettimeofday 78 +#define __NR_settimeofday 79 +#define __NR_getgroups 80 +#define __NR_setgroups 81 +#define __NR_select 82 +#define __NR_symlink 83 +#define __NR_oldlstat 84 +#define __NR_readlink 85 +#define __NR_uselib 86 +#define __NR_swapon 87 +#define __NR_reboot 88 +#define __NR_readdir 89 +#define __NR_mmap 90 +#define __NR_munmap 91 +#define __NR_truncate 92 +#define __NR_ftruncate 93 +#define __NR_fchmod 94 +#define __NR_fchown 95 +#define __NR_getpriority 96 +#define __NR_setpriority 97 +#define __NR_profil 98 +#define __NR_statfs 99 +#define __NR_fstatfs 100 +#define __NR_ioperm 101 +#define __NR_socketcall 102 +#define __NR_syslog 103 +#define __NR_setitimer 104 +#define __NR_getitimer 105 +#define __NR_stat 106 +#define __NR_lstat 107 +#define __NR_fstat 108 +#define __NR_olduname 109 +#define __NR_iopl 110 +#define __NR_vhangup 111 +#define __NR_idle 112 +#define __NR_vm86old 113 +#define __NR_wait4 114 +#define __NR_swapoff 115 +#define __NR_sysinfo 116 +#define __NR_ipc 117 +#define __NR_fsync 118 +#define __NR_sigreturn 119 +#define __NR_clone 120 +#define __NR_setdomainname 121 +#define __NR_uname 122 +#define __NR_modify_ldt 123 +#define __NR_adjtimex 124 +#define __NR_mprotect 125 +#define __NR_sigprocmask 126 +#define __NR_create_module 127 +#define __NR_init_module 128 +#define __NR_delete_module 129 +#define __NR_get_kernel_syms 130 +#define __NR_quotactl 131 +#define __NR_getpgid 132 +#define __NR_fchdir 133 +#define __NR_bdflush 134 +#define __NR_sysfs 135 +#define __NR_personality 136 +#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ +#define __NR_setfsuid 138 +#define __NR_setfsgid 139 +#define __NR__llseek 140 +#define __NR_getdents 141 +#define __NR__newselect 142 +#define __NR_flock 143 +#define __NR_msync 144 +#define __NR_readv 145 +#define __NR_writev 146 +#define __NR_getsid 147 +#define __NR_fdatasync 148 +#define __NR__sysctl 149 +#define __NR_mlock 150 +#define __NR_munlock 151 +#define __NR_mlockall 152 +#define __NR_munlockall 153 +#define __NR_sched_setparam 154 +#define __NR_sched_getparam 155 +#define __NR_sched_setscheduler 156 +#define __NR_sched_getscheduler 157 +#define __NR_sched_yield 158 +#define __NR_sched_get_priority_max 159 +#define __NR_sched_get_priority_min 160 +#define __NR_sched_rr_get_interval 161 +#define __NR_nanosleep 162 +#define __NR_mremap 163 +#define __NR_setresuid 164 +#define __NR_getresuid 165 +#define __NR_vm86 166 +#define __NR_query_module 167 +#define __NR_poll 168 +#define __NR_nfsservctl 169 +#define __NR_setresgid 170 +#define __NR_getresgid 171 +#define __NR_prctl 172 +#define __NR_rt_sigreturn 173 +#define __NR_rt_sigaction 174 +#define __NR_rt_sigprocmask 175 +#define __NR_rt_sigpending 176 +#define __NR_rt_sigtimedwait 177 +#define __NR_rt_sigqueueinfo 178 +#define __NR_rt_sigsuspend 179 +#define __NR_pread 180 +#define __NR_pwrite 181 +#define __NR_chown 182 +#define __NR_getcwd 183 +#define __NR_capget 184 +#define __NR_capset 185 +#define __NR_sigaltstack 186 +#define __NR_sendfile 187 +#define __NR_getpmsg 188 /* some people actually want streams */ +#define __NR_putpmsg 189 /* some people actually want streams */ +#define __NR_vfork 190 +#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ +#define __NR_mmap2 192 +#define __NR_truncate64 193 +#define __NR_ftruncate64 194 +#define __NR_stat64 195 +#define __NR_lstat64 196 +#define __NR_fstat64 197 +#define __NR_lchown32 198 +#define __NR_getuid32 199 +#define __NR_getgid32 200 +#define __NR_geteuid32 201 +#define __NR_getegid32 202 +#define __NR_setreuid32 203 +#define __NR_setregid32 204 +#define __NR_getgroups32 205 +#define __NR_setgroups32 206 +#define __NR_fchown32 207 +#define __NR_setresuid32 208 +#define __NR_getresuid32 209 +#define __NR_setresgid32 210 +#define __NR_getresgid32 211 +#define __NR_chown32 212 +#define __NR_setuid32 213 +#define __NR_setgid32 214 +#define __NR_setfsuid32 215 +#define __NR_setfsgid32 216 +#define __NR_pivot_root 217 +#define __NR_mincore 218 +#define __NR_madvise 219 +#define __NR_madvise1 219 /* delete when C lib stub is removed */ +#define __NR_getdents64 220 +#define __NR_fcntl64 221 +#define __NR_security 223 /* syscall for security modules */ +#define __NR_gettid 224 +#define __NR_readahead 225 +#define __NR_setxattr 226 +#define __NR_lsetxattr 227 +#define __NR_fsetxattr 228 +#define __NR_getxattr 229 +#define __NR_lgetxattr 230 +#define __NR_fgetxattr 231 +#define __NR_listxattr 232 +#define __NR_llistxattr 233 +#define __NR_flistxattr 234 +#define __NR_removexattr 235 +#define __NR_lremovexattr 236 +#define __NR_fremovexattr 237 +#define __NR_tkill 238 +#define __NR_sendfile64 239 +#define __NR_futex 240 +#define __NR_sched_setaffinity 241 +#define __NR_sched_getaffinity 242 +#define __NR_set_thread_area 243 +#define __NR_get_thread_area 244 +/* #define __NR_io_setup 245 */ +/* #define __NR_io_destroy 246 */ +/* #define __NR_io_getevents 247 */ +/* #define __NR_io_submit 248 */ +/* #define __NR_io_cancel 249 */ +/* #define __NR_alloc_hugepages 250 */ +/* #define __NR_free_hugepages 251 */ +#define __NR_exit_group 252 +/* #define __NR_lookup_dcookie 253 */ +/* #define __NR_sys_epoll_create 254 */ +/* #define __NR_sys_epoll_ctl 255 */ +/* #define __NR_sys_epoll_wait 256 */ +/* #define __NR_remap_file_pages 257 */ +#define __NR_set_tid_address 258 + + +/* + * Special definitions for compatibility glibc->newlib + */ + +#define __AC_BASE (1<<16) + +#define __AC_struct_stat_st_dev __AC_BASE + 0 +#define __AC_struct_stat_st_ino __AC_BASE + 1 +#define __AC_struct_stat_st_mode __AC_BASE + 2 +#define __AC_struct_stat_st_nlink __AC_BASE + 3 +#define __AC_struct_stat_st_uid __AC_BASE + 4 +#define __AC_struct_stat_st_gid __AC_BASE + 5 +#define __AC_struct_stat_st_rdev __AC_BASE + 6 +#define __AC_struct_stat_st_size __AC_BASE + 7 +#define __AC_struct_stat_st_blksize __AC_BASE + 8 +#define __AC_struct_stat_st_blocks __AC_BASE + 9 +#define __AC_struct_stat_st_atime __AC_BASE + 10 +#define __AC_struct_stat_st_mtime __AC_BASE + 11 +#define __AC_struct_stat_st_ctime __AC_BASE + 12 + + +#endif /* _AC_SYSCALL_CODES_ */ diff --git a/pdl/riscv/tests/libac_sysc/ac_syscall_wrapper.c b/pdl/riscv/tests/libac_sysc/ac_syscall_wrapper.c new file mode 100644 index 0000000..e26e68b --- /dev/null +++ b/pdl/riscv/tests/libac_sysc/ac_syscall_wrapper.c @@ -0,0 +1,111 @@ +/** + * @file ac_syscall_wrapper.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:20 -0300 + * + * @brief + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include +#include + +#include +#include +#include + +#ifdef ARM +#define unlink _unlink +#define getpid _getpid +#endif + + +_syscall2(int,link,const char *,oldpath,const char *,newpath) +_syscall1(int,unlink,const char*,pathname) + +_syscall2(int,chmod,const char *,path,mode_t,mode); +_syscall2(int,fchmod,int,fildes,mode_t,mode); + +_syscall3(int,chown,const char *,path,uid_t,owner,gid_t,group); +_syscall3(int,fchown,int,fd,uid_t,owner,gid_t,group); +_syscall3(int,lchown,const char *,path,uid_t,owner,gid_t,group); + +_syscall0(pid_t,getpid); +_syscall0(pid_t,getppid); + +_syscall1(int,dup,int,oldfd) +_syscall2(int,dup2,int,oldfd,int,newfd) + + +/* Specially handled syscalls */ + +/* _syscall2(int,stat,const char *,file_name,struct stat *,buf); */ +/* _syscall2(int,fstat,int, filedes,struct stat *,buf); */ +/* _syscall2(int,lstat,const char *,file_name,struct stat *,buf); */ + +#include + +#ifdef ARM +int _fstat(int filedes, struct stat *buf) { + return (fstat(filedes,buf)); +} +#endif + +int fstat(int filedes, struct stat *buf) +{ + int res = ac_syscall_wrapper(__NR_fstat,filedes,buf); + if (res == -1) { + errno = ac_syscall_geterrno(); + } + else { + buf->st_dev = ac_syscall_wrapper(__AC_struct_stat_st_dev); + buf->st_ino = ac_syscall_wrapper(__AC_struct_stat_st_ino); + buf->st_mode = ac_syscall_wrapper(__AC_struct_stat_st_mode); + buf->st_nlink = ac_syscall_wrapper(__AC_struct_stat_st_nlink); + buf->st_uid = ac_syscall_wrapper(__AC_struct_stat_st_uid); + buf->st_gid = ac_syscall_wrapper(__AC_struct_stat_st_gid); + buf->st_rdev = ac_syscall_wrapper(__AC_struct_stat_st_rdev); + buf->st_size = ac_syscall_wrapper(__AC_struct_stat_st_size); + buf->st_blksize = ac_syscall_wrapper(__AC_struct_stat_st_blksize); + buf->st_blocks = ac_syscall_wrapper(__AC_struct_stat_st_blocks); + buf->st_atime = ac_syscall_wrapper(__AC_struct_stat_st_atime); + buf->st_mtime = ac_syscall_wrapper(__AC_struct_stat_st_mtime); + buf->st_ctime = ac_syscall_wrapper(__AC_struct_stat_st_ctime); + } + return res; +} + +#include + +int utime (const char *filename, const struct utimbuf *times) +{ + return 0; +} + +void abort (void) +{ + _exit(1); +} diff --git a/pdl/riscv/tests/libac_sysc/ac_syscall_wrapper.h b/pdl/riscv/tests/libac_sysc/ac_syscall_wrapper.h new file mode 100644 index 0000000..76ac636 --- /dev/null +++ b/pdl/riscv/tests/libac_sysc/ac_syscall_wrapper.h @@ -0,0 +1,104 @@ +/** + * @file ac_syscall_wrapper.h + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:20 -0300 + * + * @brief + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#ifndef _AC_SYSCALL_WRAPPER_H_ +#define _AC_SYSCALL_WRAPPER_H_ + +#include + + + +#define __syscall_return(type, res) \ +do { \ + if ((int)(res) == -1) errno = ac_syscall_geterrno(); \ + return (type) (res); \ +} while (0) + + +#define _syscall0(type,name) \ +type name(void) \ +{ \ +long __res; \ +__res = ac_syscall_wrapper(__NR_##name); \ +__syscall_return(type,__res); \ +} + +#define _syscall1(type,name,type1,arg1) \ +type name(type1 arg1) \ +{ \ +long __res; \ +__res = ac_syscall_wrapper(__NR_##name,arg1); \ +__syscall_return(type,__res); \ +} + +#define _syscall2(type,name,type1,arg1,type2,arg2) \ +type name(type1 arg1, type2 arg2) \ +{ \ +long __res; \ +__res = ac_syscall_wrapper(__NR_##name,arg1,arg2); \ +__syscall_return(type,__res); \ +} + +#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ +type name(type1 arg1, type2 arg2, type3 arg3) \ +{ \ +long __res; \ +__res = ac_syscall_wrapper(__NR_##name,arg1,arg2,arg3); \ +__syscall_return(type,__res); \ +} + +#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ +type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ +{ \ +long __res; \ +__res = ac_syscall_wrapper(__NR_##name,arg1,arg2,arg3,arg4); \ +__syscall_return(type,__res); \ +} + +#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \ +type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \ +{ \ +long __res; \ +__res = ac_syscall_wrapper(__NR_##name,arg1,arg2,arg3,arg4,arg5); \ +__syscall_return(type,__res); \ +} + +#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5,type6,arg6) \ +type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6) \ +{ \ +long __res; \ +__res = ac_syscall_wrapper(__NR_##name,arg1,arg2,arg3,arg4,arg5,arg6); \ +__syscall_return(type,__res); \ +} + + +#endif /* _AC_SYSCALL_WRAPPER_H_ */ diff --git a/pdl/riscv/tests/libac_sysc/alarm.c b/pdl/riscv/tests/libac_sysc/alarm.c new file mode 100644 index 0000000..000117d --- /dev/null +++ b/pdl/riscv/tests/libac_sysc/alarm.c @@ -0,0 +1,39 @@ +/** + * @file alarm.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:20 -0300 + * + * @brief + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * @note There is no support for signals yet. We just return + * "no previously scheduled alarm" + */ + +int +alarm(unsigned int seconds) +{ + return 0; +} diff --git a/pdl/riscv/tests/libac_sysc/chmod.c b/pdl/riscv/tests/libac_sysc/chmod.c new file mode 100644 index 0000000..e6fbde4 --- /dev/null +++ b/pdl/riscv/tests/libac_sysc/chmod.c @@ -0,0 +1,45 @@ +/** + * @file chmod.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:20 -0300 + * + * @brief + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * @note chmod and fchmod not implemented yet + */ + +#include +#include + +int chmod(const char *path, mode_t mode) +{ + return 0; +} + +int fchmod(int fildes, mode_t mode) +{ + return 0; +} diff --git a/pdl/riscv/tests/libac_sysc/gettod.c b/pdl/riscv/tests/libac_sysc/gettod.c new file mode 100644 index 0000000..de6863d --- /dev/null +++ b/pdl/riscv/tests/libac_sysc/gettod.c @@ -0,0 +1,46 @@ +/** + * @file gettod.c + * @author Marcus Bartholomeu + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:20 -0300 + * + * @brief Weak version of gettimeofday function (based in time()). + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include +#include + +//int +//gettimeofday( struct timeval *ptimeval, +// struct timezone *ptimezone) +//{ +// int t = time(0); +// ptimeval->tv_sec = t; +// ptimeval->tv_usec = 0; +// return 0; +//} diff --git a/pdl/riscv/tests/libac_sysc/kill.c b/pdl/riscv/tests/libac_sysc/kill.c new file mode 100644 index 0000000..21831a2 --- /dev/null +++ b/pdl/riscv/tests/libac_sysc/kill.c @@ -0,0 +1,45 @@ +/** + * @file kill.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:20 -0300 + * + * @brief + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * @note The kill isn't implemented yet; go out via exit if self + * + */ + +#ifdef ARM +#define kill _kill +#endif + +int +kill(int pid, int sig) +{ + if(pid == 1) + _exit(sig); + return 0; +} diff --git a/pdl/riscv/tests/libac_sysc/stat.c b/pdl/riscv/tests/libac_sysc/stat.c new file mode 100644 index 0000000..6b6a01d --- /dev/null +++ b/pdl/riscv/tests/libac_sysc/stat.c @@ -0,0 +1,62 @@ +/** + * @file stat.c + * @author The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br/ + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:20 -0300 + * + * @brief + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#ifdef ARM +#define stat _stat +#endif + +#include +#include +#include + +#include +#include +#include + +int stat(const char *path, struct stat *buf) +{ + int res = ac_syscall_wrapper(__NR_stat,path,buf); +// if (!mode) { +// errno = ac_syscall_geterrno(); +// return -1; +// } +// else { +// //correct values: +// buf->st_mode = mode; +// //dummy values: +// buf->st_size = 1; +// buf->st_uid = 1; +// buf->st_gid = 1; +// return 0; +// } + return res; +} diff --git a/pdl/riscv/tests/rv_hal/crt.S b/pdl/riscv/tests/rv_hal/crt.S new file mode 100644 index 0000000..ac5cfe0 --- /dev/null +++ b/pdl/riscv/tests/rv_hal/crt.S @@ -0,0 +1,40 @@ +/************************************************* +************************************************** +* @file crt.S +* @author Dário Dias +* @email dsd@cin.ufpe.br +* @version 0.20 +* @date 9 July 2016 +* @brief The ArchC Risc-V functional model. +************************************************** +*************************************************/ + +#include "encoding.h" + +#define STACK_SIZE 524288 + +//512kB for each core + + .text + .globl _start + +_start: + lui sp,0x500 +// csrr t0,mhartid +// li t1, STACK_SIZE +// mul t2,t1,t0 +// sub sp,sp,t2 + jal main + sbreak + +//_interrupt_handler: +// jal main +// sbreak + +.bss +.align 8 +.skip 4096 +kstacktop: + +.section .tbss +tls_start: diff --git a/pdl/riscv/tests/rv_hal/encoding.h b/pdl/riscv/tests/rv_hal/encoding.h new file mode 100644 index 0000000..1fcfaea --- /dev/null +++ b/pdl/riscv/tests/rv_hal/encoding.h @@ -0,0 +1,927 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_IE 0x00000001 +#define MSTATUS_PRV 0x00000006 +#define MSTATUS_IE1 0x00000008 +#define MSTATUS_PRV1 0x00000030 +#define MSTATUS_IE2 0x00000040 +#define MSTATUS_PRV2 0x00000180 +#define MSTATUS_IE3 0x00000200 +#define MSTATUS_PRV3 0x00000C00 +#define MSTATUS_FS 0x00003000 +#define MSTATUS_XS 0x0000C000 +#define MSTATUS_MPRV 0x00010000 +#define MSTATUS_VM 0x003E0000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_IE 0x00000001 +#define SSTATUS_PIE 0x00000008 +#define SSTATUS_PS 0x00000010 +#define SSTATUS_FS 0x00003000 +#define SSTATUS_XS 0x0000C000 +#define SSTATUS_MPRV 0x00010000 +#define SSTATUS_TIE 0x01000000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define MIP_SSIP 0x00000002 +#define MIP_HSIP 0x00000004 +#define MIP_MSIP 0x00000008 +#define MIP_STIP 0x00000020 +#define MIP_HTIP 0x00000040 +#define MIP_MTIP 0x00000080 + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define UA_RV32 0 +#define UA_RV64 4 +#define UA_RV128 8 + +#define IRQ_SOFT 0 +#define IRQ_TIMER 1 +#define IRQ_HOST 2 +#define IRQ_COP 3 + +#define IMPL_ROCKET 1 + +#define DEFAULT_MTVEC 0x100 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_TYPE 0x01E // Type +#define PTE_R 0x020 // Referenced +#define PTE_D 0x040 // Dirty +#define PTE_SOFT 0x380 // Reserved for Software + +#define PTE_TYPE_TABLE 0x00 +#define PTE_TYPE_TABLE_GLOBAL 0x02 +#define PTE_TYPE_URX_SR 0x04 +#define PTE_TYPE_URWX_SRW 0x06 +#define PTE_TYPE_UR_SR 0x08 +#define PTE_TYPE_URW_SRW 0x0A +#define PTE_TYPE_URX_SRX 0x0C +#define PTE_TYPE_URWX_SRWX 0x0E +#define PTE_TYPE_SR 0x10 +#define PTE_TYPE_SRW 0x12 +#define PTE_TYPE_SRX 0x14 +#define PTE_TYPE_SRWX 0x16 +#define PTE_TYPE_SR_GLOBAL 0x18 +#define PTE_TYPE_SRW_GLOBAL 0x1A +#define PTE_TYPE_SRX_GLOBAL 0x1C +#define PTE_TYPE_SRWX_GLOBAL 0x1E + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1) +#define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1) +#define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1) +#define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1) +#define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1) +#define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1) +#define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1) + +#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \ + ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \ + (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \ + ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) + +#ifdef __riscv + +#ifdef __riscv64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)) + +#define swap_csr(reg, val) ({ long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_C_ADD 0x6000 +#define MASK_C_ADD 0xf003 +#define MATCH_C_ADDI 0x8000 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_ADDI4 0xa000 +#define MASK_C_ADDI4 0xe003 +#define MATCH_C_ADDIW 0xe000 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_ADDW 0x7000 +#define MASK_C_ADDW 0xf003 +#define MATCH_C_BEQZ 0x2002 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0x6002 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_J 0xa002 +#define MASK_C_J 0xe003 +#define MATCH_C_JALR 0x5000 +#define MASK_C_JALR 0xf003 +#define MATCH_C_LD 0x2001 +#define MASK_C_LD 0xe003 +#define MATCH_C_LDSP 0xc001 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_LI 0x0 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x2000 +#define MASK_C_LUI 0xe003 +#define MATCH_C_LW 0x1 +#define MASK_C_LW 0xe003 +#define MATCH_C_LWSP 0x8001 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_MV 0x4000 +#define MASK_C_MV 0xf003 +#define MATCH_C_SD 0x6001 +#define MASK_C_SD 0xe003 +#define MATCH_C_SDSP 0xe001 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_SLLI 0xc000 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_SW 0x4001 +#define MASK_C_SW 0xe003 +#define MATCH_C_SWSP 0xa001 +#define MASK_C_SWSP 0xe003 +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_HRTS 0x20500073 +#define MASK_HRTS 0xffffffff +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_MRTH 0x30600073 +#define MASK_MRTH 0xffffffff +#define MATCH_MRTS 0x30500073 +#define MASK_MRTS 0xffffffff +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SBREAK 0x100073 +#define MASK_SBREAK 0xffffffff +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_SCALL 0x73 +#define MASK_SCALL 0xffffffff +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_SFENCE_VM 0x10100073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_SRET 0x10000073 +#define MASK_SRET 0xffffffff +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_WFI 0x10200073 +#define MASK_WFI 0xffffffff +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_STATS 0xc0 +#define CSR_UARCH0 0xcc0 +#define CSR_UARCH1 0xcc1 +#define CSR_UARCH2 0xcc2 +#define CSR_UARCH3 0xcc3 +#define CSR_UARCH4 0xcc4 +#define CSR_UARCH5 0xcc5 +#define CSR_UARCH6 0xcc6 +#define CSR_UARCH7 0xcc7 +#define CSR_UARCH8 0xcc8 +#define CSR_UARCH9 0xcc9 +#define CSR_UARCH10 0xcca +#define CSR_UARCH11 0xccb +#define CSR_UARCH12 0xccc +#define CSR_UARCH13 0xccd +#define CSR_UARCH14 0xcce +#define CSR_UARCH15 0xccf +#define CSR_SSTATUS 0x100 +#define CSR_STVEC 0x101 +#define CSR_SIE 0x104 +#define CSR_STIMECMP 0x121 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_SASID 0x181 +#define CSR_CYCLEW 0x900 +#define CSR_TIMEW 0x901 +#define CSR_INSTRETW 0x902 +#define CSR_STIME 0xd01 +#define CSR_SCAUSE 0xd42 +#define CSR_SBADADDR 0xd43 +#define CSR_STIMEW 0xa01 +#define CSR_MSTATUS 0x300 +#define CSR_MTVEC 0x301 +#define CSR_MTDELEG 0x302 +#define CSR_MIE 0x304 +#define CSR_MTIMECMP 0x321 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_MTIME 0x701 +#define CSR_MCPUID 0xf00 +#define CSR_MIMPID 0xf01 +#define CSR_MHARTID 0xf10 +#define CSR_MTOHOST 0x780 +#define CSR_MFROMHOST 0x781 +#define CSR_MRESET 0x782 +#define CSR_SEND_IPI 0x783 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_CYCLEHW 0x980 +#define CSR_TIMEHW 0x981 +#define CSR_INSTRETHW 0x982 +#define CSR_STIMEH 0xd81 +#define CSR_STIMEHW 0xa81 +#define CSR_MTIMEH 0x741 +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_addi4, MATCH_C_ADDI4, MASK_C_ADDI4) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(hrts, MATCH_HRTS, MASK_HRTS) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(mrth, MATCH_MRTH, MASK_MRTH) +DECLARE_INSN(mrts, MATCH_MRTS, MASK_MRTS) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(stats, CSR_STATS) +DECLARE_CSR(uarch0, CSR_UARCH0) +DECLARE_CSR(uarch1, CSR_UARCH1) +DECLARE_CSR(uarch2, CSR_UARCH2) +DECLARE_CSR(uarch3, CSR_UARCH3) +DECLARE_CSR(uarch4, CSR_UARCH4) +DECLARE_CSR(uarch5, CSR_UARCH5) +DECLARE_CSR(uarch6, CSR_UARCH6) +DECLARE_CSR(uarch7, CSR_UARCH7) +DECLARE_CSR(uarch8, CSR_UARCH8) +DECLARE_CSR(uarch9, CSR_UARCH9) +DECLARE_CSR(uarch10, CSR_UARCH10) +DECLARE_CSR(uarch11, CSR_UARCH11) +DECLARE_CSR(uarch12, CSR_UARCH12) +DECLARE_CSR(uarch13, CSR_UARCH13) +DECLARE_CSR(uarch14, CSR_UARCH14) +DECLARE_CSR(uarch15, CSR_UARCH15) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stimecmp, CSR_STIMECMP) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(sasid, CSR_SASID) +DECLARE_CSR(cyclew, CSR_CYCLEW) +DECLARE_CSR(timew, CSR_TIMEW) +DECLARE_CSR(instretw, CSR_INSTRETW) +DECLARE_CSR(stime, CSR_STIME) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(stimew, CSR_STIMEW) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mtdeleg, CSR_MTDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtimecmp, CSR_MTIMECMP) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(mtime, CSR_MTIME) +DECLARE_CSR(mcpuid, CSR_MCPUID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(mtohost, CSR_MTOHOST) +DECLARE_CSR(mfromhost, CSR_MFROMHOST) +DECLARE_CSR(mreset, CSR_MRESET) +DECLARE_CSR(send_ipi, CSR_SEND_IPI) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(cyclehw, CSR_CYCLEHW) +DECLARE_CSR(timehw, CSR_TIMEHW) +DECLARE_CSR(instrethw, CSR_INSTRETHW) +DECLARE_CSR(stimeh, CSR_STIMEH) +DECLARE_CSR(stimehw, CSR_STIMEHW) +DECLARE_CSR(mtimeh, CSR_MTIMEH) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("fflags", CAUSE_FFLAGS) +DECLARE_CAUSE("frm", CAUSE_FRM) +DECLARE_CAUSE("fcsr", CAUSE_FCSR) +DECLARE_CAUSE("cycle", CAUSE_CYCLE) +DECLARE_CAUSE("time", CAUSE_TIME) +DECLARE_CAUSE("instret", CAUSE_INSTRET) +DECLARE_CAUSE("stats", CAUSE_STATS) +DECLARE_CAUSE("uarch0", CAUSE_UARCH0) +DECLARE_CAUSE("uarch1", CAUSE_UARCH1) +DECLARE_CAUSE("uarch2", CAUSE_UARCH2) +DECLARE_CAUSE("uarch3", CAUSE_UARCH3) +DECLARE_CAUSE("uarch4", CAUSE_UARCH4) +DECLARE_CAUSE("uarch5", CAUSE_UARCH5) +DECLARE_CAUSE("uarch6", CAUSE_UARCH6) +DECLARE_CAUSE("uarch7", CAUSE_UARCH7) +DECLARE_CAUSE("uarch8", CAUSE_UARCH8) +DECLARE_CAUSE("uarch9", CAUSE_UARCH9) +DECLARE_CAUSE("uarch10", CAUSE_UARCH10) +DECLARE_CAUSE("uarch11", CAUSE_UARCH11) +DECLARE_CAUSE("uarch12", CAUSE_UARCH12) +DECLARE_CAUSE("uarch13", CAUSE_UARCH13) +DECLARE_CAUSE("uarch14", CAUSE_UARCH14) +DECLARE_CAUSE("uarch15", CAUSE_UARCH15) +DECLARE_CAUSE("sstatus", CAUSE_SSTATUS) +DECLARE_CAUSE("stvec", CAUSE_STVEC) +DECLARE_CAUSE("sie", CAUSE_SIE) +DECLARE_CAUSE("stimecmp", CAUSE_STIMECMP) +DECLARE_CAUSE("sscratch", CAUSE_SSCRATCH) +DECLARE_CAUSE("sepc", CAUSE_SEPC) +DECLARE_CAUSE("sip", CAUSE_SIP) +DECLARE_CAUSE("sptbr", CAUSE_SPTBR) +DECLARE_CAUSE("sasid", CAUSE_SASID) +DECLARE_CAUSE("cyclew", CAUSE_CYCLEW) +DECLARE_CAUSE("timew", CAUSE_TIMEW) +DECLARE_CAUSE("instretw", CAUSE_INSTRETW) +DECLARE_CAUSE("stime", CAUSE_STIME) +DECLARE_CAUSE("scause", CAUSE_SCAUSE) +DECLARE_CAUSE("sbadaddr", CAUSE_SBADADDR) +DECLARE_CAUSE("stimew", CAUSE_STIMEW) +DECLARE_CAUSE("mstatus", CAUSE_MSTATUS) +DECLARE_CAUSE("mtvec", CAUSE_MTVEC) +DECLARE_CAUSE("mtdeleg", CAUSE_MTDELEG) +DECLARE_CAUSE("mie", CAUSE_MIE) +DECLARE_CAUSE("mtimecmp", CAUSE_MTIMECMP) +DECLARE_CAUSE("mscratch", CAUSE_MSCRATCH) +DECLARE_CAUSE("mepc", CAUSE_MEPC) +DECLARE_CAUSE("mcause", CAUSE_MCAUSE) +DECLARE_CAUSE("mbadaddr", CAUSE_MBADADDR) +DECLARE_CAUSE("mip", CAUSE_MIP) +DECLARE_CAUSE("mtime", CAUSE_MTIME) +DECLARE_CAUSE("mcpuid", CAUSE_MCPUID) +DECLARE_CAUSE("mimpid", CAUSE_MIMPID) +DECLARE_CAUSE("mhartid", CAUSE_MHARTID) +DECLARE_CAUSE("mtohost", CAUSE_MTOHOST) +DECLARE_CAUSE("mfromhost", CAUSE_MFROMHOST) +DECLARE_CAUSE("mreset", CAUSE_MRESET) +DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI) +DECLARE_CAUSE("cycleh", CAUSE_CYCLEH) +DECLARE_CAUSE("timeh", CAUSE_TIMEH) +DECLARE_CAUSE("instreth", CAUSE_INSTRETH) +DECLARE_CAUSE("cyclehw", CAUSE_CYCLEHW) +DECLARE_CAUSE("timehw", CAUSE_TIMEHW) +DECLARE_CAUSE("instrethw", CAUSE_INSTRETHW) +DECLARE_CAUSE("stimeh", CAUSE_STIMEH) +DECLARE_CAUSE("stimehw", CAUSE_STIMEHW) +DECLARE_CAUSE("mtimeh", CAUSE_MTIMEH) +#endif diff --git a/pdl/riscv/tests/rv_hal/get_id.S b/pdl/riscv/tests/rv_hal/get_id.S new file mode 100644 index 0000000..69817c4 --- /dev/null +++ b/pdl/riscv/tests/rv_hal/get_id.S @@ -0,0 +1,7 @@ +#define return a0 + +.global get_id + +get_id: + csrr return, mhartid + ret diff --git a/pdl/riscv/tests/rv_hal/get_id.h b/pdl/riscv/tests/rv_hal/get_id.h new file mode 100644 index 0000000..c0a43c0 --- /dev/null +++ b/pdl/riscv/tests/rv_hal/get_id.h @@ -0,0 +1,12 @@ +/************************************************* +************************************************** +* @file get_id.h +* @author Dário Dias +* @email dsd@cin.ufpe.br +* @version 0.20 +* @date 9 July 2016 +* @brief The ArchC Risc-V functional model. +************************************************** +*************************************************/ + +int get_id(); diff --git a/pdl/riscv/tests/rv_hal/test.ld b/pdl/riscv/tests/rv_hal/test.ld new file mode 100644 index 0000000..cee0f46 --- /dev/null +++ b/pdl/riscv/tests/rv_hal/test.ld @@ -0,0 +1,72 @@ +/************************************************* +************************************************** +* @file test.ld +* @author Dário Dias +* @email dsd@cin.ufpe.br +* @version 0.20 +* @date 9 July 2016 +* @brief The ArchC Risc-V functional model. +************************************************** +*************************************************/ + +/*======================================================================*/ +/* Proxy kernel linker script */ +/*======================================================================*/ +/* This is the linker script used when building the proxy kernel. */ + +/*----------------------------------------------------------------------*/ +/* Setup */ +/*----------------------------------------------------------------------*/ + +/* The OUTPUT_ARCH command specifies the machine architecture where the + argument is one of the names used in the BFD library. More + specifically one of the entires in bfd/cpu-mips.c */ + +OUTPUT_ARCH( "riscv" ) + +/* The ENTRY command specifies the entry point (ie. first instruction + to execute). The symbol _start should be defined in each test. */ + +ENTRY( _start ) + +/*----------------------------------------------------------------------*/ +/* Sections */ +/*----------------------------------------------------------------------*/ +_RAM_SIZE = 2M; +_RAM_START = 0x0000; +_RAM_END = _RAM_START + _RAM_SIZE; +SECTIONS +{ + + +. = 0x100; + .text : + { + crt.o(.text) + *(.text) + } + + . = 0x20100; + /* data segmemt */ + .data : { *(.data) } + .sdata : { *(.sdata) } + .rodata : { *(.rodata) } + .sbss : { *(.sbss) } + .bss : { *(.bss) } + +/* text: test code section */ + + /* thread-local data segment */ + .tbss : { + crt.o(.tbss) /* Make sure tls_start is the first TLS symbol */ + *(.tbss) + } + .tdata : { *(.tdata) } + /* End of uninitalized data segement */ + + + + _end = .; + +} + diff --git a/pdl/sparc/.gitignore b/pdl/sparc/.gitignore new file mode 100644 index 0000000..674f0e4 --- /dev/null +++ b/pdl/sparc/.gitignore @@ -0,0 +1,24 @@ +Makefile +Makefile.archc +main.cpp +main.cpp.tmpl +*.o +*.a +*.x +sparc.H +sparc.cpp +sparc.x +sparc_arch.H +sparc_arch.cpp +sparc_arch_ref.H +sparc_arch_ref.cpp +sparc_bhv_macros.H +sparc_isa.H +sparc_isa.cpp.tmpl +sparc_isa_init.cpp +sparc_parms.H +sparc_syscall.H.tmpl +sparc_syscall.cpp.tmpl +sparc_ih_bhv_macros.H +sparc_intr_handlers.H +sparc_intr_handlers.cpp* diff --git a/pdl/sparc/CONTRIBUTING.md b/pdl/sparc/CONTRIBUTING.md new file mode 100644 index 0000000..aa6a32a --- /dev/null +++ b/pdl/sparc/CONTRIBUTING.md @@ -0,0 +1,12 @@ +# Contributing + +## Submitting a Pull Request + +1. Fork it. +2. Create a branch (`git checkout -b my_project`) +3. Commit your changes (`git commit -a`) [Tips for better commit message](https://robots.thoughtbot.com/5-useful-tips-for-a-better-commit-message) +4. Push to the branch (`git push origin my_project`) +5. Open a [Pull Request][1] +6. Enjoy a refreshing Diet Coke and wait doing more + +[1]: https://github.com/ArchC/sparc/pulls diff --git a/pdl/sparc/COPYING b/pdl/sparc/COPYING new file mode 100644 index 0000000..d445e88 --- /dev/null +++ b/pdl/sparc/COPYING @@ -0,0 +1,74 @@ + ArchC DEVELOPMENT PUBLIC LICENSE + +Everyone is permitted to copy and distribute verbatim copies of this +license document, but changing it is not allowed. + + Preamble + +You received this software from a trusted source and for research +purposes. Using or modifying this Program implies full acceptance of +this license. Please contact the person who send or gave you access to +this program for further information. + + ArchC DEVELOPMENT PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + +This license extends to all Programs contained in the package that +you received, including all subdirectories from this root, except if +the file header indicates another license. + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. + + 1. You may copy verbatim copies of the Program's source code as you +receive it, in any medium, for personal use, provided that you copy +copyright notice and disclaimer of warranty; and keep intact all the +notices that refer to this License and to the absence of any warranty. + +Personal use can be extended to a laboratory facility or a shared room +only if you are in charge of a research group that contributes to this +program and only with developing and research purposes. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy such +modifications or work under the terms of Section 1 above, provided +that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must not share, publish or distribute this program, either + in parts or in original form. You must not share, publish or + distribute programs that use this Program, either in parts or in + its original form. + + + 3. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or using the Program (or any work based on the Program), you +indicate your acceptance of this License to do so, and all its terms +and conditions for copying, distributing or modifying the Program or +works based on it. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the software in its development phase. + + NO WARRANTY + + 4. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + END OF TERMS AND CONDITIONS + diff --git a/pdl/sparc/HISTORY.md b/pdl/sparc/HISTORY.md new file mode 100644 index 0000000..b75fcb9 --- /dev/null +++ b/pdl/sparc/HISTORY.md @@ -0,0 +1,75 @@ +## 2.4.0 + +* Revision numbers following the ArchC release +* Instructions with cycles annotations +* Two new .ac files to use with MPSoCBench (block and nonblock) +* sparc_isa.cpp using the reserved work DATA_PORT to data request. See the [commit message](https://github.com/ArchC/sparc/commit/b52eac067ce76e6e4de016697f2158c12d3fcdb1). +* Interrupt handler support. It is inactive in standalone simulator. +* New PowerSC tables + +[Full changelog](https://github.com/ArchC/sparc/compare/v2.3.0...v2.4.0) + +## 2.3.0 +* Revision numbers following the ArchC release ++ PowerSC support with power tables ++ Added id register for core identification + +[Full changelog](https://github.com/ArchC/sparc/compare/v1.0.0...v2.3.0) + +## 1.0.0 +* ArchC 2.2 compliant + +[Full changelog](https://github.com/ArchC/sparc/compare/v0.7.8...v1.0.0) + +## 0.7.8 ++ Added binary utilities support files +* ArchC 2.0 compliant + +[Full changelog](https://github.com/ArchC/sparc/compare/v0.7.7...v0.7.8) + +## 0.7.7-archc2.0beta3 ++ Fixed an annoying bug which caused a segfault on the fft program (MiBench) + +[Full changelog](https://github.com/ArchC/sparc/compare/v0.7.6...v0.7.7) + +## 0.7.6-archc2.0beta3 + ++ Added license headers + +[Full changelog](https://github.com/ArchC/sparc/compare/v0.7.5-1...v0.7.6) + +## 0.7.5-archc2.0beta1 + +* Model compliant with ArchC 2.0beta1 + +[Full changelog](https://github.com/ArchC/sparc/compare/v0.7.5...v0.7.5-1) + +## 0.7.5 + +* Fixed 'unimplemented' instruction format and assembly syntax +* Fixed bug in mulscc_reg and mulscc_imm instructions (condition codes) +* npc initialization depends on ac_pc, so program can start at arbitrary address + +## 0.7.4 + ++ Included assembly language syntax information + +## 0.7.3 + +* Fix bug in instruction MULSCC (used only for V7 multiplication) ++ New REGS register bank holds the current register window from RB +* Use ArchC support for debug messages: ac_debug_model.H +* Use operator[] syntax to read register banks, which is faster + +## 0.7.2 + ++ Included optimization instruction methods for compiled simulation +* Separate nop instruction from sethi to optimize simulation + +## 0.7.1 + ++ Included file for GDB integration + +## 0.7.0 + +* Model passed selected Mediabench and Mibench applications diff --git a/pdl/sparc/README.md b/pdl/sparc/README.md new file mode 100644 index 0000000..41432fa --- /dev/null +++ b/pdl/sparc/README.md @@ -0,0 +1,75 @@ +SPARC V8 ArchC functional model +=============================== + +This is the SPARC-V8 ArchC functional model. + +License +------- + - ArchC models are provided under the ArchC license. + See [Copying](COPYING) file for details on this license. + +acsim +----- + +This model has the system call emulation functions implemented, +so it is a good idea to turn on the ABI option. + +To use acsim, the interpreted simulator: + + acsim sparcv8.ac -abi (create the simulator) + make (compile) + sparcv8.x --load= [args] (run an application) + +The [args] are optional arguments for the application. + +There are two formats recognized for application : +- ELF binary matching ArchC specifications +- hexadecimal text file for ArchC + + +Binary utilities +---------------- +To generate binary utilities use: + + acbingen.sh -i -a sparcv8.ac + +This will generate the tools source files using the architeture +name (if omitted, sparcv8 is used), copy them to the +binutils source tree, build and install them into the directory + (which -must- be an absolute path). +Use "acbingen.sh -h" to get information about the command-line +options available. + + +Change history +------------ + +See [History](HISTORY.md) + + +Contributing +------------ + +See [Contributing](CONTRIBUTING.md) + + +More +---- + +Remember that ArchC models and SystemC library must be compiled with +the same GCC version, otherwise you will get compilation problems. + +Several documents which further information can be found in the 'doc' +subdirectory. + +You can find language overview, models, and documentation at +http://www.archc.org + + + +Thanks for the interest. We hope you enjoy using ArchC! + +The ArchC Team +Computer Systems Laboratory (LSC) +IC-UNICAMP +http://www.lsc.ic.unicamp.br diff --git a/pdl/sparc/ansi-colors.h b/pdl/sparc/ansi-colors.h new file mode 100644 index 0000000..f9f3efe --- /dev/null +++ b/pdl/sparc/ansi-colors.h @@ -0,0 +1,57 @@ +/** + * @file ansi-colors.h + * @author Sandro Rigo + * Marcus Bartholomeu + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:50:50 -0300 + * + * @brief The ArchC SPARC-V8 functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + */ + +#ifndef ANSI_COLORS_H +#define ANSI_COLORS_H + +#define C_RESET "\E[0m" +#define C_BOLD "\E[1m" +#define C_ITALIC "\E[3m" +#define C_UNDERLINE "\E[4m" +#define C_INVERSE "\E[7m" +#define C_STRIKETHROUGH "\E[9m" +#define C_BOLD_OFF "\E[22m" +#define C_ITALIC_OFF "\E[23m" +#define C_UNDERLINE_OFF "\E[24m" +#define C_INVERSE_OFF "\E[27m" +#define C_STRIKETHROUGH_OFF "\E[29m" +#define CF_BLACK "\E[30m" +#define CF_RED "\E[31m" +#define CF_GREEN "\E[32m" +#define CF_YELLOW "\E[33m" +#define CF_BLUE "\E[34m" +#define CF_MAGENTA "\E[35m" +#define CF_CYAN "\E[36m" +#define CF_WHITE "\E[37m" +#define CF_DEFAULT "\E[39m" +#define CB_BLACK "\E[40m" +#define CB_RED "\E[41m" +#define CB_GREEN "\E[42m" +#define CB_YELLOW "\E[43m" +#define CB_BLUE "\E[44m" +#define CB_MAGENTA "\E[45m" +#define CB_CYAN "\E[46m" +#define CB_WHILE "\E[47m" +#define CB_DEFAULT "\E[49m" + +#define LF "\n" + +#endif diff --git a/pdl/sparc/arch_power_stats.H b/pdl/sparc/arch_power_stats.H new file mode 100644 index 0000000..10f3772 --- /dev/null +++ b/pdl/sparc/arch_power_stats.H @@ -0,0 +1,644 @@ +#ifdef POWER_SIM +#include +#include + +/* Data struct definition. You should think that it is a row in a table. Each profile will have a certain number of tables. + The basic idea is use a profile, with a pre-fixed number of operational frequencies. Each frequency, with a specific + table of values */ + +// This group should be parameters, not defines + +#define NUM_INSTR 119 +//#define POWER_TABLE_FILE "acpower_table_sparc_spartan_50Mhz.csv" +//#define POWER_TABLE_FILE "acpower_table_sparc_xc3s1000_40Mhz.csv" +//#define POWER_TABLE_FILE "acpower_table_sparc_xc3s1200e_40Mhz.csv" +//#define POWER_TABLE_FILE "acpower_table_sparc_xc5vlx50t_40Mhz.csv" +#define POWER_TABLE_FILE "acpower_table_sparc_xc6slx75_40Mhz.csv" + +#define WINDOW_REPORT +#define WINDOW_REPORT_FILE "window_power_report" +#define START_WINDOW_SIZE 1000 + +#define MAX_LINESIZE_CSV_FILE 10240 // Inefficient and non-scalable +#define MAX_INSTR_NAME_SIZE 30 +#define MAX_POWER_STATS_NAME_SIZE 30 +#define MAX_POWER_STATS_DESCR_SIZE 140 + +#define TYPE_LINE_NUM_PROFILE 0 +#define TYPE_LINE_PROFILE 1 +#define TYPE_LINE_STALL 2 +#define TYPE_LINE_OP 3 + + +#define CYCLES_PER_FREQUENCY_EXCHANGE 20000 // nanoseconds = or 20 micro seconds +#define CYCLES_TO_RESTART 300 + +//#define DEBUG + +class power_stats { + private: + struct profile + { + char power_stats_name[MAX_POWER_STATS_NAME_SIZE]; + char power_stats_descr[MAX_POWER_STATS_DESCR_SIZE]; + + unsigned int freq; + double freq_scale; + double power_scale; + double power[NUM_INSTR+1]; + double stall_power; + + }; + + struct power_stats_data + { + char instr_name[NUM_INSTR+1][MAX_INSTR_NAME_SIZE]; + profile* p; + int index_nop; + }; + + struct dynamic_data + { + #ifdef WINDOW_REPORT + long long window_num_instr; + double window_energy; + double window_power; + long long window_count; + unsigned int window_size; + #endif + + + double execution_time; + sc_core::sc_time system_time; + long long total_num_instr; + double total_energy; + double total_power; + + /*****/ + double edp; + double energy_per_core; + + int delta_instr; + int last_delta_instr; + + double delta_t; + + unsigned int actual_profile; + unsigned int num_profiles; + + bool freq_changed; + }; + + dynamic_data dyn; + power_stats_data psc_data; + + + #ifdef WINDOW_REPORT + FILE* out_window_power_report; + + #endif + + #ifdef DEBUG + FILE* debug_file; + int contador_debug; + #endif + + + + + public: + psc_cell_power_info psc_info; + + // Constructor + power_stats(const char* proc_name): psc_info(proc_name, "Processor") + { + PSC_NUM_FIRST_SAMPLES(0x7FFFFFFF); + init(POWER_TABLE_FILE); + + /*Initialize power state using profile 0*/ + dyn.actual_profile = 0; + dyn.total_num_instr = 0; + dyn.total_energy = 0; + dyn.total_power = 0; + + /******/ + dyn.edp = 0; + dyn.energy_per_core = 0; + dyn.delta_instr = 0; + dyn.delta_t = 0; + dyn.last_delta_instr = 0; + + dyn.freq_changed = false; + + + char filename[512]; + + #ifdef WINDOW_REPORT + dyn.window_size = START_WINDOW_SIZE; + dyn.window_num_instr = 0; + dyn.window_energy = 0; + dyn.window_power = 0; + dyn.window_count = 0; + dyn.execution_time = 0; + dyn.system_time = sc_time(0,SC_NS); + + /****/ + + strcpy(filename, WINDOW_REPORT_FILE); + strcat(filename, "_"); + strcat(filename, proc_name); + strcat(filename, ".csv"); + out_window_power_report = fopen(filename, "w"); + if (out_window_power_report == NULL) { + perror("Couldn't open specified out_window_power_report file"); + exit(1); + } + /****/ + #endif + + #ifdef DEBUG + strcpy (filename, "debug_power"); + strcat(filename, "_"); + strcat(filename, proc_name); + strcat(filename, ".txt"); + + debug_file = fopen(filename, "w"); + if (debug_file == NULL) { + perror("Couldn't open specified debug file"); + exit(1); + } + contador_debug = 0; + + print_psc_data(); + #endif + } + + + // Destructor + ~power_stats() + { + free(psc_data.p); + + #ifdef WINDOW_REPORT + fclose(out_window_power_report); + #endif + + #ifdef DEBUG + fclose(debug_file); + #endif + } + + double get_power() { + return psc_info.get_power(); + } + + double get_power_instruction(int id, int profile) + { + // [J] * [1/s] = [W] + + double power = psc_data.p[profile].power[id] * psc_data.p[profile].power_scale * psc_data.p[profile].freq_scale * psc_data.p[profile].freq; + + #ifdef DEBUG + fprintf(debug_file,"\nGetting power instruction."); + fprintf(debug_file,"\nprofile: %d\t id: %d\t power[id]*power_scale*freq_scale*freq = %f * %f * %f * %d" , profile, id, psc_data.p[profile].power[id], psc_data.p[profile].power_scale, psc_data.p[profile].freq_scale, psc_data.p[profile].freq); + fprintf(debug_file,"\nReturning: %f", power); + contador_debug++; + #endif + + return power; + } + + double update_energy (int id, int profile) + { + + //printf("\nupdate_energy id=%d profile=%d", id, profile); + + double energy_per_instruction = psc_data.p[profile].power[id]; // * psc_data.p[profile].power_scale; + + set_edp(dyn.edp + energy_per_instruction); + dyn.energy_per_core = dyn.energy_per_core + energy_per_instruction; + } + + + double get_energy_stamp (int prof) + { + + dyn.delta_instr = get_total_num_instr() - dyn.delta_instr; // total de instr executadas no delta_T atual + int freq = psc_data.p[prof].freq; // freq em MegaHz + double cycle_time_ns = 1000/freq; // tempo de um ciclo em nanossegundos + double edp = get_edp(); + + double energyStampUsingFreq = (double) edp*dyn.delta_instr*cycle_time_ns; + + dyn.delta_t = sc_time_stamp().to_seconds() - dyn.delta_t; + + + double t = dyn.delta_t*1000000000; // em nanossegundos + + + double energyStampUsingTime = edp*t; + + return energyStampUsingTime; + } + + void initialize_energy_stamp() + { + dyn.edp = 0.0; + dyn.delta_instr = 0; + + } + + double get_edp () + { + return dyn.edp; + } + void set_edp (double value) + { + dyn.edp = value; + } + int type_line(int line, int num_profiles) + { + if (num_profiles == 0) + { + return TYPE_LINE_NUM_PROFILE; + } + else if (line <= num_profiles + 1) + { + return TYPE_LINE_PROFILE; + } + else if (line == num_profiles + 2) + { + return TYPE_LINE_STALL; + } + else + return TYPE_LINE_OP; + } + + #ifdef WINDOW_REPORT + void incr_window_energy(double v) + { + dyn.window_energy += v; + } + + void reset_window_data() + { + dyn.window_num_instr = 0; + dyn.window_energy = 0; + dyn.window_power = 0; + } + + void calc_window_power() + { + + dyn.window_power = dyn.window_energy / dyn.window_num_instr; + } + + void window_power_report() + { + + fprintf(out_window_power_report, "%d,%.10lf,%lld,%.10lf\n", dyn.actual_profile, dyn.execution_time, dyn.window_count, dyn.window_power); + } + #endif + + void incr_total_energy(double v) { + dyn.total_energy += v; + + } + + void incr_execution_time(int num_instr, int p) + { + + dyn.system_time = sc_time_stamp (); + + dyn.execution_time += num_instr / (psc_data.p[dyn.actual_profile].freq * psc_data.p[dyn.actual_profile].freq_scale); + + } + + void update_stat_power(int instr_id, int n = 1) + { + + #ifdef DEBUG + if (n!=1) + { + printf("\nPOWER_STATS: calculating power after change frequency."); + printf("\nPOWER_STATS: NOP id: %d , NOP power: %f",instr_id, get_power_instruction(instr_id, dyn.actual_profile)); + } + #endif + + dyn.total_num_instr = dyn.total_num_instr + n; + incr_execution_time(n, dyn.actual_profile); + + incr_total_energy(n * get_power_instruction(instr_id, dyn.actual_profile)); + + + update_energy(instr_id, dyn.actual_profile); + + #ifdef WINDOW_REPORT + + dyn.window_num_instr = dyn.window_num_instr + n; + + + incr_window_energy(n* get_power_instruction(instr_id, dyn.actual_profile)); + + + if (dyn.window_num_instr >= dyn.window_size) + { + dyn.window_count++; + calc_window_power(); + window_power_report(); + reset_window_data(); + } + #endif + + } + + + double get_total_num_instr () + { + return dyn.total_num_instr; + } + double get_total_energy() + { + return dyn.total_energy; + } + + double get_total_power () + { + calc_total_power(); + return dyn.total_power; + } + void calc_total_power() + { + dyn.total_power = dyn.total_energy / dyn.total_num_instr; + + #ifdef DEBUG + fprintf(debug_file,"\n\nCalculating total power = %f:", dyn.total_power); + #endif + } + + void powersc_connect() + { + calc_total_power(); + + // teste + psc_info.set_power(dyn.total_power); + psc_info.set_level(PSC_RT_LEVEL); + PSC_INSERT_CELL(psc_info); + + } + + void report() + { + PSC_REPORT_POWER; + dyn.system_time = sc_time_stamp(); + + } + + double getEnergyPerCore() + { + return dyn.energy_per_core; + } + char* next_strtok(const char* param, FILE* f, int pos_line) + { + char* pch = NULL; + pch = strtok(NULL,param); + if (pch == NULL) { + printf("Error reading csv file, line %d. Unexpected format\n", pos_line); + fclose(f); + exit(1); + } + return pch; + } + + // Read from file + void init(const char* filename) + { + FILE* f = NULL; + char c = 0; + char line[MAX_LINESIZE_CSV_FILE]; + char instr_name[MAX_INSTR_NAME_SIZE]; + char aux[MAX_LINESIZE_CSV_FILE]; + double value; + char* res; + + unsigned int index = 0; + unsigned int pos_line = 0; + unsigned int valid_line = 0; + unsigned int profile_id = 0; + fpos_t pos; + + char* pch = NULL; + + // Get self PATH + char buff[1024]; + strcpy (buff, POWER_SIM); + strcat (buff, "/"); + strcat (buff, filename); + + f = fopen(buff, "r"); + if (f == NULL) { + sprintf(aux, "Power file %s not found", buff); + perror(aux); + exit(1); + } + + dyn.num_profiles = 0; // Set a default value + + int state_id = 0; + + do { + //fgetpos (f, &pos); + res = fgets(line, MAX_LINESIZE_CSV_FILE, f); // Get a new line from file + if (feof(f)) break; + pos_line++; // It says what line I am reading now + pch = strtok(line, ",\""); // It parses the line + + + if (pch[0] == '#'); // If it is a comment, ignore + else if (pch == NULL) break; + else + { // Just found a valid new line + valid_line++; + // First Valid Line: number of profiles + switch(type_line(valid_line, dyn.num_profiles)) + { + case TYPE_LINE_NUM_PROFILE: + dyn.num_profiles = atoi(pch); + + psc_data.p = (profile *)malloc(sizeof(profile) * dyn.num_profiles); + // Cleaning table + for(int j = 0; j <= NUM_INSTR; j++) { + strcpy(psc_data.instr_name[j], ""); + for (int i = 0; i < dyn.num_profiles; i++) { + psc_data.p[i].power[j] = 0; + } + } + break; + + case TYPE_LINE_PROFILE: + + profile_id = state_id++; + + if (profile_id >= dyn.num_profiles) { + printf("Error: Invalid profile_id greater than num_profiles: %d > %d\n", + profile_id, dyn.num_profiles); + } + + //pch = next_strtok(",\"", f, pos_line); + psc_data.p[profile_id].freq = atoi(pch); + + pch = next_strtok(",\"", f, pos_line); + psc_data.p[profile_id].freq_scale = atof(pch); + + pch = next_strtok(",\"", f, pos_line); + psc_data.p[profile_id].power_scale = atof(pch); + + pch = next_strtok(",\"", f, pos_line); + strcpy(psc_data.p[profile_id].power_stats_name, pch); + + pch = next_strtok(",\"", f, pos_line); + strcpy(psc_data.p[profile_id].power_stats_descr, pch); + break; + case TYPE_LINE_STALL: + psc_data.p[0].stall_power = atof(pch); + + for(int i = 1; i < dyn.num_profiles;i++) { + pch = next_strtok(",\"", f, pos_line); + psc_data.p[i].stall_power = atof(pch); + } + break; + default: // TYPE_LINE_OP + + index = atoi(pch); + if (index <= NUM_INSTR) { + pch = next_strtok(",\"", f, pos_line); + strcpy(psc_data.instr_name[index], pch); + if (!strcmp(pch,"nop")) psc_data.index_nop = index; // capture the NOP index + + for(int i = 0; i < dyn.num_profiles;i++) + { + pch = next_strtok(",\"", f, pos_line); + psc_data.p[i].power[index] = atof(pch); + } + } + break; + } + } + } while(!feof(f)); + + fclose(f); + + + } + + void print_psc_data() { + + + + #ifdef DEBUG + + int i = 0, p = 0; + for(p = 0; p < dyn.num_profiles; p++) { + printf("\nProfile %d\n", p); + printf("Name: %s\n", psc_data.p[p].power_stats_name); + printf("Description: %s\n", psc_data.p[p].power_stats_descr); + printf("Frequency: %d\n\n", psc_data.p[p].freq); + printf("Frequency: %f\n\n", psc_data.p[p].freq_scale); + printf("NOP Power: %f\n\n", psc_data.p[p].power[psc_data.index_nop]); + + fprintf(debug_file,"\nProfile %d\n", p); + fprintf(debug_file,"Name: %s\n", psc_data.p[p].power_stats_name); + fprintf(debug_file,"Description: %s\n", psc_data.p[p].power_stats_descr); + fprintf(debug_file,"Frequency: %d\n\n", psc_data.p[p].freq); + fprintf(debug_file,"Frequency: %f\n\n", psc_data.p[p].freq_scale); + fprintf(debug_file,"NOP Power: %f\n\n", psc_data.p[p].power[psc_data.index_nop]); + } + + printf("Instr ID | Instruction Name"); + fprintf(debug_file,"Instr ID | Instruction Name"); + for(p = 0; p < dyn.num_profiles; p++) { + printf(" | Power Profile %d", p); + fprintf(debug_file," | Power Profile %d", p); + } + printf("\n"); + fprintf(debug_file,"\n"); + for(i = 1; i <= NUM_INSTR; i++) { + printf("%8d | %16s", i, psc_data.instr_name[i]); + fprintf(debug_file,"%8d | %16s", i, psc_data.instr_name[i]); + for(p = 0; p < dyn.num_profiles; p++) { + printf(" | %15.3lf", psc_data.p[p].power[i]); + fprintf(debug_file," | %15.3lf", psc_data.p[p].power[i]); + + } + + printf("\n"); + fprintf(debug_file,"\n"); + } + + #endif + } + + + /****** NEW DVFS FUNCTIONS *******/ + int getPowerState() + { + return dyn.actual_profile; + } + + void setPowerState (int state) + { + + if (state < dyn.num_profiles) + { + dyn.actual_profile = state; + + update_stat_power (psc_data.index_nop, CYCLES_PER_FREQUENCY_EXCHANGE); + + dyn.freq_changed = true; + + #ifdef DEBUG + printf("\nPOWER_STATS: updating the power state to %d ",state); + #endif + } + } + + bool needToWait() + { + if (dyn.freq_changed) + { + dyn.freq_changed = false; + return (true); + } + else return (false); + + + } + + int getNumberOfStates() + { + return dyn.num_profiles; + } + + void completeListOfStates (int* list) + { + + #ifdef DEBUG + printf("\nPOWER_STATS: returning the list of available states"); + #endif + + for (int i=0; iType_F3B.simm13 = reloc->input & 0x3FF; + +// reloc->output = reloc->input & 0x3FF; +} + +ac_modifier_decode(low) +{ +} + +ac_modifier_encode(pcrel) +{ + reloc->output = (reloc->input - reloc->address) >> 2; +} + +ac_modifier_decode(pcrel) +{ + reloc->output = (reloc->input << 2) + reloc->address; +} + +ac_modifier_encode(high) +{ + reloc->Type_F2A.imm22 = reloc->input >> 10; + +// reloc->output = reloc->input >> 10; +} + +ac_modifier_decode(high) +{ +} diff --git a/pdl/sparc/powersc/acpower_table_sparc_spartan_50Mhz.csv b/pdl/sparc/powersc/acpower_table_sparc_spartan_50Mhz.csv new file mode 100644 index 0000000..ad0c072 --- /dev/null +++ b/pdl/sparc/powersc/acpower_table_sparc_spartan_50Mhz.csv @@ -0,0 +1,125 @@ +# Number of profiles +1 +# ProfileID, Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +50,1e6,1e-12,"Leon3 at 50MHz","Using Xilinx tools, Spartan3 at 50MHz" +# Stall consumption +0 +1,call,103.80 +2,nop,149.60 +3,sethi,244.80 +4,ba,102.80 +5,bn,150.00 +6,bne,150.40 +7,be,102.40 +8,bg,151.80 +9,ble,102.40 +10,bge,106.40 +11,bl,151.80 +12,bgu,151.80 +13,bleu,102.20 +14,bcc,106.20 +15,bcs,151.60 +16,bpos,106.60 +17,bneg,151.60 +18,bvc,106.40 +19,bvs,151.80 +20,ldsb_reg,118.20 +21,ldsh_reg,117.00 +22,ldub_reg,111.00 +23,lduh_reg,111.40 +24,ld_reg,111.00 +25,ldd_reg,169.80 +26,stb_reg,235.20 +27,sth_reg,220.40 +28,st_reg,189.40 +29,std_reg,167.20 +30,ldstub_reg,149.60 +31,swap_reg,137.60 +32,sll_reg,183.40 +33,srl_reg,175.80 +34,sra_reg,176.20 +35,add_reg,396.00 +36,addcc_reg,396.80 +37,addx_reg,394.60 +38,addxcc_reg,397.40 +39,sub_reg,405.20 +40,subcc_reg,407.80 +41,subx_reg,405.20 +42,subxcc_reg,407.40 +43,and_reg,174.20 +44,andcc_reg,175.00 +45,andn_reg,176.20 +46,andncc_reg,177.40 +47,or_reg,182.60 +48,orcc_reg,183.00 +49,orn_reg,193.00 +50,orncc_reg,194.40 +51,xor_reg,288.00 +52,xorcc_reg,281.60 +53,xnor_reg,375.60 +54,xnorcc_reg,380.00 +55,save_reg,171.40 +56,restore_reg,169.60 +57,umul_reg,115.00 +58,smul_reg,116.00 +59,umulcc_reg,113.60 +60,smulcc_reg,115.20 +61,mulscc_reg,278.80 +62,udiv_reg,115.00 +63,udivcc_reg,113.60 +64,sdiv_reg,116.00 +65,sdivcc_reg,115.20 +66,jmpl_reg,102.80 +67,wry_reg,218.80 +68,ldsb_imm,118.20 +69,ldsh_imm,117.00 +70,ldub_imm,111.00 +71,lduh_imm,111.40 +72,ld_imm,111.00 +73,ldd_imm,126.40 +74,and_imm,188.20 +75,andcc_imm,191.00 +76,andn_imm,205.60 +77,andncc_imm,209.80 +78,or_imm,217.60 +79,orcc_imm,217.00 +80,orn_imm,222.20 +81,orncc_imm,224.60 +82,xor_imm,257.00 +83,xorcc_imm,265.40 +84,xnor_imm,345.40 +85,xnorcc_imm,347.20 +86,umul_imm,133.20 +87,smul_imm,171.00 +88,umulcc_imm,144.40 +89,smulcc_imm,167.60 +90,mulscc_imm,256.40 +91,udiv_imm,133.20 +92,udivcc_imm,144.40 +93,sdiv_imm,171.00 +94,sdivcc_imm,144.40 +95,stb_imm,229.80 +96,sth_imm,220.40 +97,st_imm,189.40 +98,std_imm,167.20 +99,ldstub_imm,149.60 +100,swap_imm,137.60 +101,sll_imm,195.20 +102,srl_imm,193.60 +103,sra_imm,190.60 +104,add_imm,272.00 +105,addcc_imm,286.00 +106,addx_imm,282.20 +107,addxcc_imm,282.80 +108,sub_imm,298.60 +109,subcc_imm,302.20 +110,subx_imm,299.40 +111,subxcc_imm,300.00 +112,jmpl_imm,102.80 +113,save_imm,171.00 +114,restore_imm,170.00 +115,rdy,160.00 +116,wry_imm,324.00 +117,unimplemented,0 +118,trap_reg,0 +119,trap_imm,0 diff --git a/pdl/sparc/powersc/acpower_table_sparc_xc3s1000_40Mhz.csv b/pdl/sparc/powersc/acpower_table_sparc_xc3s1000_40Mhz.csv new file mode 100644 index 0000000..1615d9b --- /dev/null +++ b/pdl/sparc/powersc/acpower_table_sparc_xc3s1000_40Mhz.csv @@ -0,0 +1,125 @@ +# Number of profiles +1 +# ProfileID, Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +40,1.00E+06,1.00E-12,"Leon3 at 40MHz","Using Xilinx tools, Spartan3 at 40MHz" +# Stall consumption +0 +1,add_imm,540.25 +2,add_reg,624.00 +3,addcc_imm,502.50 +4,addcc_reg,625.25 +5,addx_imm,505.25 +6,addx_reg,624.00 +7,addxcc_imm,503.50 +8,addxcc_reg,626.25 +9,and_imm,386.75 +10,and_reg,370.25 +11,andcc_imm,390.25 +12,andcc_reg,372.75 +13,andn_imm,419.75 +14,andn_reg,373.75 +15,andncc_imm,422.25 +16,andncc_reg,379.75 +17,ba,283.50 +18,bcc,288.00 +19,bcs,348.00 +20,be,283.25 +21,bg,348.00 +22,bge,288.00 +23,bgu,348.00 +24,bl,348.00 +25,ble,283.25 +26,bleu,283.00 +27,bn,345.75 +28,bne,346.25 +29,bneg,347.75 +30,bpos,288.25 +31,bvc,288.25 +32,bvs,348.00 +33,call,285.00 +34,jmpl_imm,283.50 +35,jmpl_reg,283.50 +36,ld_imm,295.50 +37,ld_reg,295.50 +38,ldd_imm,314.75 +39,ldd_reg,378.25 +40,ldsb_imm,304.50 +41,ldsb_reg,304.50 +42,ldsh_imm,303.00 +43,ldsh_reg,303.00 +44,ldstub_imm,343.25 +45,ldstub_reg,343.25 +46,ldub_imm,295.25 +47,ldub_reg,295.25 +48,lduh_imm,295.75 +49,lduh_reg,295.75 +50,mulscc_imm,469.00 +51,mulscc_reg,605.50 +52,nop,345.75 +53,or_imm,429.75 +54,or_reg,386.75 +55,orcc_imm,433.25 +56,orcc_reg,388.25 +57,orn_imm,425.00 +58,orn_reg,395.00 +59,orncc_imm,426.00 +60,orncc_reg,395.00 +61,rdy,356.50 +62,restore_imm,379.75 +63,restore_reg,380.50 +64,save_imm,381.75 +65,save_reg,383.25 +66,sdiv_imm,355.75 +67,sdiv_reg,295.00 +68,sdivcc_imm,354.25 +69,sdivcc_reg,296.50 +70,sethi,450.25 +71,sll_imm,392.75 +72,sll_reg,383.50 +73,smul_imm,355.75 +74,smul_reg,295.00 +75,smulcc_imm,354.25 +76,smulcc_reg,296.50 +77,sra_imm,390.50 +78,sra_reg,372.50 +79,srl_imm,392.00 +80,srl_reg,372.75 +81,st_imm,433.25 +82,st_reg,433.25 +83,stb_imm,396.50 +84,stb_reg,386.50 +85,std_imm,412.75 +86,std_reg,412.75 +87,sth_imm,458.50 +88,sth_reg,458.50 +89,sub_imm,507.25 +90,sub_reg,631.50 +91,subcc_imm,513.75 +92,subcc_reg,634.25 +93,subx_imm,505.75 +94,subx_reg,629.00 +95,subxcc_imm,511.00 +96,subxcc_reg,631.75 +97,swap_imm,327.50 +98,swap_reg,327.50 +99,trap_imm,0.00 +100,trap_reg,0.00 +101,udiv_imm,325.25 +102,udiv_reg,295.50 +103,udivcc_imm,323.00 +104,udivcc_reg,300.00 +105,umul_imm,325.25 +106,umul_reg,295.50 +107,umulcc_imm,323.00 +108,umulcc_reg,300.00 +109,unimplemented,0.00 +110,wry_imm,589.00 +111,wry_reg,482.00 +112,xnor_imm,562.00 +113,xnor_reg,595.25 +114,xnorcc_imm,563.50 +115,xnorcc_reg,601.25 +116,xor_imm,482.25 +117,xor_reg,588.75 +118,xorcc_imm,481.00 +119,xorcc_reg,592.75 diff --git a/pdl/sparc/powersc/acpower_table_sparc_xc3s1200e_40Mhz.csv b/pdl/sparc/powersc/acpower_table_sparc_xc3s1200e_40Mhz.csv new file mode 100644 index 0000000..5279dcf --- /dev/null +++ b/pdl/sparc/powersc/acpower_table_sparc_xc3s1200e_40Mhz.csv @@ -0,0 +1,125 @@ +# Number of profiles +1 +# ProfileID, Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +40,1e6,1e-9,"Leon3 at 40MHz","Using Xilinx tools, Spartan3 at 40MHz" +# Stall consumption +0 +1,call,0.28 +2,nop,0.31 +3,sethi,0.52 +4,ba,0.28 +5,bn,0.39 +6,bne,0.4 +7,be,0.28 +8,bg,0.4 +9,ble,0.28 +10,bge,0.29 +11,bl,0.4 +12,bgu,0.4 +13,bleu,0.28 +14,bcc,0.29 +15,bcs,0.4 +16,bpos,0.29 +17,bneg,0.4 +18,bvc,0.29 +19,bvs,0.4 +20,ldsb_reg,0.3 +21,ldsh_reg,0.3 +22,ldub_reg,0.29 +23,lduh_reg,0.29 +24,ld_reg,0.29 +25,ldd_reg,0.52 +26,stb_reg,0.44 +27,sth_reg,0.43 +28,st_reg,0.56 +29,std_reg,0.69 +30,ldstub_reg,0.37 +31,swap_reg,0.34 +32,sll_reg,0.44 +33,srl_reg,0.43 +34,sra_reg,0.43 +35,add_reg,0.66 +36,addcc_reg,0.71 +37,addx_reg,0.7 +38,addxcc_reg,0.7 +39,sub_reg,0.7 +40,subcc_reg,0.71 +41,subx_reg,0.71 +42,subxcc_reg,0.72 +43,and_reg,0.43 +44,andcc_reg,0.43 +45,andn_reg,0.43 +46,andncc_reg,0.44 +47,or_reg,0.45 +48,orcc_reg,0.45 +49,orn_reg,0.46 +50,orncc_reg,0.45 +51,xor_reg,0.68 +52,xorcc_reg,0.69 +53,xnor_reg,0.64 +54,xnorcc_reg,0.69 +55,save_reg,0.43 +56,restore_reg,0.43 +57,umul_reg,0.3 +58,smul_reg,0.49 +59,umulcc_reg,0.3 +60,smulcc_reg,0.45 +61,mulscc_reg,0.53 +62,udiv_reg,0.3 +63,udivcc_reg,0.3 +64,sdiv_reg,0.49 +65,sdivcc_reg,0.45 +66,jmpl_reg,0.28 +67,wry_reg,0.57 +68,ldsb_imm,0.3 +69,ldsh_imm,0.3 +70,ldub_imm,0.29 +71,lduh_imm,0.29 +72,ld_imm,0.29 +73,ldd_imm,0.32 +74,and_imm,0.45 +75,andcc_imm,0.46 +76,andn_imm,0.49 +77,andncc_imm,0.49 +78,or_imm,0.39 +79,orcc_imm,0.3 +80,orn_imm,0.5 +81,orncc_imm,0.5 +82,xor_imm,0.56 +83,xorcc_imm,0.46 +84,xnor_imm,0.66 +85,xnorcc_imm,0.66 +86,umul_imm,0.31 +87,smul_imm,0.39 +88,umulcc_imm,0.31 +89,smulcc_imm,0.5 +90,mulscc_imm,0.44 +91,udiv_imm,0.31 +92,udivcc_imm,0.31 +93,sdiv_imm,0.39 +94,sdivcc_imm,0.5 +95,stb_imm,0.44 +96,sth_imm,0.43 +97,st_imm,0.56 +98,std_imm,0.69 +99,ldstub_imm,0.37 +100,swap_imm,0.34 +101,sll_imm,0.54 +102,srl_imm,0.59 +103,sra_imm,0.5 +104,add_imm,0.58 +105,addcc_imm,0.59 +106,addx_imm,0.58 +107,addxcc_imm,0.62 +108,sub_imm,0.59 +109,subcc_imm,0.43 +110,subx_imm,0.59 +111,subxcc_imm,0.59 +112,jmpl_imm,0.28 +113,save_imm,0.43 +114,restore_imm,0.43 +115,rdy,0.41 +116,wry_imm,0.68 +117,unimplemented,0 +118,trap_reg,0 +119,trap_imm,0 diff --git a/pdl/sparc/powersc/acpower_table_sparc_xc5vlx50t_40Mhz.csv b/pdl/sparc/powersc/acpower_table_sparc_xc5vlx50t_40Mhz.csv new file mode 100644 index 0000000..702f25d --- /dev/null +++ b/pdl/sparc/powersc/acpower_table_sparc_xc5vlx50t_40Mhz.csv @@ -0,0 +1,125 @@ +# Number of profiles +1 +# ProfileID, Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description, +40,1e6,1e-9,"Leon3 at 40MHz","Using Xilinx tools Virtex5 at 40MHz" +# Stall consumption +0 +1,call,0.969 +2,nop,0.962 +3,sethi,1.042 +4,ba,0.968 +5,bn,0.963 +6,bne,0.963 +7,be,0.969 +8,bg,0.962 +9,ble,0.968 +10,bge,0.968 +11,bl,0.963 +12,bgu,0.963 +13,bleu,0.968 +14,bcc,0.973 +15,bcs,0.964 +16,bpos,0.968 +17,bneg,0.964 +18,bvc,0.968 +19,bvs,0.964 +20,ldsb_reg,0.985 +21,ldsh_reg,0.986 +22,ldub_reg,0.986 +23,lduh_reg,0.984 +24,ld_reg,0.984 +25,ldd_reg,0.984 +26,stb_reg,1.021 +27,sth_reg,1.109 +28,st_reg,1.093 +29,std_reg,1.074 +30,ldstub_reg,1.012 +31,swap_reg,0.997 +32,sll_reg,1.002 +33,srl_reg,0.983 +34,sra_reg,0.985 +35,add_reg,1.198 +36,addcc_reg,1.212 +37,addx_reg,1.2 +38,addxcc_reg,1.206 +39,sub_reg,1.2 +40,subcc_reg,1.21 +41,subx_reg,1.199 +42,subxcc_reg,1.209 +43,and_reg,0.993 +44,andcc_reg,0.997 +45,andn_reg,0.994 +46,andncc_reg,0.998 +47,or_reg,1.051 +48,orcc_reg,1.058 +49,orn_reg,1.057 +50,orncc_reg,1.058 +51,xor_reg,1.188 +52,xorcc_reg,1.197 +53,xnor_reg,1.196 +54,xnorcc_reg,1.203 +55,save_reg,1.01 +56,restore_reg,1.011 +57,umul_reg,0.985 +58,smul_reg,0.984 +59,umulcc_reg,0.985 +60,smulcc_reg,0.985 +61,mulscc_reg,1.188 +62,udiv_reg,0.985 +63,udivcc_reg,0.985 +64,sdiv_reg,0.984 +65,sdivcc_reg,0.985 +66,jmpl_reg,0.968 +67,wry_reg,1.096 +68,ldsb_imm,0.985 +69,ldsh_imm,0.986 +70,ldub_imm,0.986 +71,lduh_imm,0.984 +72,ld_imm,0.984 +73,ldd_imm,0.984 +74,and_imm,1.01 +75,andcc_imm,1.017 +76,andn_imm,1.032 +77,andncc_imm,1.032 +78,or_imm,1.047 +79,orcc_imm,1.046 +80,orn_imm,1.055 +81,orncc_imm,1.057 +82,xor_imm,1.093 +83,xorcc_imm,1.094 +84,xnor_imm,1.155 +85,xnorcc_imm,1.159 +86,umul_imm,0.994 +87,smul_imm,1 +88,umulcc_imm,0.993 +89,smulcc_imm,0.994 +90,mulscc_imm,1.08 +91,udiv_imm,0.994 +92,udivcc_imm,0.993 +93,sdiv_imm,1 +94,sdivcc_imm,0.994 +95,stb_imm,1.047 +96,sth_imm,1.109 +97,st_imm,1.093 +98,std_imm,1.074 +99,ldstub_imm,1.012 +100,swap_imm,0.997 +101,sll_imm,1.012 +102,srl_imm,1.008 +103,sra_imm,1.009 +104,add_imm,1.138 +105,addcc_imm,1.113 +106,addx_imm,1.113 +107,addxcc_imm,1.11 +108,sub_imm,1.111 +109,subcc_imm,1.111 +110,subx_imm,1.105 +111,subxcc_imm,1.106 +112,jmpl_imm,0.968 +113,save_imm,1.01 +114,restore_imm,1.01 +115,rdy,0.968 +116,wry_imm,1.188 +117,unimplemented,0 +118,trap_reg,0 +119,trap_imm,0 diff --git a/pdl/sparc/powersc/acpower_table_sparc_xc6slx75_40Mhz.csv b/pdl/sparc/powersc/acpower_table_sparc_xc6slx75_40Mhz.csv new file mode 100644 index 0000000..398ebf0 --- /dev/null +++ b/pdl/sparc/powersc/acpower_table_sparc_xc6slx75_40Mhz.csv @@ -0,0 +1,125 @@ +# Number of profiles +1 +# ProfileID, Characterization Frequency,Frequency Scale,EPI Scale,Characterization Name,Characterization Description +40,1.00E+06,1.00E-09,"Leon3 at 40MHz","Using Xilinx tools, Spartan6 at 40MHz" +# Stall consumption +0 +1,add_imm,0.39 +2,add_reg,0.28 +3,addcc_imm,0.39 +4,addcc_reg,0.55 +5,addx_imm,0.39 +6,addx_reg,0.54 +7,addxcc_imm,0.43 +8,addxcc_reg,0.55 +9,and_imm,0.33 +10,and_reg,0.33 +11,andcc_imm,0.33 +12,andcc_reg,0.33 +13,andn_imm,0.35 +14,andn_reg,0.34 +15,andncc_imm,0.36 +16,andncc_reg,0.34 +17,ba,0.25 +18,bcc,0.25 +19,bcs,0.34 +20,be,0.25 +21,bg,0.34 +22,bge,0.25 +23,bgu,0.34 +24,bl,0.34 +25,ble,0.25 +26,bleu,0.25 +27,bn,0.33 +28,bne,0.34 +29,bneg,0.34 +30,bpos,0.25 +31,bvc,0.25 +32,bvs,0.34 +33,call,0.26 +34,jmpl_imm,0.25 +35,jmpl_reg,0.25 +36,ld_imm,0.23 +37,ld_reg,0.23 +38,ldd_imm,0.24 +39,ldd_reg,0.24 +40,ldsb_imm,0.24 +41,ldsb_reg,0.24 +42,ldsh_imm,0.24 +43,ldsh_reg,0.24 +44,ldstub_imm,0.26 +45,ldstub_reg,0.26 +46,ldub_imm,0.22 +47,ldub_reg,0.22 +48,lduh_imm,0.22 +49,lduh_reg,0.22 +50,mulscc_imm,0.42 +51,mulscc_reg,0.33 +52,nop,0.31 +53,or_imm,0.37 +54,or_reg,0.36 +55,orcc_imm,0.37 +56,orcc_reg,0.36 +57,orn_imm,0.37 +58,orn_reg,0.36 +59,orncc_imm,0.37 +60,orncc_reg,0.37 +61,rdy,0.36 +62,restore_imm,0.19 +63,restore_reg,0.19 +64,save_imm,0.19 +65,save_reg,0.19 +66,sdiv_imm,0.19 +67,sdiv_reg,0.16 +68,sdivcc_imm,0.17 +69,sdivcc_reg,0.17 +70,sethi,0.32 +71,sll_imm,0.33 +72,sll_reg,0.34 +73,smul_imm,0.19 +74,smul_reg,0.16 +75,smulcc_imm,0.17 +76,smulcc_reg,0.17 +77,sra_imm,0.34 +78,sra_reg,0.34 +79,srl_imm,0.33 +80,srl_reg,0.33 +81,st_imm,0.38 +82,st_reg,0.38 +83,stb_imm,0.29 +84,stb_reg,0.29 +85,std_imm,0.34 +86,std_reg,0.34 +87,sth_imm,0.40 +88,sth_reg,0.40 +89,sub_imm,0.46 +90,sub_reg,0.60 +91,subcc_imm,0.66 +92,subcc_reg,0.60 +93,subx_imm,0.46 +94,subx_reg,0.61 +95,subxcc_imm,0.45 +96,subxcc_reg,0.61 +97,swap_imm,0.22 +98,swap_reg,0.22 +99,trap_imm,0.00 +100,trap_reg,0.00 +101,udiv_imm,0.17 +102,udiv_reg,0.17 +103,udivcc_imm,0.17 +104,udivcc_reg,0.17 +105,umul_imm,0.17 +106,umul_reg,0.17 +107,umulcc_imm,0.17 +108,umulcc_reg,0.17 +109,unimplemented,0.00 +110,wry_imm,0.51 +111,wry_reg,0.41 +112,xnor_imm,0.51 +113,xnor_reg,0.52 +114,xnorcc_imm,0.51 +115,xnorcc_reg,0.57 +116,xor_imm,0.41 +117,xor_reg,0.55 +118,xorcc_imm,0.42 +119,xorcc_reg,0.56 diff --git a/pdl/sparc/sparc.ac b/pdl/sparc/sparc.ac new file mode 100644 index 0000000..12bf6fb --- /dev/null +++ b/pdl/sparc/sparc.ac @@ -0,0 +1,52 @@ +/** + * @file sparc.ac + * @author Sandro Rigo + * Marcus Bartholomeu + * Alexandro Baldassin (assembly information) + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Thu, 29 Jun 2006 14:49:07 -0300 + * + * @brief The ArchC SPARC-V8 functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + */ + +AC_ARCH(sparc){ + + ac_mem DM:512M; + ac_regbank RB:256; + ac_regbank REGS:32; + + ac_reg npc; + + ac_reg<1> PSR_icc_n; + ac_reg<1> PSR_icc_z; + ac_reg<1> PSR_icc_v; + ac_reg<1> PSR_icc_c; + + ac_reg PSR; + ac_reg Y; + + ac_reg<8> WIM; + ac_reg<8> CWP; + + ac_reg id; + ac_wordsize 32; + + ARCH_CTOR(sparc){ + + ac_isa("sparc_isa.ac"); + ac_gdb("sparc.xml"); + defines_gdb("defines_gdb"); + set_endian("big"); + }; +}; diff --git a/pdl/sparc/sparc.xml b/pdl/sparc/sparc.xml new file mode 100644 index 0000000..9a4afaf --- /dev/null +++ b/pdl/sparc/sparc.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pdl/sparc/sparc_block.ac b/pdl/sparc/sparc_block.ac new file mode 100644 index 0000000..5d20a0d --- /dev/null +++ b/pdl/sparc/sparc_block.ac @@ -0,0 +1,59 @@ +/** + * @file sparc.ac + * @author Sandro Rigo + * Marcus Bartholomeu + * Alexandro Baldassin (assembly information) + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Thu, 29 Jun 2006 14:49:07 -0300 + * + * @brief The ArchC SPARC-V8 functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + */ + +AC_ARCH(sparc){ + + + ac_tlm2_port MEM:512M; + + ac_icache IC("2w", 128, 32, "wb", "fifo"); + ac_dcache DC("2w", 512, 32, "wt", "fifo"); + + ac_tlm2_intr_port intr_port; + ac_regbank RB:256; + ac_regbank REGS:32; + + ac_reg npc; + + ac_reg<1> PSR_icc_n; + ac_reg<1> PSR_icc_z; + ac_reg<1> PSR_icc_v; + ac_reg<1> PSR_icc_c; + + ac_reg PSR; + ac_reg Y; + + ac_reg<8> WIM; + ac_reg<8> CWP; + + ac_wordsize 32; + ac_fetchsize 32; + + ac_reg id; + ARCH_CTOR(sparc){ + + ac_isa("sparc_isa.ac"); + set_endian("big"); + IC.bindTo(MEM); + DC.bindTo(MEM); + }; +}; diff --git a/pdl/sparc/sparc_gdb_funcs.cpp b/pdl/sparc/sparc_gdb_funcs.cpp new file mode 100644 index 0000000..7d577a9 --- /dev/null +++ b/pdl/sparc/sparc_gdb_funcs.cpp @@ -0,0 +1,70 @@ +/** + * @file sparc_gdb_funcs.cpp + * @author Sandro Rigo + * Marcus Bartholomeu + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:50:50 -0300 + * + * @brief The ArchC SPARC-V8 functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + */ + +#include "sparc.H" + +using namespace sparc_parms; + +int sparc::nRegs(void) { + return 72; +} + +ac_word sparc::reg_read( int reg ) { + /* General Purpose: G, O, L, I */ + if ( ( reg >= 0 ) && ( reg < 32 ) ) { + return REGS[reg]; + } + + /* Y, PSR, WIM, PC, NPC */ + else if ( reg == 64 ) return Y; + else if ( reg == 65 ) return PSR; + else if ( reg == 66 ) return WIM; + else if ( reg == 68 ) return ac_pc; + else if ( reg == 69 ) return npc; + + /* Floating point, TBR, FPSR, CPSR */ + return 0; +} + + +void sparc::reg_write( int reg, ac_word value ) { + /* General Purpose: G, O, L & I regs */ + if ( ( reg >= 0 ) && ( reg < 32 ) ) { + REGS[reg] = value; + } + + /* Y, PSR, WIM, PC, NPC */ + else if ( reg == 64 ) Y = value; + else if ( reg == 65 ) PSR = value; + else if ( reg == 66 ) WIM = value; + else if ( reg == 68 ) ac_pc = value; + else if ( reg == 69 ) npc = value; +} + + +unsigned char sparc::mem_read( unsigned int address ) { + return DATA_PORT->read_byte( address ); +} + + +void sparc::mem_write( unsigned int address, unsigned char byte ) { + DATA_PORT->write_byte( address, byte ); +} diff --git a/pdl/sparc/sparc_isa.ac b/pdl/sparc/sparc_isa.ac new file mode 100644 index 0000000..888cbb5 --- /dev/null +++ b/pdl/sparc/sparc_isa.ac @@ -0,0 +1,912 @@ +/** + * @file sparc_isa.ac + * @author Sandro Rigo + * Marcus Bartholomeu + * Alexandro Baldassin (assembly information) + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Thu, 29 Jun 2006 14:49:07 -0300 + * + * @brief The ArchC SPARC-V8 functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + */ + +AC_ISA(sparc){ + + ac_format Type_F1 = "%op:2 %disp30:30"; + ac_format Type_F2A = "%op:2 %rd:5 %op2:3 %imm22:22"; + ac_format Type_F2B = "%op:2 %an:1 %cond:4 %op2:3 %disp22:22:s"; + ac_format Type_F3A = "%op:2 %rd:5 %op3:6 %rs1:5 %is:1 %asi:8 %rs2:5"; + ac_format Type_F3B = "%op:2 %rd:5 %op3:6 %rs1:5 %is:1 %simm13:13:s"; +/* format for trap instructions */ +/* + ac_format Type_FT = "%op:2 %r1:1 %cond:4 %op2a:6 %rs1:5 %is:1 [%r2a:8 %rs2:5 | %r2b:6 %imm7:7]"; +*/ + + ac_instr call; + ac_instr nop, sethi; + ac_instr ba, bn, bne, be, bg, ble, bge, bl, bgu, bleu, bcc, bcs, + bpos, bneg, bvc, bvs; + + ac_instr ldsb_reg, ldsh_reg, ldub_reg, lduh_reg, ld_reg, ldd_reg, + stb_reg, sth_reg, st_reg, std_reg, ldstub_reg, swap_reg, + sll_reg, srl_reg, sra_reg, add_reg, addcc_reg, addx_reg, + addxcc_reg, sub_reg, subcc_reg, subx_reg, subxcc_reg, + and_reg, andcc_reg, andn_reg, andncc_reg, or_reg, orcc_reg, + orn_reg, orncc_reg, xor_reg, xorcc_reg, xnor_reg, + xnorcc_reg, save_reg, restore_reg, umul_reg, smul_reg, + umulcc_reg, smulcc_reg, mulscc_reg, udiv_reg, udivcc_reg, + sdiv_reg, sdivcc_reg, jmpl_reg, wry_reg; + + ac_instr ldsb_imm, ldsh_imm, ldub_imm, lduh_imm, ld_imm, ldd_imm, + and_imm, andcc_imm, andn_imm, andncc_imm, or_imm, orcc_imm, + orn_imm, orncc_imm, xor_imm, xorcc_imm, xnor_imm, + xnorcc_imm, umul_imm, smul_imm, umulcc_imm, smulcc_imm, + mulscc_imm, udiv_imm, udivcc_imm, sdiv_imm, sdivcc_imm; + + ac_instr stb_imm, sth_imm, st_imm, std_imm, ldstub_imm, swap_imm, + sll_imm, srl_imm, sra_imm, add_imm, addcc_imm, addx_imm, + addxcc_imm, sub_imm, subcc_imm, subx_imm, subxcc_imm, + jmpl_imm, save_imm, restore_imm, rdy, wry_imm; + + ac_instr unimplemented; +/* + ac_instr trap_reg, trap_imm; +*/ + + + ac_asm_map reg { + "%r"[0..31] = [0..31]; + "%g"[0..7] = [0..7]; + "%o"[0..7] = [8..15]; + "%l"[0..7] = [16..23]; + "%i"[0..7] = [24..31]; + "%fp" = 30; + "%sp" = 14; + } + + ac_asm_map anul { + "" = 0; + ",a" = 1; + } + + ac_asm_map cond { + "a" = 8; + "n" = 0; + "ne" = 5; + "e" = 1; + "g" = 10; + "le" = 2; + "ge" = 11; + "l" = 3; + "gu" = 12; + "leu" = 4; + "cc" = 13; + "cs" = 5; + "pos" = 14; + "neg" = 6; + "vc" = 15; + "vs" = 7; + } + + + ISA_CTOR(sparc){ + + ldsb_reg.set_asm("ldsb [%reg + %reg], %reg", rs1, rs2, rd); + ldsb_reg.set_asm("ldsb [%reg], %reg", rs1, rd, rs2="%g0"); + ldsb_reg.set_decoder(op=0x03, op3=0x09, is=0x00); + // ldsb_reg.set_cycles(2); + + ldsh_reg.set_asm("ldsh [%reg + %reg], %reg", rs1, rs2, rd); + ldsh_reg.set_asm("ldsh [%reg], %reg", rs1, rd, rs2="%g0"); + ldsh_reg.set_decoder(op=0x03, op3=0x0A, is=0x00); +// ldsh_reg.set_cycles(2); + + ldub_reg.set_asm("ldub [%reg + %reg], %reg", rs1, rs2, rd); + ldub_reg.set_asm("ldub [%reg], %reg", rs1, rd, rs2="%g0"); + ldub_reg.set_decoder(op=0x03, op3=0x01, is=0x00); +// ldub_reg.set_cycles(2); + + lduh_reg.set_asm("lduh [%reg + %reg], %reg", rs1, rs2, rd); + lduh_reg.set_asm("lduh [%reg], %reg", rs1, rd, rs2="%g0"); + lduh_reg.set_decoder(op=0x03, op3=0x02, is=0x00); +// lduh_reg.set_cycles(2); + + ld_reg.set_asm("ld [%reg + %reg], %reg", rs1, rs2, rd); + ld_reg.set_asm("ld [%reg], %reg", rs1, rd, rs2="%g0"); + ld_reg.set_decoder(op=0x03, op3=0x00, is=0x00); +// ld_reg.set_cycles(2); + + ldd_reg.set_asm("ldd [%reg + %reg], %reg", rs1, rs2, rd); + ldd_reg.set_asm("ldd [%reg], %reg", rs1, rd, rs2="%g0"); + ldd_reg.set_decoder(op=0x03, op3=0x03, is=0x00); + // ldd_reg.set_cycles(2); + + stb_reg.set_asm("stb %reg, [%reg + %reg]", rd, rs1, rs2); + stb_reg.set_asm("stb %reg, [%reg]", rd, rs1, rs2="%g0"); + stb_reg.set_asm("clrb [%reg + %reg]", rd="%g0", rs1, rs2); // synthetic + stb_reg.set_asm("clrb [%reg]", rd="%g0", rs1, rs2="%g0"); // synthetic + stb_reg.set_decoder(op=0x03, op3=0x05, is=0x00); + // stb_reg.set_cycles(3); + + sth_reg.set_asm("sth %reg, [%reg + %reg]", rd, rs1, rs2); + sth_reg.set_asm("sth %reg, [%reg]", rd, rs1, rs2="%g0"); + sth_reg.set_asm("clrh [%reg + %reg]", rd="%g0", rs1, rs2); // synthetic + sth_reg.set_asm("clrh [%reg]", rd="%g0", rs1, rs2="%g0"); // synthetic + sth_reg.set_decoder(op=0x03, op3=0x06, is=0x00); + // sth_reg.set_cycles(3); + + + st_reg.set_asm("st %reg, [%reg + %reg]", rd, rs1, rs2); + st_reg.set_asm("st %reg, [%reg]", rd, rs1, rs2="%g0"); + st_reg.set_asm("clr [%reg + %reg]", rd="%g0", rs1, rs2); // synthetic + st_reg.set_asm("clr [%reg]", rd="%g0", rs1, rs2="%g0"); // synthetic + st_reg.set_decoder(op=0x03, op3=0x04, is=0x00); + // st_reg.set_cycles(3); + + std_reg.set_asm("std %reg, [%reg + %reg]", rd, rs1, rs2); + std_reg.set_asm("std %reg, [%reg]", rd, rs1, rs2="%g0"); + std_reg.set_decoder(op=0x03, op3=0x07, is=0x00); + // std_reg.set_cycles(2); + + ldstub_reg.set_asm("ldstub [%reg + %reg], %reg", rs1, rs2, rd); + ldstub_reg.set_asm("ldstub [%reg], %reg", rs1, rd, rs2="%g0"); + ldstub_reg.set_decoder(op=0x03, op3=0x0D, is=0x00); +// ldstub_reg.set_cycles(2); + + swap_reg.set_asm("swap [%reg + %reg], %reg", rs1, rs2, rd); + swap_reg.set_asm("swap [%reg], %reg", rs1, rd, rs2="%g0"); + swap_reg.set_decoder(op=0x03, op3=0x0F, is=0x00); + // swap_reg.set_cycles(1); + + ldsb_imm.set_asm("ldsb [%reg + \%lo(%exp(low))], %reg", rs1, simm13, rd); + ldsb_imm.set_asm("ldsb [%reg + %imm], %reg", rs1, simm13, rd); + ldsb_imm.set_asm("ldsb [%imm + %reg], %reg", simm13, rs1, rd); + ldsb_imm.set_asm("ldsb [%imm], %reg", simm13, rd, rs1="%g0"); + ldsb_imm.set_decoder(op=0x03, op3=0x09, is = 0x01); + // ldsb_imm.set_cycles(2); + + ldsh_imm.set_asm("ldsh [%reg + \%lo(%exp(low))], %reg", rs1, simm13, rd); + ldsh_imm.set_asm("ldsh [%reg + %imm], %reg", rs1, simm13, rd); + ldsh_imm.set_asm("ldsh [%imm + %reg], %reg", simm13, rs1, rd); + ldsh_imm.set_asm("ldsh [%imm], %reg", simm13, rd, rs1="%g0"); + ldsh_imm.set_decoder(op=0x03, op3=0x0A, is = 0x01); + // ldsh_imm.set_cycles(2); + + ldub_imm.set_asm("ldub [%reg + \%lo(%exp(low))], %reg", rs1, simm13, rd); + ldub_imm.set_asm("ldub [%reg + %imm], %reg", rs1, simm13, rd); + ldub_imm.set_asm("ldub [%imm + %reg], %reg", simm13, rs1, rd); + ldub_imm.set_asm("ldub [%imm], %reg", simm13, rd, rs1="%g0"); + ldub_imm.set_decoder(op=0x03, op3=0x01, is = 0x01); + // ldub_imm.set_cycles(2); + + lduh_imm.set_asm("lduh [%reg + \%lo(%exp(low))], %reg", rs1, simm13, rd); + lduh_imm.set_asm("lduh [%reg + %imm], %reg", rs1, simm13, rd); + lduh_imm.set_asm("lduh [%imm + %reg], %reg", simm13, rs1, rd); + lduh_imm.set_asm("lduh [%imm], %reg", simm13, rd, rs1="%g0"); + lduh_imm.set_decoder(op=0x03, op3=0x02, is = 0x01); + // ldub_imm.set_cycles(2); + + ld_imm.set_asm("ld [%reg + \%lo(%exp(low))], %reg", rs1, simm13, rd); + ld_imm.set_asm("ld [%reg + %imm], %reg", rs1, simm13, rd); + ld_imm.set_asm("ld [%imm + %reg], %reg", simm13, rs1, rd); + ld_imm.set_asm("ld [%imm], %reg", simm13, rd, rs1="%g0"); + ld_imm.set_decoder(op=0x03, op3=0x00, is = 0x01); +// ld_imm.set_cycles(2); + + ldd_imm.set_asm("ldd [%reg + \%lo(%exp(low))], %reg", rs1, simm13, rd); + ldd_imm.set_asm("ldd [%reg + %imm], %reg", rs1, simm13, rd); + ldd_imm.set_asm("ldd [%imm + %reg], %reg", simm13, rs1, rd); + ldd_imm.set_asm("ldd [%imm], %reg", simm13, rd, rs1="%g0"); + ldd_imm.set_decoder(op=0x03, op3=0x03, is = 0x01); +// ldd_imm.set_cycles(2); + + stb_imm.set_asm("stb %reg, [%reg + \%lo(%exp(low))]", rd, rs1, simm13); + stb_imm.set_asm("stb %reg, [%reg + %imm]", rd, rs1, simm13); + stb_imm.set_asm("stb %reg, [%imm + %reg]", rd, simm13, rs1); + stb_imm.set_asm("stb %reg, [%imm]", rd, simm13, rs1="%g0"); + stb_imm.set_asm("clrb [%reg + %imm]", rd="%g0", rs1, simm13); // synthetic + stb_imm.set_asm("clrb [%imm + %reg]", rd="%g0", simm13, rs1); // synthetic + stb_imm.set_asm("clrb [%imm]", rd="%g0", rs1="%g0", simm13); // synthetic + stb_imm.set_decoder(op=0x03, op3=0x05, is = 0x01); + // stb_imm.set_cycles(3); + + sth_imm.set_asm("sth %reg, [%reg + \%lo(%exp(low))]", rd, rs1, simm13); + sth_imm.set_asm("sth %reg, [%reg + %imm]", rd, rs1, simm13); + sth_imm.set_asm("sth %reg, [%imm + %reg]", rd, simm13, rs1); + sth_imm.set_asm("sth %reg, [%imm]", rd, simm13, rs1="%g0"); + sth_imm.set_asm("clrh [%reg + %imm]", rd="%g0", rs1, simm13); // synthetic + sth_imm.set_asm("clrh [%imm + %reg]", rd="%g0", simm13, rs1); // synthetic + sth_imm.set_asm("clrh [%imm]", rd="%g0", rs1="%g0", simm13); // synthetic + sth_imm.set_decoder(op=0x03, op3=0x06, is = 0x01); + // sth_imm.set_cycles(3); + + st_imm.set_asm("st %reg, [%reg + \%lo(%exp(low))]", rd, rs1, simm13); + st_imm.set_asm("st %reg, [%reg + %imm]", rd, rs1, simm13); + st_imm.set_asm("st %reg, [%imm + %reg]", rd, simm13, rs1); + st_imm.set_asm("st %reg, [%imm]", rd, simm13, rs1="%g0"); + st_imm.set_asm("clr [%reg + %imm]", rd="%g0", rs1, simm13); // synthetic + st_imm.set_asm("clr [%imm + %reg]", rd="%g0", simm13, rs1); // synthetic + st_imm.set_asm("clr [%imm]", rd="%g0", rs1="%g0", simm13); // synthetic + st_imm.set_decoder(op=0x03, op3=0x04, is = 0x01); +// st_imm.set_cycles(3); + + std_imm.set_asm("std %reg, [%reg + \%lo(%exp(low))]", rd, rs1, simm13); + std_imm.set_asm("std %reg, [%reg + %imm]", rd, rs1, simm13); + std_imm.set_asm("std %reg, [%imm + %reg]", rd, simm13, rs1); + std_imm.set_asm("std %reg, [%imm]", rd, simm13, rs1="%g0"); + std_imm.set_decoder(op=0x03, op3=0x07, is = 0x01); +// std_imm.set_cycles(3); + + ldstub_imm.set_asm("ldstub [%reg + \%lo(%exp(low))], %reg", rs1, simm13, rd); + ldstub_imm.set_asm("ldstub [%reg + %imm], %reg", rs1, simm13, rd); + ldstub_imm.set_asm("ldstub [%imm + %reg], %reg", simm13, rs1, rd); + ldstub_imm.set_asm("ldstub [%imm], %reg", simm13, rd, rs1="%g0"); + ldstub_imm.set_decoder(op=0x03, op3=0x0D, is = 0x01); + // ldstub_imm.set_cycles(2); + + swap_imm.set_asm("swap [%reg + \%lo(%exp(low))], %reg", rs1, simm13, rd); + swap_imm.set_asm("swap [%reg + %imm], %reg", rs1, simm13, rd); + swap_imm.set_asm("swap [%imm + %reg], %reg", simm13, rs1, rd); + swap_imm.set_asm("swap [%imm], %reg", simm13, rd, rs1="%g0"); + swap_imm.set_decoder(op=0x03, op3=0x0F, is = 0x01); +// swap_imm.set_cycles(1); + + nop.set_asm("nop"); + nop.set_decoder(op=0x00, rd=0x00, op2=0x04, imm22=0x00); + // nop.set_cycles(1); + + sethi.set_asm("sethi %exp, %reg", imm22, rd); + sethi.set_asm("sethi \%hi(%exp(high)), %reg", imm22, rd); + sethi.set_decoder(op=0x00, op2=0x04); + // sethi.set_cycles(1); + + and_reg.set_asm("and %reg, %reg, %reg", rs1, rs2, rd); + and_reg.set_decoder(op=0x02, op3=0x01, is=0x00); +// and_reg.set_cycles(1); + + and_imm.set_asm("and %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + and_imm.set_asm("and %reg, %imm, %reg", rs1, simm13, rd); + and_imm.set_decoder(op=0x02, op3=0x01, is=0x01); +// and_imm.set_cycles(1); + + andcc_reg.set_asm("andcc %reg, %reg, %reg", rs1, rs2, rd); + andcc_reg.set_asm("btst %reg, %reg", rs2, rs1, rd="%g0"); + andcc_reg.set_decoder(op=0x02, op3=0x11, is=0x00); + // andcc_reg.set_cycles(1); + + + andcc_imm.set_asm("andcc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + andcc_imm.set_asm("andcc %reg, %imm, %reg", rs1, simm13, rd); + andcc_imm.set_asm("btst %imm, %reg", simm13, rs1, rd="%g0"); + andcc_imm.set_decoder(op=0x02, op3=0x11, is=0x01); + // andcc_imm.set_cycles(1); + + andn_reg.set_asm("andn %reg, %reg, %reg", rs1, rs2, rd); + andn_reg.set_decoder(op=0x02, op3=0x05, is=0x00); + // andn_reg.set_cycles(1); + + andn_imm.set_asm("andn %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + andn_imm.set_asm("andn %reg, %imm, %reg", rs1, simm13, rd); + andn_imm.set_decoder(op=0x02, op3=0x05, is=0x01); +// andn_imm.set_cycles(1); + + andncc_reg.set_asm("andncc %reg, %reg, %reg", rs1, rs2, rd); + andncc_reg.set_decoder(op=0x02, op3=0x15, is=0x00); +// andncc_reg.set_cycles(1); + + andncc_imm.set_asm("andncc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + andncc_imm.set_asm("andncc %reg, %imm, %reg", rs1, simm13, rd); + andncc_imm.set_decoder(op=0x02, op3=0x15, is=0x01); +// andncc_imm.set_cycles(1); + + or_reg.set_asm("or %reg, %reg, %reg", rs1, rs2, rd); + or_reg.set_asm("clr %reg", rs1="%g0", rs2="%g0", rd); // synthetic + or_reg.set_asm("mov %reg, %reg", rs1="%g0", rs2, rd); // synthetic + or_reg.set_decoder(op=0x02, op3=0x02, is=0x00); + // or_reg.set_cycles(1); + + or_imm.set_asm("or %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + or_imm.set_asm("or %reg, %imm, %reg", rs1, simm13, rd); + or_imm.set_asm("mov %imm, %reg", rs1="%g0", simm13, rd); // synthetic + or_imm.set_decoder(op=0x02, op3=0x02, is=0x01); +// or_imm.set_cycles(1); + + orcc_reg.set_asm("orcc %reg, %reg, %reg", rs1, rs2, rd); + orcc_reg.set_asm("tst %reg", rs1="%g0", rs2, rd="%g0"); // synthetic + orcc_reg.set_decoder(op=0x02, op3=0x12, is=0x00); +// orcc_reg.set_cycles(1); + + orcc_imm.set_asm("orcc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + orcc_imm.set_asm("orcc %reg, %imm, %reg", rs1, simm13, rd); + orcc_imm.set_decoder(op=0x02, op3=0x12, is=0x01); +// orcc_imm.set_cycles(1); + + + orn_reg.set_asm("orn %reg, %reg, %reg", rs1, rs2, rd); + orn_reg.set_decoder(op=0x02, op3=0x06, is=0x00); + // orn_reg.set_cycles(1); + + + orn_imm.set_asm("orn %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + orn_imm.set_asm("orn %reg, %imm, %reg", rs1, simm13, rd); + orn_imm.set_decoder(op=0x02, op3=0x06, is=0x01); + // orn_imm.set_cycles(1); + + + orncc_reg.set_asm("orncc %reg, %reg, %reg", rs1, rs2, rd); + orncc_reg.set_decoder(op=0x02, op3=0x16, is=0x00); + // orncc_reg.set_cycles(1); + + orncc_imm.set_asm("orncc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + orncc_imm.set_asm("orncc %reg, %imm, %reg", rs1, simm13, rd); + orncc_imm.set_decoder(op=0x02, op3=0x16, is=0x01); +// orncc_imm.set_cycles(1); + + xor_reg.set_asm("xor %reg, %reg, %reg", rs1, rs2, rd); + xor_reg.set_decoder(op=0x02, op3=0x03, is=0x00); +// xor_reg.set_cycles(1); + + xor_imm.set_asm("xor %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + xor_imm.set_asm("xor %reg, %imm, %reg", rs1, simm13, rd); + xor_imm.set_decoder(op=0x02, op3=0x03, is=0x01); + // xor_imm.set_cycles(1); + + xorcc_reg.set_asm("xorcc %reg, %reg, %reg", rs1, rs2, rd); + xorcc_reg.set_decoder(op=0x02, op3=0x13, is=0x00); +// xorcc_reg.set_cycles(1); + + xorcc_imm.set_asm("xorcc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + xorcc_imm.set_asm("xorcc %reg, %imm, %reg", rs1, simm13, rd); + xorcc_imm.set_decoder(op=0x02, op3=0x13, is=0x01); +// xorcc_imm.set_cycles(1); + + xnor_reg.set_asm("xnor %reg, %reg, %reg", rs1, rs2, rd); + xnor_reg.set_asm("not %reg, %reg", rs1, rs2="%g0", rd); // synthetic + xnor_reg.set_decoder(op=0x02, op3=0x07, is=0x00); + // xnor_reg.set_cycles(1); + + xnor_imm.set_asm("xnor %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + xnor_imm.set_asm("xnor %reg, %imm, %reg", rs1, simm13, rd); + xnor_imm.set_decoder(op=0x02, op3=0x07, is=0x01); +// xnor_imm.set_cycles(1); + + xnorcc_reg.set_asm("xnorcc %reg, %reg, %reg", rs1, rs2, rd); + xnorcc_reg.set_decoder(op=0x02, op3=0x17, is=0x00); +// xnorcc_reg.set_cycles(1); + + xnorcc_imm.set_asm("xnorcc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + xnorcc_imm.set_asm("xnorcc %reg, %imm, %reg", rs1, simm13, rd); + xnorcc_imm.set_decoder(op=0x02, op3=0x17, is=0x01); +// xnorcc_imm.set_cycles(1); + + sll_reg.set_asm("sll %reg, %reg, %reg", rs1, rs2, rd); + sll_reg.set_decoder(op=0x02, op3=0x25, is=0x00); +// sll_reg.set_cycles(1); + + sll_imm.set_asm("sll %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + sll_imm.set_asm("sll %reg, %imm, %reg", rs1, simm13, rd); + sll_imm.set_decoder(op=0x02, op3=0x25, is=0x01); +// sll_imm.set_cycles(1); + + srl_reg.set_asm("srl %reg, %reg, %reg", rs1, rs2, rd); + srl_reg.set_decoder(op=0x02, op3=0x26, is=0x00); +// srl_reg.set_cycles(1); + + srl_imm.set_asm("srl %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + srl_imm.set_asm("srl %reg, %imm, %reg", rs1, simm13, rd); + srl_imm.set_decoder(op=0x02, op3=0x26, is=0x01); +// srl_imm.set_cycles(1); + + sra_reg.set_asm("sra %reg, %reg, %reg", rs1, rs2, rd); + sra_reg.set_decoder(op=0x02, op3=0x27, is=0x00); +// sra_reg.set_cycles(1); + + + sra_imm.set_asm("sra %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + sra_imm.set_asm("sra %reg, %imm, %reg", rs1, simm13, rd); + sra_imm.set_decoder(op=0x02, op3=0x27, is=0x01); +// sra_imm.set_cycles(1); + + + add_reg.set_asm("add %reg, %reg, %reg", rs1, rs2, rd); + add_reg.set_decoder(op=0x02, op3=0x00, is=0x00); +// add_reg.set_cycles(4); + + add_imm.set_asm("add %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); // gas + add_imm.set_asm("add %reg, %imm, %reg", rs1, simm13, rd); + add_imm.set_decoder(op=0x02, op3=0x00, is=0x01); + // add_imm.set_cycles(4); + + addcc_reg.set_asm("addcc %reg, %reg, %reg", rs1, rs2, rd); + addcc_reg.set_asm("btst %reg, %reg", rs1, rs2, rd="%g0"); // synthetic + addcc_reg.set_decoder(op=0x02, op3=0x10, is=0x00); +// addcc_reg.set_cycles(4); + + addcc_imm.set_asm("addcc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + addcc_imm.set_asm("addcc %reg, %imm, %reg", rs1, simm13, rd); + addcc_imm.set_asm("btst %reg, %imm", rs1, simm13, rd="%g0"); // synthetic + addcc_imm.set_decoder(op=0x02, op3=0x10, is=0x01); + // addcc_imm.set_cycles(4); + + addx_reg.set_asm("addx %reg, %reg, %reg", rs1, rs2, rd); + addx_reg.set_decoder(op=0x02, op3=0x08, is=0x00); +// addx_reg.set_cycles(4); + + addx_imm.set_asm("addx %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + addx_imm.set_asm("addx %reg, %imm, %reg", rs1, simm13, rd); + addx_imm.set_decoder(op=0x02, op3=0x08, is=0x01); +// addx_imm.set_cycles(4); + + addxcc_reg.set_asm("addxcc %reg, %reg, %reg", rs1, rs2, rd); + addxcc_reg.set_decoder(op=0x02, op3=0x18, is=0x00); + // addxcc_reg.set_cycles(4); + + addxcc_imm.set_asm("addxcc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + addxcc_imm.set_asm("addxcc %reg, %imm, %reg", rs1, simm13, rd); + addxcc_imm.set_decoder(op=0x02, op3=0x18, is=0x01); + // addxcc_imm.set_cycles(4); + + sub_reg.set_asm("sub %reg, %reg, %reg", rs1, rs2, rd); + sub_reg.set_asm("neg %reg, %reg", rs1="%g0", rs2, rd); // synthetic + sub_reg.set_decoder(op=0x02, op3=0x04, is=0x00); + // sub_reg.set_cycles(4); + + sub_imm.set_asm("sub %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + sub_imm.set_asm("sub %reg, %imm, %reg", rs1, simm13, rd); + sub_imm.set_decoder(op=0x02, op3=0x04, is=0x01); + + // sub_imm.set_cycles(4); + subcc_reg.set_asm("subcc %reg, %reg, %reg", rs1, rs2, rd); + subcc_reg.set_asm("cmp %reg, %reg", rs1, rs2, rd="%g0"); // synthetic + subcc_reg.set_decoder(op=0x02, op3=0x14, is=0x00); + + // subcc_reg.set_cycles(4); + subcc_imm.set_asm("subcc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + subcc_imm.set_asm("subcc %reg, %imm, %reg", rs1, simm13, rd); + subcc_imm.set_asm("cmp %reg, %imm", rs1, simm13, rd="%g0"); // synthetic + subcc_imm.set_decoder(op=0x02, op3=0x14, is=0x01); + +// subcc_imm.set_cycles(4); + subx_reg.set_asm("subx %reg, %reg, %reg", rs1, rs2, rd); + subx_reg.set_decoder(op=0x02, op3=0x0C, is=0x00); + + // subx_reg.set_cycles(4); + subx_imm.set_asm("subx %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + subx_imm.set_asm("subx %reg, %imm, %reg", rs1, simm13, rd); + subx_imm.set_decoder(op=0x02, op3=0x0C, is=0x01); + // subx_imm.set_cycles(4); + + subxcc_reg.set_asm("subxcc %reg, %reg, %reg", rs1, rs2, rd); + subxcc_reg.set_decoder(op=0x02, op3=0x1C, is=0x00); + // subxcc_reg.set_cycles(4); + + subxcc_imm.set_asm("subxcc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + subxcc_imm.set_asm("subxcc %reg, %imm, %reg", rs1, simm13, rd); + subxcc_imm.set_decoder(op=0x02, op3=0x1C, is=0x01); +// subxcc_imm.set_cycles(4); + + umulcc_imm.set_asm("umulcc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + umulcc_imm.set_asm("umulcc %reg, %imm, %reg", rs1, simm13, rd); + umulcc_imm.set_decoder(op=0x02, op3=0x1A, is=0x01); +// umulcc_imm.set_cycles(4); + + umul_imm.set_asm("umul %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + umul_imm.set_asm("umul %reg, %imm, %reg", rs1, simm13, rd); + umul_imm.set_decoder(op=0x02, op3=0x0A, is=0x01); + // umul_imm.set_cycles(4); + + umulcc_reg.set_asm("umulcc %reg, %reg, %reg", rs1, rs2, rd); + umulcc_reg.set_decoder(op=0x02, op3=0x1A, is=0x00); +// umulcc_reg.set_cycles(4); + + umul_reg.set_asm("umul %reg, %reg, %reg", rs1, rs2, rd); + umul_reg.set_asm("umul %reg, %reg, \%g0", rs1, rs2, rd="%g0"); + umul_reg.set_decoder(op=0x02, op3=0x0A, is=0x00); +// umul_reg.set_cycles(4); + + smul_imm.set_asm("smul %reg, %imm, %reg", rs1, simm13, rd); + smul_imm.set_decoder(op=0x02, op3=0x0B, is=0x01); + // smul_imm.set_cycles(4); + + smulcc_imm.set_asm("smulcc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + smulcc_imm.set_asm("smulcc %reg, %imm, %reg", rs1, simm13, rd); + smulcc_imm.set_decoder(op=0x02, op3=0x1B, is=0x01); + // smulcc_imm.set_cycles(4); + + smul_reg.set_asm("smul %reg, %reg, %reg", rs1, rs2, rd); + smul_reg.set_decoder(op=0x02, op3=0x0B, is=0x00); +// smul_reg.set_cycles(4); + + smulcc_reg.set_asm("smulcc %reg, %reg, %reg", rs1, rs2, rd); + smulcc_reg.set_decoder(op=0x02, op3=0x1B, is=0x00); + // smulcc_reg.set_cycles(1); + + mulscc_reg.set_asm("mulscc %reg, %reg, %reg", rs1, rs2, rd); + mulscc_reg.set_decoder(op=0x02, op3=0x24, is=0x00); + // mulscc_reg.set_cycles(1); + + mulscc_imm.set_asm("mulscc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + mulscc_imm.set_asm("mulscc %reg, %imm, %reg", rs1, simm13, rd); + mulscc_imm.set_decoder(op=0x02, op3=0x24, is=0x01); + // mulscc_imm.set_cycles(1); + + udiv_reg.set_asm("udiv %reg, %reg, %reg", rs1, rs2, rd); + udiv_reg.set_decoder(op=0x02, op3=0x0E, is=0x00); + // udiv_reg.set_cycles(17); + + udivcc_reg.set_asm("smul %reg, %reg, %reg", rs1, rs2, rd); + udivcc_reg.set_decoder(op=0x02, op3=0x1E, is=0x00); + // udivcc_reg.set_cycles(17); + + udiv_imm.set_asm("udiv %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + udiv_imm.set_asm("udiv %reg, %imm, %reg", rs1, simm13, rd); + udiv_imm.set_decoder(op=0x02, op3=0x0E, is=0x01); + // udiv_imm.set_cycles(17); + + udivcc_imm.set_asm("udivcc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + udivcc_imm.set_asm("udivcc %reg, %imm, %reg", rs1, simm13, rd); + udivcc_imm.set_decoder(op=0x02, op3=0x1E, is=0x01); +// udivcc_imm.set_cycles(17); + + sdiv_reg.set_asm("sdiv %reg, %reg, %reg", rs1, rs2, rd); + sdiv_reg.set_decoder(op=0x02, op3=0x0F, is=0x00); + // sdiv_reg.set_cycles(17); + + sdivcc_reg.set_asm("sdivcc %reg, %reg, %reg", rs1, rs2, rd); + sdivcc_reg.set_decoder(op=0x02, op3=0x1F, is=0x00); + // sdivcc_reg.set_cycles(17); + + sdiv_imm.set_asm("sdiv %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + sdiv_imm.set_asm("sdiv %reg, %imm, %reg", rs1, simm13, rd); + sdiv_imm.set_decoder(op=0x02, op3=0x0F, is=0x01); +// sdiv_imm.set_cycles(17); + + sdivcc_imm.set_asm("sdivcc %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + sdivcc_imm.set_asm("sdivcc %reg, %imm, %reg", rs1, simm13, rd); + sdivcc_imm.set_decoder(op=0x02, op3=0x1F, is=0x01); + // sdivcc_imm.set_cycles(17); + + save_reg.set_asm("save %reg, %reg, %reg", rs1, rs2, rd); + save_reg.set_asm("save", rs1="%g0", rs2="%g0", rd="%g0"); // synthetic + save_reg.set_decoder(op=0x02, op3=0x3C, is=0x00); + // save_reg.set_cycles(1); + + save_imm.set_asm("save %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + save_imm.set_asm("save %reg, %imm, %reg", rs1, simm13, rd); + save_imm.set_decoder(op=0x02, op3=0x3C, is=0x01); + // save_imm.set_cycles(1); + + restore_reg.set_asm("restore %reg, %reg, %reg", rs1, rs2, rd); + restore_reg.set_asm("restore", rs1="%g0", rs2="%g0", rd="%g0"); // synthetic + restore_reg.set_decoder(op=0x02, op3=0x3D, is=0x00); +// restore_reg.set_cycles(1); + + restore_imm.set_asm("restore %reg, \%lo(%exp(low)), %reg", rs1, simm13, rd); + restore_imm.set_asm("restore %reg, %imm, %reg", rs1, simm13, rd); + restore_imm.set_decoder(op=0x02, op3=0x3D, is=0x01); + // restore_imm.set_cycles(1); + + ba.set_asm("b %exp(pcrel)", disp22, an=0); + ba.set_asm("ba %exp(pcrel)", disp22, an=0); + ba.set_asm("ba,a %exp(pcrel)", disp22, an=1); + ba.set_decoder(op=0x00, cond=0x08, op2=0x02); + // ba.set_cycles(1); + + bn.set_asm("bn %exp(pcrel)", disp22, an=0); + bn.set_asm("bn,a %exp(pcrel)", disp22, an=1); + bn.set_decoder(op=0x00, cond=0x00, op2=0x02); + // bn.set_cycles(1); + + bne.set_asm("bne%[anul] %exp(pcrel)", an, disp22); + bne.set_asm("bnz%[anul] %exp(pcrel)", an, disp22); + bne.set_decoder(op=0x00, cond=0x09, op2=0x02); + // bne.set_cycles(1); + + be.set_asm("be%[anul] %exp(pcrel)", an, disp22); + be.set_asm("bz%[anul] %exp(pcrel)", an, disp22); + be.set_decoder(op=0x00, cond=0x01, op2=0x02); +// be.set_cycles(1); + + bg.set_asm("bg%[anul] %exp(pcrel)", an, disp22); + bg.set_decoder(op=0x00, cond=0x0A, op2=0x02); + // bg.set_cycles(1); + + ble.set_asm("ble%[anul] %exp(pcrel)", an, disp22); + ble.set_decoder(op=0x00, cond=0x02, op2=0x02); + // ble.set_cycles(1); + + bge.set_asm("bge%[anul] %exp(pcrel)", an, disp22); + bge.set_decoder(op=0x00, cond=0x0B, op2=0x02); + // bge.set_cycles(1); + + bl.set_asm("bl%[anul] %exp(pcrel)", an, disp22); + bl.set_decoder(op=0x00, cond=0x03, op2=0x02); +// bl.set_cycles(1); + + bgu.set_asm("bgu%[anul] %exp(pcrel)", an, disp22); + bgu.set_decoder(op=0x00, cond=0x0C, op2=0x02); + // bgu.set_cycles(1); + + bleu.set_asm("bleu%[anul] %exp(pcrel)", an, disp22); + bleu.set_decoder(op=0x00, cond=0x04, op2=0x02); + // bleu.set_cycles(1); + + bcc.set_asm("bcc%anul %exp(pcrel)", an, disp22); + bcc.set_asm("bgeu%[anul] %exp(pcrel)", an, disp22); + bcc.set_decoder(op=0x00, cond=0x0D, op2=0x02); +// bcc.set_cycles(1); + + bcs.set_asm("bcs%[anul] %exp(pcrel)", an, disp22); + bcs.set_asm("blu%[anul] %exp(pcrel)", an, disp22); + bcs.set_decoder(op=0x00, cond=0x05, op2=0x02); +// bcs.set_cycles(1); + + bpos.set_asm("bpos%[anul] %exp(pcrel)", an, disp22); + bpos.set_decoder(op=0x00, cond=0x0E, op2=0x02); +// bpos.set_cycles(1); + + bneg.set_asm("bneg%[anul] %exp(pcrel)", an, disp22); + bneg.set_decoder(op=0x00, cond=0x06, op2=0x02); + // bneg.set_cycles(1); + + bvc.set_asm("bvc%[anul] %exp(pcrel)", an, disp22); + bvc.set_decoder(op=0x00, cond=0x0F, op2=0x02); +// bvc.set_cycles(1); + + bvs.set_asm("bvs%[anul] %exp(pcrel)", an, disp22); + bvs.set_decoder(op=0x00, cond=0x07, op2=0x02); +// bvs.set_cycles(1); + + call.set_asm("call %exp(pcrel)", disp30); + call.set_asm("call %exp(pcrel)", disp30); // compiler_info related information + call.set_decoder(op=0x01); + + // call.set_cycles(1); + rdy.set_asm("rd \%y, %reg", rs1=0, rd); + rdy.set_asm("mov \%y, %reg", rs1=0, rd); + rdy.set_decoder(op=0x02, op3=0x28); +// rdy.set_cycles(1); + + jmpl_reg.set_asm("jmp %reg", rs1, rs2=0, rd=0); // gas + jmpl_reg.set_asm("call %reg", rs1, rs2=0, rd=15); // gas + jmpl_reg.set_asm("jmpl %reg + %reg, %reg", rs1, rs2, rd); + jmpl_reg.set_asm("jmp %reg + %reg", rs1, rs2, rd="%g0"); // synthetic + jmpl_reg.set_asm("call %reg + %reg", rs1, rs2, rd="%o7"); // synthetic + jmpl_reg.set_decoder(op=0x02, op3=0x38, is=0x00); + // jmpl_reg.set_cycles(1); + + jmpl_imm.set_asm("jmpl %reg + %imm, %reg", rs1, simm13, rd); + jmpl_imm.set_asm("jmpl %imm + %reg, %reg", simm13, rs1, rd); + jmpl_imm.set_asm("jmp %reg + %imm", rs1, simm13, rd="%g0"); // synthetic + jmpl_imm.set_asm("call %reg + %imm", rs1, simm13, rd="%o7"); // synthetic + jmpl_imm.set_asm("ret", rs1="%i7", simm13=8, rd="%g0"); // synthetic + jmpl_imm.set_asm("retl", rs1="%o7", simm13=8, rd="%g0"); // synthetic + jmpl_imm.set_decoder(op=0x02, op3=0x38, is=0x01); + // jmpl_imm.set_cycles(1); + + wry_reg.set_asm("wr %reg, \%y", rs1, rd=0, rs2=0); + wry_reg.set_asm("wr %reg, %reg, \%y", rs1, rs2, rd=0); + wry_reg.set_asm("mov %reg, \%y", rs1="%g0", rs2, rd=0); + wry_reg.set_decoder(op=0x02, op3=0x30, is=0x00); +// wry_reg.set_cycles(1); + + wry_imm.set_asm("wr %reg, %imm, \%y", rs1, simm13, rd=0); + wry_imm.set_asm("mov %imm, \%y", simm13, rs1="%g0", rd=0); + wry_imm.set_decoder(op=0x02, op3=0x30, is=0x01); + // wry_imm.set_cycles(1); + +/* + trap_imm.set_asm("t%cond %imm", cond, imm7, r1=0); + trap_imm.set_decoder(op=0x02, is=1, op2a=0x3A); + // trap_imm.set_cycles(1); + + trap_reg.set_asm("t%cond %reg", cond, rs2); + trap_reg.set_decoder(op=0x02, is=0, op2a=0x3A); + // trap_reg.set_cycles(1); +*/ + + unimplemented.set_asm("unimp %imm", imm22); + unimplemented.set_decoder(op=0x00,rd=0x00,op2=0x00); + + pseudo_instr("not %reg") { + "xnor %0, \%g0, %0"; + } + + pseudo_instr("neg %reg") { + "sub \%g0, %0, %0"; + } + + pseudo_instr("inc %reg") { + "add %0, 1, %0"; + } + + pseudo_instr("inc %imm, %reg") { + "add %1, %0, %1"; + } + + pseudo_instr("inccc %reg") { + "addcc %0, 1, %0"; + } + + pseudo_instr("inccc %imm, %reg") { + "addcc %1, %0, %1"; + } + + pseudo_instr("dec %reg") { + "sub %0, 1, %0"; + } + + pseudo_instr("dec %imm, %reg") { + "sub %1, %0, %1"; + } + + pseudo_instr("deccc %reg") { + "subcc %0, 1, %0"; + } + + pseudo_instr("deccc %imm, %reg") { + "subcc %0, %1, %0"; + } + + pseudo_instr("set %addr, %reg") { + "sethi \%hi(%0), %1"; + "or %1, \%lo(%0), %1"; + } + + pseudo_instr("set %imm, %reg") { // only valid when -4096 <= imm <= 4095 + "or \%g0, %0, %1"; + } + + pseudo_instr("bset %reg, %reg") { + "or %1, %0, %1"; + } + + pseudo_instr("bset %imm, %reg") { + "or %1, %0, %1"; + } + + pseudo_instr("bclr %reg, %reg") { + "andn %1, %0, %1"; + } + + pseudo_instr("bclr %imm, %reg") { + "andn %1, %0, %1"; + } + + pseudo_instr("btog %reg, %reg") { + "xor %1, %0, %1"; + } + + pseudo_instr("btog %imm, %reg") { + "xor %1, %0, %1"; + } + + pseudo_instr("call %exp, %imm") { + "call %0"; + } + + pseudo_instr("call %reg, %imm") { + "call %0"; + } + + +/********************************************************/ +/* Optional properties to optimize compiled simulation */ +/********************************************************/ + + call.is_jump(ac_pc+(disp30<<2)); + call.delay(1); + call.behavior(writeReg(15, ac_pc);); + + jmpl_reg.is_jump(readReg(rs1) + readReg(rs2) - ac_start_addr); + jmpl_reg.delay(1); + jmpl_reg.behavior(writeReg(rd, ac_pc);); + + jmpl_imm.is_jump(readReg(rs1) + simm13); + jmpl_imm.delay(1); + jmpl_imm.behavior(writeReg(rd, ac_pc);); + + + + ba.is_branch(ac_pc+(disp22<<2)); + ba.cond(1); + ba.delay(1); + ba.delay_cond(!an); + + bn.is_branch(ac_pc+(disp22<<2)); + bn.cond(0); + bn.delay(1); + bn.delay_cond(!an); + + bne.is_branch(ac_pc+(disp22<<2)); + bne.cond(!PSR_icc_z); + bne.delay(1); + bne.delay_cond(!PSR_icc_z || !an); + + be.is_branch(ac_pc+(disp22<<2)); + be.cond(PSR_icc_z); + be.delay(1); + be.delay_cond(PSR_icc_z || !an); + + bg.is_branch(ac_pc+(disp22<<2)); + bg.cond(!(PSR_icc_z ||(PSR_icc_n ^PSR_icc_v))); + bg.delay(1); + bg.delay_cond(!(PSR_icc_z ||(PSR_icc_n ^PSR_icc_v)) || !an); + + ble.is_branch(ac_pc+(disp22<<2)); + ble.cond(PSR_icc_z ||(PSR_icc_n ^PSR_icc_v)); + ble.delay(1); + ble.delay_cond(PSR_icc_z ||(PSR_icc_n ^PSR_icc_v) || !an); + + bge.is_branch(ac_pc+(disp22<<2)); + bge.cond(!(PSR_icc_n ^PSR_icc_v)); + bge.delay(1); + bge.delay_cond(!(PSR_icc_n ^PSR_icc_v) || !an); + + bl.is_branch(ac_pc+(disp22<<2)); + bl.cond(PSR_icc_n ^PSR_icc_v); + bl.delay(1); + bl.delay_cond(PSR_icc_n ^PSR_icc_v || !an); + + bgu.is_branch(ac_pc+(disp22<<2)); + bgu.cond(!(PSR_icc_c ||PSR_icc_z)); + bgu.delay(1); + bgu.delay_cond(!(PSR_icc_c ||PSR_icc_z) || !an); + + bleu.is_branch(ac_pc+(disp22<<2)); + bleu.cond(PSR_icc_c ||PSR_icc_z); + bleu.delay(1); + bleu.delay_cond(PSR_icc_c ||PSR_icc_z || !an); + + bcc.is_branch(ac_pc+(disp22<<2)); + bcc.cond(!PSR_icc_c); + bcc.delay(1); + bcc.delay_cond(!PSR_icc_c || !an); + + bcs.is_branch(ac_pc+(disp22<<2)); + bcs.cond(PSR_icc_c); + bcs.delay(1); + bcs.delay_cond(PSR_icc_c || !an); + + bpos.is_branch(ac_pc+(disp22<<2)); + bpos.cond(!PSR_icc_n); + bpos.delay(1); + bpos.delay_cond(!PSR_icc_n || !an); + + bneg.is_branch(ac_pc+(disp22<<2)); + bneg.cond(PSR_icc_n); + bneg.delay(1); + bneg.delay_cond(PSR_icc_n || !an); + + bvc.is_branch(ac_pc+(disp22<<2)); + bvc.cond(!PSR_icc_v); + bvc.delay(1); + bvc.delay_cond(!PSR_icc_v || !an); + + bvs.is_branch(ac_pc+(disp22<<2)); + bvs.cond(PSR_icc_v); + bvs.delay(1); + bvs.delay_cond(PSR_icc_v || !an); + + }; +}; + + + + + + + + + + diff --git a/pdl/sparc/sparc_isa.cpp b/pdl/sparc/sparc_isa.cpp new file mode 100644 index 0000000..6fe5117 --- /dev/null +++ b/pdl/sparc/sparc_isa.cpp @@ -0,0 +1,1607 @@ +/** + * @file sparc_isa.cpp + * @author Sandro Rigo + * Marcus Bartholomeu + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:50:50 -0300 + * + * @brief The ArchC SPARC-V8 functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + */ + +//IMPLEMENTATION NOTES: +// 1. readReg(RB, 0) returns always 0, so in condition codes instructions +// a temporary is necessary or else it will read 0 +// 2. Register windows: 4 bits for window (16 windows) + 4 bits for register = 8 bit +// using char type + +#include "sparc_isa.H" +#include "sparc_isa_init.cpp" +#include "sparc_bhv_macros.H" + +//If you want debug information for this model, uncomment next line +//#define DEBUG_MODEL +#include "ac_debug_model.H" +#include "ansi-colors.h" + +// Namespace for sparc types. +using namespace sparc_parms; + +static int processors_started = 0; +#define DEFAULT_STACK_SIZE (256*1024) + +#ifdef SLEEP_AWAKE_MODE +/*********************************************************************************/ +/* SLEEP / AWAKE mode control */ +/* INTR_REG may store 1 (AWAKE MODE) or 0 (SLEEP MODE) */ +/* if intr_reg == 0, the simulator will be suspended until it receives a */ +/* interruption 1 */ +/*********************************************************************************/ +#define test_sleep() { if (intr_reg.read() == 0) ac_wait(); } +#else +#define test_sleep() {} +#endif + +//!Generic instruction behavior method. +void ac_behavior( instruction ) +{ + + test_sleep(); + + dbg_printf("----- PC=0x%x NPC=0x%x ----- #executed=%lld\n", (unsigned) ac_pc.read(), (unsigned)npc.read(), ac_instr_counter); +} + +//! Instruction Format behavior methods. +void ac_behavior( Type_F1 ){} +void ac_behavior( Type_F2A ){} +void ac_behavior( Type_F2B ){} +void ac_behavior( Type_F3A ){} +void ac_behavior( Type_F3B ){} +void ac_behavior( Type_FT ){} + +//!User declared functions. + +#define writeReg(addr, val) REGS[addr] = (addr)? ac_word(val) : 0 +#define readReg(addr) (int)(REGS[addr]) + + +inline void update_pc(bool branch, bool taken, bool b_always, bool annul, ac_word addr, ac_reg& ac_pc, ac_reg& npc) +{ + //Reference book: "Sparc Architecture, Assembly Language Programing, and C" + // Author: Richard P. Paul. Prentice Hall, Second Edition. Page 87 + + // If (not to execute next instruction) + + if (branch && (!taken ||b_always) && annul) { + if (taken) { + npc = addr; + dbg_printf(CB_RED "Branch Taken" C_RESET LF); + } + else { + npc+=4; + } + dbg_printf("Delay instruction annuled\n"); + ac_pc = npc; + npc+=4; + } + // else (next instruction will be executed) + else { + ac_pc = npc; + if (taken) { + npc = addr; + dbg_printf(CB_RED "Branch Taken" C_RESET LF); + } + else { + npc+=4; + } + } + +} + + +//Use updatepc() only when needed +#ifdef NO_NEED_PC_UPDATE +#define update_pc(a,b,c,d,e, ac_pc, npc) /*nothing*/ +#endif + + +void trap_reg_window_overflow(ac_memory* DATA_PORT, ac_regbank<256, ac_word, ac_Dword>& RB, ac_reg& WIM) +{ + WIM = (WIM-0x10); + int sp = (WIM+14) & 0xFF; + int l0 = (WIM+16) & 0xFF; + for (int i=0; i<16; i++) { + DATA_PORT->write(RB.read(sp)+(i<<2), RB.read(l0+i)); + } +} + + +void trap_reg_window_underflow(ac_memory* DATA_PORT, ac_regbank<256, ac_word, ac_Dword>& RB, ac_reg& WIM) +{ + int sp = (WIM+14) & 0xFF; + int l0 = (WIM+16) & 0xFF; + for (int i=0; i<16; i++) { + RB.write(l0+i, DATA_PORT->read(RB.read(sp)+(i<<2))); + } + WIM = (WIM+0x10); +} + + +//!Function called before simulation start +void ac_behavior(begin) +{ + dbg_printf("@@@ begin behavior @@@\n"); + REGS[0] = 0; //writeReg can't initialize register 0 + npc = ac_pc + 4; + + CWP = 0xF0; + /* sp for multi-core platforms */ + writeReg(14,AC_RAM_END - 1024 - processors_started++ * DEFAULT_STACK_SIZE); + +} + +//!Function called after simulation end +void ac_behavior(end) +{ + dbg_printf("@@@ end behavior @@@\n"); +} + + +/************************************************** + * Instructions Behaviors * + **************************************************/ + +//!Instruction call behavior method. +void ac_behavior( call ) +{ + dbg_printf("call 0x%x\n", ac_pc+(disp30<<2)); + writeReg(15, ac_pc); //saves ac_pc in %o7(or %r15) + update_pc(1,1,1,0, ac_pc+(disp30<<2), ac_pc, npc); +}; + +//!Instruction nop behavior method. +void ac_behavior( nop ) +{ + dbg_printf("nop\n"); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction sethi behavior method. +void ac_behavior( sethi ) +{ + dbg_printf("sethi 0x%x,r%d\n", imm22, rd); + writeReg(rd, (imm22 << 10)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction ba behavior method. +void ac_behavior( ba ) +{ + dbg_printf("ba 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1,1,1,an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +///!Instruction bn behavior method. +void ac_behavior( bn ) +{ + dbg_printf("bn 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1,0,0,an,0, ac_pc, npc); +}; + +///!Instruction bne behavior method. +void ac_behavior( bne ) +{ + dbg_printf("bne 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1, !PSR_icc_z, 0, an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +///!Instruction be behavior method. +void ac_behavior( be ) +{ + dbg_printf("be 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1, PSR_icc_z, 0, an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +///!Instruction bg behavior method. +void ac_behavior( bg ) +{ + dbg_printf("bg 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1, !(PSR_icc_z ||(PSR_icc_n ^PSR_icc_v)), 0, an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +///!Instruction ble behavior method. +void ac_behavior( ble ) +{ + dbg_printf("ble 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1, PSR_icc_z ||(PSR_icc_n ^PSR_icc_v), 0, an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +///!Instruction bge behavior method. +void ac_behavior( bge ) +{ + dbg_printf("bge 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1, !(PSR_icc_n ^PSR_icc_v), 0, an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +///!Instruction bl behavior method. +void ac_behavior( bl ) +{ + dbg_printf("bl 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1, PSR_icc_n ^PSR_icc_v, 0, an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +///!Instruction bgu behavior method. +void ac_behavior( bgu ) +{ + dbg_printf("bgu 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1, !(PSR_icc_c ||PSR_icc_z), 0, an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +///!Instruction bleu behavior method. +void ac_behavior( bleu ) +{ + dbg_printf("bleu 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1, PSR_icc_c ||PSR_icc_z, 0, an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +///!Instruction bcc behavior method. +void ac_behavior( bcc ) +{ + dbg_printf("bcc 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1, !PSR_icc_c, 0, an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +///!Instruction bcs behavior method. +void ac_behavior( bcs ) +{ + dbg_printf("bcs 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1, PSR_icc_c, 0, an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +///!Instruction bpos behavior method. +void ac_behavior( bpos ) +{ + dbg_printf("bpos 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1, !PSR_icc_n, 0, an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +///!Instruction bneg behavior method. +void ac_behavior( bneg ) +{ + dbg_printf("bneg 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1, PSR_icc_n, 0, an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +///!Instruction bvc behavior method. +void ac_behavior( bvc ) +{ + dbg_printf("bvc 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1, !PSR_icc_v, 0, an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +///!Instruction bvs behavior method. +void ac_behavior( bvs ) +{ + dbg_printf("bvs 0x%x\n", ac_pc+(disp22<<2)); + update_pc(1, PSR_icc_v, 0, an, ac_pc+(disp22<<2), ac_pc, npc); +}; + +//!Instruction ldsb_reg behavior method. +void ac_behavior( ldsb_reg ) +{ + dbg_printf("ldsb_reg [r%d+r%d], r%d\n", rs1, rs2, rd); + writeReg(rd, (int)(char) DATA_PORT->read_byte(readReg(rs1) + readReg(rs2))); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction ldsh_reg behavior method. +void ac_behavior( ldsh_reg ) +{ + dbg_printf("ldsh_reg [r%d+r%d], r%d\n", rs1, rs2, rd); + writeReg(rd, (int)(short) DATA_PORT->read_half(readReg(rs1) + readReg(rs2))); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction ldub_reg behavior method. +void ac_behavior( ldub_reg ) +{ + dbg_printf("ldub_reg [r%d+r%d], r%d\n", rs1, rs2, rd); + writeReg(rd, DATA_PORT->read_byte(readReg(rs1) + readReg(rs2))); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction lduh_reg behavior method. +void ac_behavior( lduh_reg ) +{ + dbg_printf("lduh_reg [r%d+r%d], r%d\n", rs1, rs2, rd); + writeReg(rd, DATA_PORT->read_half(readReg(rs1) + readReg(rs2))); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction ld_reg behavior method. +void ac_behavior( ld_reg ) +{ + dbg_printf("ld_reg [r%d+r%d], r%d\n", rs1, rs2, rd); + writeReg(rd, DATA_PORT->read(readReg(rs1) + readReg(rs2))); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction ldd_reg behavior method. +void ac_behavior( ldd_reg ) +{ + dbg_printf("ldd_reg [r%d+r%d], r%d\n", rs1, rs2, rd); + int tmp = DATA_PORT->read(readReg(rs1) + readReg(rs2) + 4); + writeReg(rd, DATA_PORT->read(readReg(rs1) + readReg(rs2) )); + writeReg(rd+1, tmp); + dbg_printf("Result = 0x%x\n", readReg(rd)); + dbg_printf("Result = 0x%x\n", readReg(rd+1)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction stb_reg behavior method. +void ac_behavior( stb_reg ) +{ + dbg_printf("stb_reg r%d, [r%d+r%d]\n", rd, rs1, rs2); + DATA_PORT->write_byte(readReg(rs1) + readReg(rs2), (char) readReg(rd)); + dbg_printf("Result = 0x%x\n", (char) readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction sth_reg behavior method. +void ac_behavior( sth_reg ) +{ + dbg_printf("sth_reg r%d, [r%d+r%d]\n", rd, rs1, rs2); + DATA_PORT->write_half(readReg(rs1) + readReg(rs2), (short) readReg(rd)); + dbg_printf("Result = 0x%x\n", (short) readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction st_reg behavior method. +void ac_behavior( st_reg ) +{ + dbg_printf("st_reg r%d, [r%d+r%d]\n", rd, rs1, rs2); + DATA_PORT->write(readReg(rs1) + readReg(rs2), readReg(rd)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction std_reg behavior method. +void ac_behavior( std_reg ) +{ + dbg_printf("std_reg r%d, [r%d+r%d]\n", rd, rs1, rs2); + DATA_PORT->write(readReg(rs1) + readReg(rs2), readReg(rd )); + DATA_PORT->write(readReg(rs1) + readReg(rs2) + 4, readReg(rd+1)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + dbg_printf("Result = 0x%x\n", readReg(rd+1)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction ldstub_reg behavior method. +void ac_behavior( ldstub_reg ) +{ + dbg_printf("atomic ldstub_reg r%d, [r%d+r%d]\n", rd, rs1, rs2); + writeReg(rd, DATA_PORT->read_byte(readReg(rs1) + readReg(rs2))); + DATA_PORT->write_byte(readReg(rs1) + readReg(rs2), 0xFF); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction swap_reg behavior method. +void ac_behavior( swap_reg ) +{ + dbg_printf("swap_reg r%d, [r%d+r%d]\n", rd, rs1, rs2); + int swap_temp = DATA_PORT->read(readReg(rs1) + readReg(rs2)); + DATA_PORT->write(readReg(rs1) + readReg(rs2), readReg(rd)); + writeReg(rd, swap_temp); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction sll_reg behavior method. +void ac_behavior( sll_reg ) +{ + dbg_printf("sll_reg r%d,r%d,r%d\n", rs1, rs2, rd); + writeReg(rd, readReg(rs1) << readReg(rs2)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction srl_reg behavior method. +void ac_behavior( srl_reg ) +{ + dbg_printf("srl_reg r%d,r%d,r%d\n", rs1, rs2, rd); + writeReg(rd, ((unsigned) readReg(rs1)) >> ((unsigned) readReg(rs2))); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction sra_reg behavior method. +void ac_behavior( sra_reg ) +{ + dbg_printf("sra_reg r%d,r%d,r%d\n", rs1, rs2, rd); + writeReg(rd, ((int) readReg(rs1)) >> ((int) readReg(rs2))); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction add_reg behavior method. +void ac_behavior( add_reg ) +{ + dbg_printf("add_reg r%d,r%d,r%d\n", rs1, rs2, rd); + writeReg(rd, readReg(rs1) + readReg(rs2)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction addcc_reg behavior method. +void ac_behavior( addcc_reg ) +{ + dbg_printf("addcc_reg r%d,r%d,r%d\n", rs1, rs2, rd); + int dest = readReg(rs1) + readReg(rs2); + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = (( readReg(rs1) & readReg(rs2) & ~dest & 0x80000000) | + (~readReg(rs1) & ~readReg(rs2) & dest & 0x80000000) ); + PSR_icc_c = ((readReg(rs1) & readReg(rs2) & 0x80000000) | + (~dest & (readReg(rs1) | readReg(rs2)) & 0x80000000) ); + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction addx_reg behavior method. +void ac_behavior( addx_reg ) +{ + dbg_printf("addx_reg r%d,r%d,r%d\n", rs1, rs2, rd); + writeReg(rd, readReg(rs1) + readReg(rs2) + PSR_icc_c); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction addxcc_reg behavior method. +void ac_behavior( addxcc_reg ) +{ + dbg_printf("addxcc_reg r%d,r%d,r%d\n", rs1, rs2, rd); + int dest = readReg(rs1) + readReg(rs2) + PSR_icc_c; + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = (( readReg(rs1) & readReg(rs2) & ~dest & 0x80000000) | + (~readReg(rs1) & ~readReg(rs2) & dest & 0x80000000) ); + PSR_icc_c = ((readReg(rs1) & readReg(rs2) & 0x80000000) | + (~dest & (readReg(rs1) | readReg(rs2)) & 0x80000000) ); + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction sub_reg behavior method. +void ac_behavior( sub_reg ) +{ + dbg_printf("sub_reg r%d,r%d,r%d\n", rs1, rs2, rd); + writeReg(rd, (readReg(rs1) - readReg(rs2))); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction subcc_reg behavior method. +void ac_behavior( subcc_reg ) +{ + dbg_printf("subcc_reg r%d,r%d,r%d\n", rs1, rs2, rd); + int dest = readReg(rs1) - readReg(rs2); + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = (( readReg(rs1) & ~readReg(rs2) & ~dest & 0x80000000) | + (~readReg(rs1) & readReg(rs2) & dest & 0x80000000) ); + PSR_icc_c = ((~readReg(rs1) & readReg(rs2) & 0x80000000) | + (dest & (~readReg(rs1) | readReg(rs2)) & 0x80000000) ); + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction subx_reg behavior method. +void ac_behavior( subx_reg ) +{ + dbg_printf("subx_reg r%d,r%d,r%d\n", rs1, rs2, rd); + writeReg(rd, readReg(rs1) - readReg(rs2) - PSR_icc_c); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction subxcc_reg behavior method. +void ac_behavior( subxcc_reg ) +{ + dbg_printf("subxcc_reg r%d,r%d,r%d\n", rs1, rs2, rd); + int dest = readReg(rs1) - readReg(rs2) - PSR_icc_c; + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = (( readReg(rs1) & ~readReg(rs2) & ~dest & 0x80000000) | + (~readReg(rs1) & readReg(rs2) & dest & 0x80000000) ); + PSR_icc_c = ((~readReg(rs1) & readReg(rs2) & 0x80000000) | + (dest & (~readReg(rs1) | readReg(rs2)) & 0x80000000) ); + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction and_reg behavior method. +void ac_behavior( and_reg ) +{ + dbg_printf("and_reg r%d,r%d,r%d\n", rs1, rs2, rd); + writeReg(rd, readReg(rs1) & readReg(rs2)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction andcc_reg behavior method. +void ac_behavior( andcc_reg ) +{ + dbg_printf("andcc_reg r%d,r%d,r%d\n", rs1, rs2, rd); + int dest = readReg(rs1) & readReg(rs2); + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction andn_reg behavior method. +void ac_behavior( andn_reg ) +{ + dbg_printf("andn_reg r%d,r%d,r%d\n", rs1, rs2, rd); + writeReg(rd, readReg(rs1) & ~readReg(rs2)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction andncc_reg behavior method. +void ac_behavior( andncc_reg ) +{ + dbg_printf("andncc_reg r%d,r%d,r%d\n", rs1, rs2, rd); + int dest = readReg(rs1) & ~readReg(rs2); + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction or_reg behavior method. +void ac_behavior( or_reg ) +{ + dbg_printf("or_reg r%d,r%d,r%d\n", rs1, rs2, rd); + writeReg(rd, readReg(rs1) | readReg(rs2)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction orcc_reg behavior method. +void ac_behavior( orcc_reg ) +{ + dbg_printf("orcc_reg r%d,r%d,r%d\n", rs1, rs2, rd); + int dest = readReg(rs1) | readReg(rs2); + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction orn_reg behavior method. +void ac_behavior( orn_reg ) +{ + dbg_printf("orn_reg r%d,r%d,r%d\n", rs1, rs2, rd); + writeReg(rd, readReg(rs1) | ~readReg(rs2)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction orncc_reg behavior method. +void ac_behavior( orncc_reg ) +{ + dbg_printf("orncc_reg r%d,r%d,r%d\n", rs1, rs2, rd); + int dest = readReg(rs1) | ~readReg(rs2); + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction xor_reg behavior method. +void ac_behavior( xor_reg ) +{ + dbg_printf("xor_reg r%d,r%d,r%d\n", rs1, rs2, rd); + writeReg(rd, readReg(rs1) ^ readReg(rs2)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction xorcc_reg behavior method. +void ac_behavior( xorcc_reg ) +{ + dbg_printf("xorcc_reg r%d,r%d,r%d\n", rs1, rs2, rd); + int dest = readReg(rs1) ^ readReg(rs2); + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction xnor_reg behavior method. +void ac_behavior( xnor_reg ) +{ + dbg_printf("xnor_reg r%d,r%d,r%d\n", rs1, rs2, rd); + writeReg(rd, ~(readReg(rs1) ^ readReg(rs2))); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction xnorcc_reg behavior method. +void ac_behavior( xnorcc_reg ) +{ + dbg_printf("xnorcc_reg r%d,r%d,r%d\n", rs1, rs2, rd); + int dest = ~(readReg(rs1) ^ readReg(rs2)); + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction save_reg behavior method. +void ac_behavior( save_reg ) +{ + dbg_printf("save_reg r%d,r%d,r%d\n", rs1, rs2, rd); + int tmp = readReg(rs1) + readReg(rs2); + + //copy ins and locals to RB + for (int i=16; i<32; i++) { + RB.write((CWP + i) & 0xFF, REGS[i]); + } + + //move out to in + for (int i=0; i<8; i++) { + REGS[i+24] = REGS[i+8]; + } + + //realy change reg window + CWP = (CWP-0x10); + if (CWP == WIM) trap_reg_window_overflow(DATA_PORT, RB, WIM); + + //copy local and out from buffer + for (int i=8; i<24; i++) { + REGS[i] = RB.read((CWP + i) & 0xFF); + } + + writeReg(rd, tmp); + dbg_printf(C_INVERSE "CWP: %d" C_RESET LF, CWP>>4); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction restore_reg behavior method. +void ac_behavior( restore_reg ) +{ + dbg_printf("restore_reg r%d,r%d,r%d\n", rs1, rs2, rd); + int tmp = readReg(rs1) + readReg(rs2); + + //copy locals and out to buffer + for (int i=8; i<24; i++) { + RB.write((CWP + i) & 0xFF, REGS[i]); + } + + //move in to out + for (int i=0; i<8; i++) { + REGS[i+8] = REGS[i+24]; + } + + //realy change reg window + CWP = (CWP+0x10); + if (CWP == WIM) trap_reg_window_underflow(DATA_PORT, RB, WIM); + + //copy in and local from buffer + for (int i=16; i<32; i++) { + REGS[i] = RB.read((CWP + i) & 0xFF); + } + + writeReg(rd, tmp); + dbg_printf(C_INVERSE "CWP: %d" C_RESET LF, CWP>>4); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction umul_reg behavior method. +void ac_behavior( umul_reg ) +{ + dbg_printf("umul_reg r%d,r%d,r%d\n", rs1, rs2, rd); + unsigned long long tmp = (unsigned long long) (unsigned) readReg(rs1) * (unsigned long long) (unsigned) readReg(rs2); + writeReg(rd, (unsigned int) tmp); + Y.write( (unsigned int) (tmp >> 32)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction smul_reg behavior method. +void ac_behavior( smul_reg ) +{ + dbg_printf("smul_reg r%d,r%d,r%d\n", rs1, rs2, rd); + long long tmp = (long long) readReg(rs1) * (long long) readReg(rs2); + writeReg(rd, (int) tmp); + Y.write( (int) (tmp >> 32)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction umulcc_reg behavior method. +void ac_behavior( umulcc_reg ) +{ + dbg_printf("umul_reg r%d,r%d,r%d\n", rs1, rs2, rd); + unsigned long long tmp = (unsigned long long) (unsigned) readReg(rs1) * (unsigned long long) (unsigned) readReg(rs2); + + PSR_icc_n = (unsigned int) tmp >> 31; + PSR_icc_z = (unsigned int) tmp == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, (unsigned int) tmp); + Y.write( (unsigned int) (tmp >> 32)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction smulcc_reg behavior method. +void ac_behavior( smulcc_reg ) +{ + dbg_printf("smulcc_reg r%d,r%d,r%d\n", rs1, rs2, rd); + long long tmp = (long long) readReg(rs1) * (long long) readReg(rs2); + + PSR_icc_n = (unsigned int) tmp >> 31; + PSR_icc_z = (unsigned int) tmp == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, (int) tmp); + Y.write( (int) (tmp >> 32)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction udiv_reg behavior method. +void ac_behavior( udiv_reg ) +{ + dbg_printf("udiv_reg r%d,r%d,r%d\n", rs1, rs2, rd); + unsigned long long tmp; + tmp = (unsigned long long) Y.read() << 32; + tmp |= (unsigned) readReg(rs1); + tmp /= (unsigned int) readReg(rs2); + unsigned int result = tmp & 0xFFFFFFFF; + bool temp_v = ((tmp >> 32) == 0) ? 0 : 1; + if (temp_v) result = 0xFFFFFFFF; + writeReg(rd, result); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction udivcc_reg behavior method. +void ac_behavior( udivcc_reg ) +{ + dbg_printf("udivcc_reg r%d,r%d,r%d\n", rs1, rs2, rd); + unsigned long long tmp; + tmp = (unsigned long long) Y.read() << 32; + tmp |= (unsigned) readReg(rs1); + tmp /= (unsigned int) readReg(rs2); + unsigned int result = tmp & 0xFFFFFFFF; + bool temp_v = ((tmp >> 32) == 0) ? 0 : 1; + if (temp_v) result = 0xFFFFFFFF; + + PSR_icc_n = result >> 31; + PSR_icc_z = result == 0; + PSR_icc_v = temp_v; + PSR_icc_c = 0; + + writeReg(rd, result); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction sdiv_reg behavior method. +void ac_behavior( sdiv_reg ) +{ + dbg_printf("sdiv_reg r%d,r%d,r%d\n", rs1, rs2, rd); + long long tmp; + tmp = (unsigned long long) Y.read() << 32; + tmp |= (unsigned) readReg(rs1); + tmp /= (signed) readReg(rs2); + int result = tmp & 0xFFFFFFFF; + bool temp_v = (((tmp >> 31) == 0) | + ((tmp >> 31) == -1LL)) ? 0 : 1; + if (temp_v) { + if (tmp > 0) result = 0x7FFFFFFF; + else result = 0x80000000; + } + writeReg(rd, result); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction sdivcc_reg behavior method. +void ac_behavior( sdivcc_reg ) +{ + dbg_printf("sdivcc_reg r%d,r%d,r%d\n", rs1, rs2, rd); + long long tmp; + tmp = (unsigned long long) Y.read() << 32; + tmp |= (unsigned) readReg(rs1); + tmp /= (signed) readReg(rs2); + int result = tmp & 0xFFFFFFFF; + bool temp_v = (((tmp >> 31) == 0) | + ((tmp >> 31) == -1LL)) ? 0 : 1; + if (temp_v) { + if (tmp > 0) result = 0x7FFFFFFF; + else result = 0x80000000; + } + + PSR_icc_n = result >> 31; + PSR_icc_z = result == 0; + PSR_icc_v = temp_v; + PSR_icc_c = 0; + + writeReg(rd, result); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction jmpl_reg behavior method. +void ac_behavior( jmpl_reg ) +{ + dbg_printf("jmpl_reg r%d,r%d,r%d\n", rs1, rs2, rd); + writeReg(rd, ac_pc); + //TODO: ugly: create a way to jump from a register without mapping + update_pc(1,1,1,0, readReg(rs1) + readReg(rs2), ac_pc, npc); +}; + +///!Instruction wry_reg behavior method. +void ac_behavior( wry_reg ) +{ + dbg_printf("wry_reg r%d,r%d,r%d\n", rs1, rs2, rd); + Y.write( readReg(rs1) ^ readReg(rs2)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction ldsb_imm behavior method. +void ac_behavior( ldsb_imm ) +{ + dbg_printf("ldsb_imm [r%d + %d], r%d\n", rs1, simm13, rd); + writeReg(rd, (int)(char) DATA_PORT->read_byte(readReg(rs1) + simm13)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction ldsh_imm behavior method. +void ac_behavior( ldsh_imm ) +{ + dbg_printf("ldsh_imm [r%d + %d], r%d\n", rs1, simm13, rd); + writeReg(rd, (int)(short) DATA_PORT->read_half(readReg(rs1) + simm13)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction ldub_imm behavior method. +void ac_behavior( ldub_imm ) +{ + dbg_printf("ldub_imm [r%d + %d], r%d\n", rs1, simm13, rd); + writeReg(rd, DATA_PORT->read_byte(readReg(rs1) + simm13)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction lduh_imm behavior method. +void ac_behavior( lduh_imm ) +{ + dbg_printf("lduh_imm [r%d + %d], r%d\n", rs1, simm13, rd); + writeReg(rd, DATA_PORT->read_half(readReg(rs1) + simm13)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction ld_imm behavior method. +void ac_behavior( ld_imm ) +{ + dbg_printf("ld_imm [r%d + %d], r%d\n", rs1, simm13, rd); + writeReg(rd, DATA_PORT->read(readReg(rs1) + simm13)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction ldd_imm behavior method. +void ac_behavior( ldd_imm ) +{ + dbg_printf("ldd_imm [r%d + %d], r%d\n", rs1, simm13, rd); + int tmp = DATA_PORT->read(readReg(rs1) + simm13 + 4); + writeReg(rd, DATA_PORT->read(readReg(rs1) + simm13)); + writeReg(rd+1, tmp); + dbg_printf("Result = 0x%x\n", readReg(rd)); + dbg_printf("Result = 0x%x\n", readReg(rd+1)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction and_imm behavior method. +void ac_behavior( and_imm ) +{ + dbg_printf("and_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + writeReg(rd, readReg(rs1) & simm13); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction andcc_imm behavior method. +void ac_behavior( andcc_imm ) +{ + dbg_printf("andcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + int dest = readReg(rs1) & simm13; + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction andn_imm behavior method. +void ac_behavior( andn_imm ) +{ + dbg_printf("andn_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + writeReg(rd, readReg(rs1) & ~simm13); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction andncc_imm behavior method. +void ac_behavior( andncc_imm ) +{ + dbg_printf("andncc_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + int dest = readReg(rs1) & ~simm13; + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction or_imm behavior method. +void ac_behavior( or_imm ) +{ + dbg_printf("or_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + writeReg(rd, readReg(rs1) | simm13); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction orcc_imm behavior method. +void ac_behavior( orcc_imm ) +{ + dbg_printf("orcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + int dest = readReg(rs1) | simm13; + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction orn_imm behavior method. +void ac_behavior( orn_imm ) +{ + dbg_printf("orn_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + writeReg(rd, readReg(rs1) | ~simm13); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction orncc_imm behavior method. +void ac_behavior( orncc_imm ) +{ + dbg_printf("orn_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + int dest = readReg(rs1) | ~simm13; + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction xor_imm behavior method. +void ac_behavior( xor_imm ) +{ + dbg_printf("xor_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + writeReg(rd, readReg(rs1) ^ simm13); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction xorcc_imm behavior method. +void ac_behavior( xorcc_imm ) +{ + dbg_printf("xorcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + int dest = readReg(rs1) ^ simm13; + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction xnor_imm behavior method. +void ac_behavior( xnor_imm ) +{ + dbg_printf("xnor_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + writeReg(rd, ~(readReg(rs1) ^ simm13)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction xnorcc_imm behavior method. +void ac_behavior( xnorcc_imm ) +{ + dbg_printf("xnorcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + int dest = ~(readReg(rs1) ^ simm13); + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction umul_imm behavior method. +void ac_behavior( umul_imm ) +{ + dbg_printf("umul_imm r%d,%d,r%d\n", rs1, simm13, rd); + unsigned long long tmp = (unsigned long long) (unsigned) readReg(rs1) * (unsigned long long) (unsigned) simm13; + writeReg(rd, (unsigned int) tmp); + Y.write( (unsigned int) (tmp >> 32)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction smul_imm behavior method. +void ac_behavior( smul_imm ) +{ + dbg_printf("smul_imm r%d,%d,r%d\n", rs1, simm13, rd); + long long tmp = (long long) readReg(rs1) * (long long) simm13; + writeReg(rd, (int) tmp); + Y.write( (int) (tmp >> 32)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction umulcc_imm behavior method. +void ac_behavior( umulcc_imm ) +{ + dbg_printf("umulcc_imm r%d,%d,r%d\n", rs1, simm13, rd); + unsigned long long tmp = (unsigned long long) (unsigned) readReg(rs1) * (unsigned long long) (unsigned) simm13; + + PSR_icc_n = (unsigned int) tmp >> 31; + PSR_icc_z = (unsigned int) tmp == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, (unsigned int) tmp); + Y.write( (unsigned int) (tmp >> 32)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction smulcc_imm behavior method. +void ac_behavior( smulcc_imm ) +{ + dbg_printf("smulcc_imm r%d,%d,r%d\n", rs1, simm13, rd); + long long tmp = (long long) readReg(rs1) * (long long) simm13; + + PSR_icc_n = (unsigned int) tmp >> 31; + PSR_icc_z = (unsigned int) tmp == 0; + PSR_icc_v = 0; + PSR_icc_c = 0; + + writeReg(rd, (int) tmp); + Y.write( (int) (tmp >> 32)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction udiv_imm behavior method. +void ac_behavior( udiv_imm ) +{ + dbg_printf("udiv_imm r%d,%d,r%d\n", rs1, simm13, rd); + unsigned long long tmp; + tmp = (unsigned long long) Y.read() << 32; + tmp |= (unsigned) readReg(rs1); + tmp /= (unsigned int) simm13; + unsigned int result = tmp & 0xFFFFFFFF; + bool temp_v = ((tmp >> 32) == 0) ? 0 : 1; + if (temp_v) result = 0xFFFFFFFF; + writeReg(rd, result); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction udivcc_imm behavior method. +void ac_behavior( udivcc_imm ) +{ + dbg_printf("udivcc_imm r%d,%d,r%d\n", rs1, simm13, rd); + unsigned long long tmp; + tmp = (unsigned long long) Y.read() << 32; + tmp |= (unsigned) readReg(rs1); + tmp /= (unsigned int) simm13; + unsigned int result = tmp & 0xFFFFFFFF; + bool temp_v = ((tmp >> 32) == 0) ? 0 : 1; + if (temp_v) result = 0xFFFFFFFF; + + PSR_icc_n = result >> 31; + PSR_icc_z = result == 0; + PSR_icc_v = temp_v; + PSR_icc_c = 0; + + writeReg(rd, result); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction sdiv_imm behavior method. +void ac_behavior( sdiv_imm ) +{ + dbg_printf("sdiv_imm r%d,%d,r%d\n", rs1, simm13, rd); + long long tmp; + tmp = (unsigned long long) Y.read() << 32; + tmp |= (unsigned) readReg(rs1); + tmp /= (signed) simm13; + int result = tmp & 0xFFFFFFFF; + bool temp_v = (((tmp >> 31) == 0) | + ((tmp >> 31) == -1LL)) ? 0 : 1; + if (temp_v) { + if (tmp > 0) result = 0x7FFFFFFF; + else result = 0x80000000; + } + writeReg(rd, result); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction sdivcc_imm behavior method. +void ac_behavior( sdivcc_imm ) +{ + dbg_printf("sdivcc_imm r%d,%d,r%d\n", rs1, simm13, rd); + long long tmp; + tmp = (unsigned long long) Y.read() << 32; + tmp |= (unsigned) readReg(rs1); + tmp /= simm13; + int result = tmp & 0xFFFFFFFF; + bool temp_v = (((tmp >> 31) == 0) | + ((tmp >> 31) == -1LL)) ? 0 : 1; + if (temp_v) { + if (tmp > 0) result = 0x7FFFFFFF; + else result = 0x80000000; + } + + PSR_icc_n = result >> 31; + PSR_icc_z = result == 0; + PSR_icc_v = temp_v; + PSR_icc_c = 0; + + writeReg(rd, result); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction stb_imm behavior method. +void ac_behavior( stb_imm ) +{ + dbg_printf("stb_imm r%d, [r%d + %d]\n", rd, rs1, simm13); + DATA_PORT->write_byte(readReg(rs1) + simm13, (char) readReg(rd)); + dbg_printf("Result = 0x%x\n", (char) readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction sth_imm behavior method. +void ac_behavior( sth_imm ) +{ + dbg_printf("sth_imm r%d, [r%d + %d]\n", rd, rs1, simm13); + DATA_PORT->write_half(readReg(rs1) + simm13, (short) readReg(rd)); + dbg_printf("Result = 0x%x\n", (short) readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction st_imm behavior method. +void ac_behavior( st_imm ) +{ + dbg_printf("st_imm r%d, [r%d + %d]\n", rd, rs1, simm13); + DATA_PORT->write(readReg(rs1) + simm13, readReg(rd)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction std_imm behavior method. +void ac_behavior( std_imm ) +{ + dbg_printf("std_imm r%d, [r%d + %d]\n", rd, rs1, simm13); + DATA_PORT->write(readReg(rs1) + simm13, readReg(rd )); + DATA_PORT->write(readReg(rs1) + simm13 + 4, readReg(rd+1)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + dbg_printf("Result = 0x%x\n", readReg(rd+1)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction ldstub_imm behavior method. +void ac_behavior( ldstub_imm ) +{ + dbg_printf("atomic ldstub_imm r%d, [r%d + %d]\n", rd, rs1, simm13); + writeReg(rd, DATA_PORT->read_byte(readReg(rs1) + simm13)); + DATA_PORT->write_byte(readReg(rs1) + simm13, 0xFF); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction swap_imm behavior method. +void ac_behavior( swap_imm ) +{ + dbg_printf("swap_imm r%d, [r%d + %d]\n", rd, rs1, simm13); + int swap_temp = DATA_PORT->read(readReg(rs1) + simm13); + DATA_PORT->write(readReg(rs1) + simm13, readReg(rd)); + writeReg(rd, swap_temp); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction sll_imm behavior method. +void ac_behavior( sll_imm ) +{ + dbg_printf("sll_imm r%d,%d,r%d\n", rs1, simm13, rd); + writeReg(rd, readReg(rs1) << simm13); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction srl_imm behavior method. +void ac_behavior( srl_imm ) +{ + dbg_printf("srl_imm r%d,%d,r%d\n", rs1, simm13, rd); + writeReg(rd, ((unsigned) readReg(rs1)) >> ((unsigned) simm13)); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction sra_imm behavior method. +void ac_behavior( sra_imm ) +{ + dbg_printf("sra_imm r%d,%d,r%d\n", rs1, simm13, rd); + writeReg(rd, ((int) readReg(rs1)) >> simm13 ); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction add_imm behavior method. +void ac_behavior( add_imm ) +{ + dbg_printf("add_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + writeReg(rd, readReg(rs1) + simm13); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction addcc_imm behavior method. +void ac_behavior( addcc_imm ) +{ + dbg_printf("addcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + int dest = readReg(rs1) + simm13; + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = (( readReg(rs1) & simm13 & ~dest & 0x80000000) | + (~readReg(rs1) & ~simm13 & dest & 0x80000000) ); + PSR_icc_c = ((readReg(rs1) & simm13 & 0x80000000) | + (~dest & (readReg(rs1) | simm13) & 0x80000000) ); + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction addx_imm behavior method. +void ac_behavior( addx_imm ) +{ + dbg_printf("addx_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + writeReg(rd, readReg(rs1) + simm13 + PSR_icc_c); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction addxcc_imm behavior method. +void ac_behavior( addxcc_imm ) +{ + dbg_printf("addxcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + int dest = readReg(rs1) + simm13 + PSR_icc_c; + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = (( readReg(rs1) & simm13 & ~dest & 0x80000000) | + (~readReg(rs1) & ~simm13 & dest & 0x80000000) ); + PSR_icc_c = ((readReg(rs1) & simm13 & 0x80000000) | + (~dest & (readReg(rs1) | simm13) & 0x80000000) ); + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction sub_imm behavior method. +void ac_behavior( sub_imm ) +{ + dbg_printf("sub_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + writeReg(rd, readReg(rs1) - simm13); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction subcc_imm behavior method. +void ac_behavior( subcc_imm ) +{ + dbg_printf("subcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + int dest = readReg(rs1) - simm13; + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = (( readReg(rs1) & ~simm13 & ~dest & 0x80000000) | + (~readReg(rs1) & simm13 & dest & 0x80000000) ); + PSR_icc_c = ((~readReg(rs1) & simm13 & 0x80000000) | + (dest & (~readReg(rs1) | simm13) & 0x80000000) ); + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction subx_imm behavior method. +void ac_behavior( subx_imm ) +{ + dbg_printf("subx_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + writeReg(rd, readReg(rs1) - simm13 - PSR_icc_c); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction subxcc_imm behavior method. +void ac_behavior( subxcc_imm ) +{ + dbg_printf("subxcc_imm r%d,0x%x,r%d\n", rs1, simm13, rd); + int dest = readReg(rs1) - simm13 - PSR_icc_c; + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = (( readReg(rs1) & ~simm13 & ~dest & 0x80000000) | + (~readReg(rs1) & simm13 & dest & 0x80000000) ); + PSR_icc_c = ((~readReg(rs1) & simm13 & 0x80000000) | + (dest & (~readReg(rs1) | simm13) & 0x80000000) ); + + writeReg(rd, dest); + dbg_printf("Result = 0x%x\n", dest); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +///!Instruction jmpl_imm behavior method. +void ac_behavior( jmpl_imm ) +{ + dbg_printf("jmpl_imm r%d,%d,r%d\n", rs1, simm13, rd); + writeReg(rd, ac_pc); + update_pc(1,1,1,0, readReg(rs1) + simm13, ac_pc, npc); +}; + +//!Instruction save_imm behavior method. +void ac_behavior( save_imm ) +{ + dbg_printf("save_imm r%d, %d, r%d\n", rs1, simm13, rd); + int tmp = readReg(rs1) + simm13; + + //copy ins and locals to RB + for (int i=16; i<32; i++) { + RB.write((CWP + i) & 0xFF, REGS[i]); + } + + //move out to in + for (int i=0; i<8; i++) { + REGS[i+24] = REGS[i+8]; + } + + //realy change reg window + CWP = (CWP-0x10); + if (CWP == WIM) trap_reg_window_overflow(DATA_PORT, RB, WIM); + + //copy local and out from buffer + for (int i=8; i<24; i++) { + REGS[i] = RB.read((CWP + i) & 0xFF); + } + + writeReg(rd, tmp); + dbg_printf(C_INVERSE "CWP: %d" C_RESET LF, CWP>>4); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction restore_imm behavior method. +void ac_behavior( restore_imm ) +{ + dbg_printf("restore_imm r%d, %d, r%d\n", rs1, simm13, rd); + int tmp = readReg(rs1) + simm13; + + //copy locals and out to buffer + for (int i=8; i<24; i++) { + RB.write((CWP + i) & 0xFF, REGS[i]); + } + + //move in to out + for (int i=0; i<8; i++) { + REGS[i+8] = REGS[i+24]; + } + + //realy change reg window + CWP = (CWP+0x10); + if (CWP == WIM) trap_reg_window_underflow(DATA_PORT, RB, WIM); + + //copy in and local from buffer + for (int i=16; i<32; i++) { + REGS[i] = RB.read((CWP + i) & 0xFF); + } + + writeReg(rd, tmp); + dbg_printf(C_INVERSE "CWP: %d" C_RESET LF, CWP>>4); + dbg_printf("Result = 0x%x\n", readReg(rd)); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction rdy behavior method. +void ac_behavior( rdy ) +{ + dbg_printf("rdy r%d\n", rd); + writeReg(rd, Y.read()); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction wry_imm behavior method. +void ac_behavior( wry_imm ) +{ + dbg_printf("wry_imm\n"); + Y.write( readReg(rs1) ^ simm13); + update_pc(0,0,0,0,0, ac_pc, npc); +}; + +//!Instruction mulscc_reg behavior method. +void ac_behavior( mulscc_reg ) +{ + dbg_printf("mulscc_reg r%d, r%d, r%d\n", rs1, rs2, rd); + int rs1_0 = readReg(rs1) & 1; + int op1 = ((PSR_icc_n ^ PSR_icc_v) << 31) | (readReg(rs1) >> 1); + int op2 = ((Y.read() & 1) == 0) ? 0 : readReg(rs2); + int dest = op1+op2; + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = (( op1 & op2 & ~dest & 0x80000000) | + (~op1 & ~op2 & dest & 0x80000000) ); + PSR_icc_c = (( op1 & op2 & 0x80000000) | + (~dest & (op1 | op2) & 0x80000000) ); + + writeReg(rd, dest); + Y.write( (rs1_0 << 31) | (Y.read() >> 1)); + update_pc(0,0,0,0,0, ac_pc, npc); +} + +//!Instruction mulscc_imm behavior method. +void ac_behavior( mulscc_imm ) +{ + dbg_printf("mulscc_imm r%d, %d, r%d\n", rs1, simm13, rd); + int rs1_0 = readReg(rs1) & 1; + int op1 = ((PSR_icc_n ^ PSR_icc_v) << 31) | (readReg(rs1) >> 1); + int op2 = ((Y.read() & 1) == 0) ? 0 : simm13; + int dest = op1+op2; + + PSR_icc_n = dest >> 31; + PSR_icc_z = dest == 0; + PSR_icc_v = (( op1 & op2 & ~dest & 0x80000000) | + (~op1 & ~op2 & dest & 0x80000000) ); + PSR_icc_c = (( op1 & op2 & 0x80000000) | + (~dest & (op1 | op2) & 0x80000000) ); + + writeReg(rd, dest); + Y.write( (rs1_0 << 31) | (Y.read() >> 1)); + update_pc(0,0,0,0,0, ac_pc, npc); +} + +//!Instruction trap behavior method. +//TODO: unimplemented +void ac_behavior( trap_reg ) +{ + dbg_printf("trap\n"); + stop(); +} + +//!Instruction trap behavior method. +//TODO: unimplemented +void ac_behavior( trap_imm ) +{ + dbg_printf("trap\n"); + stop(); +} + +//!Instruction unimplemented behavior method. +void ac_behavior( unimplemented ) +{ + dbg_printf("unimplemented\n"); + printf("sparc-isa.cpp: program flow reach instruction 'unimplemented' at ac_pc=%#x\n", (int)ac_pc); + stop(EXIT_FAILURE); + update_pc(0,0,0,0,0, ac_pc, npc); +} diff --git a/pdl/sparc/sparc_nonblock.ac b/pdl/sparc/sparc_nonblock.ac new file mode 100644 index 0000000..fa68c7b --- /dev/null +++ b/pdl/sparc/sparc_nonblock.ac @@ -0,0 +1,62 @@ +/** + * @file sparc.ac + * @author Sandro Rigo + * Marcus Bartholomeu + * Alexandro Baldassin (assembly information) + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Thu, 29 Jun 2006 14:49:07 -0300 + * + * @brief The ArchC SPARC-V8 functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + */ + +AC_ARCH(sparc){ + + + ac_tlm2_nb_port MEM:512M; + //ac_icache IC("2w", 128, 32, "wb", "fifo"); + //ac_dcache DC("2w", 512, 32, "wt", "fifo"); + + ac_icache IC("2w", 128, 8, "wt", "fifo"); + ac_dcache DC("2w", 128, 8, "wt", "fifo"); + + ac_regbank RB:256; + ac_regbank REGS:32; + + ac_reg npc; + + ac_tlm2_intr_port intr_port; + + ac_reg<1> PSR_icc_n; + ac_reg<1> PSR_icc_z; + ac_reg<1> PSR_icc_v; + ac_reg<1> PSR_icc_c; + + ac_reg PSR; + ac_reg Y; + + ac_reg<8> WIM; + ac_reg<8> CWP; + + ac_wordsize 32; + ac_fetchsize 32; + + ac_reg id; + ARCH_CTOR(sparc){ + + ac_isa("sparc_isa.ac"); + set_endian("big"); + IC.bindTo(MEM); + DC.bindTo(MEM); + }; +}; diff --git a/pdl/sparc/sparc_syscall.H b/pdl/sparc/sparc_syscall.H new file mode 100644 index 0000000..2afc3da --- /dev/null +++ b/pdl/sparc/sparc_syscall.H @@ -0,0 +1,40 @@ +/****************************************************** + * ArchC Architecture Dependent Syscall header file. * + * This file is automatically generated by ArchC * + * WITHOUT WARRANTY OF ANY KIND, either express * + * or implied. * + * For more information on ArchC, please visit: * + * http://www.archc.org * + * * + * The ArchC Team * + * Computer Systems Laboratory (LSC) * + * IC-UNICAMP * + * http://www.lsc.ic.unicamp.br * + ******************************************************/ + + +#ifndef sparc_SYSCALL_H +#define sparc_SYSCALL_H + +#include "sparc_arch.H" +#include "sparc_arch_ref.H" +#include "sparc_parms.H" +#include "ac_syscall.H" + +//sparc system calls +class sparc_syscall : public ac_syscall, public sparc_arch_ref +{ +public: + sparc_syscall(sparc_arch& ref) : ac_syscall(ref, sparc_parms::AC_RAMSIZE), sparc_arch_ref(ref) {}; + virtual ~sparc_syscall() {}; + + void get_buffer(int argn, unsigned char* buf, unsigned int size); + void set_buffer(int argn, unsigned char* buf, unsigned int size); + void set_buffer_noinvert(int argn, unsigned char* buf, unsigned int size); + int get_int(int argn); + void set_int(int argn, int val); + void return_from_syscall(); + void set_prog_args(int argc, char **argv); +}; + +#endif diff --git a/pdl/sparc/sparc_syscall.cpp b/pdl/sparc/sparc_syscall.cpp new file mode 100644 index 0000000..2e7a2b6 --- /dev/null +++ b/pdl/sparc/sparc_syscall.cpp @@ -0,0 +1,121 @@ +/** + * @file sparc_syscall.cpp + * @author Sandro Rigo + * Marcus Bartholomeu + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:50:50 -0300 + * + * @brief The ArchC SPARC-V8 functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include "sparc_syscall.H" + +#define writeReg(addr, val) REGS[addr] = (addr)? ac_word(val) : 0 +#define readReg(addr) REGS[addr] + +// Namespace for sparc types. +using namespace sparc_parms; + +void sparc_syscall::get_buffer(int argn, unsigned char* buf, unsigned int size) +{ + unsigned int addr = readReg(8+argn); + + for (unsigned int i = 0; iread_byte(addr); + } +} + +void sparc_syscall::set_buffer(int argn, unsigned char* buf, unsigned int size) +{ + unsigned int addr = readReg(8+argn); + + for (unsigned int i = 0; iwrite_byte(addr, buf[i]); + } +} + +void sparc_syscall::set_buffer_noinvert(int argn, unsigned char* buf, unsigned int size) +{ + unsigned int addr = readReg(8+argn); + + for (unsigned int i = 0; iwrite(addr, *(unsigned int *) &buf[i]); + } +} + +int sparc_syscall::get_int(int argn) +{ + return readReg(8+argn); +} + +void sparc_syscall::set_int(int argn, int val) +{ + writeReg(8+argn, val); +} + +void sparc_syscall::return_from_syscall() +{ + //similar to retl (jmpl %o7+8, %g0), but annul next + npc = readReg(15) + 8; + ac_pc = npc; + npc += 4; +} + +void sparc_syscall::set_prog_args(int argc, char **argv) +{ + int i, j, base; + + unsigned int ac_argv[30]; + char ac_argstr[512]; + + base = AC_RAM_END - 512; + for (i=0, j=0; i + + + + +IA32 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pdl/x86/IA32_gdb_funcs.cpp b/pdl/x86/IA32_gdb_funcs.cpp new file mode 100644 index 0000000..6e5b504 --- /dev/null +++ b/pdl/x86/IA32_gdb_funcs.cpp @@ -0,0 +1,160 @@ +/** + * @file IA32_gdb_funcs.cpp + * @author Rodolfo Jardim de Azevedo + * Team 03 - MC723 - 2005, 1st period + * Eduardo Uemura Okada + * Andre Deiano Pansani + * Ricardo Andrade + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:29 -0300 + * + * @brief The ArchC x86 functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + */ + + +#include "IA32.H" + + +#define GENREGS 8 +#define SEGREGS 6 +#define SPRREGS 2 +#define INVALID_REG 0xFFFFFFFF + + +// Register definitions to register bank GR:8 +#define EAX 0 +#define ECX 1 +#define EDX 2 +#define EBX 3 +#define ESP 4 +#define EBP 5 +#define ESI 6 +#define EDI 7 +#define AX 0 +#define CX 1 +#define DX 2 +#define BX 3 +#define SP 4 +#define BP 5 +#define SI 6 +#define DI 7 +#define AL 0 +#define CL 1 +#define DL 2 +#define BL 3 +#define AH 4 +#define CH 5 +#define DH 6 +#define BH 7 +#define STACK_BOTTOM 0x01000000 +// Register definitions to register bank SR:6 +#define CS 0 +#define DS 1 +#define SS 2 +#define ES 3 +#define FS 4 +#define GS 5 +// Register definitions to register bank SPR:2 +#define EFLAGS 0 +#define EIP 1 +#define FLAG_CF (1) +#define FLAG_PF (1<<2) +#define FLAG_AF (1<<4) +#define FLAG_ZF (1<<6) +#define FLAG_SF (1<<7) +#define FLAG_TF (1<<8) +#define FLAG_IF (1<<9) +#define FLAG_DF (1<<10) +#define FLAG_OF (1<<11) +#define FLAG_IOPL (1<<12 | 1<<13) +#define FLAG_NT (1<<14) +#define FLAG_RF (1<<16) +#define FLAG_VM (1<<17) +#define FLAG_AC (1<<18) +#define FLAG_VIF (1<<19) +#define FLAG_VIP (1<<20) +#define FLAG_ID (1<<21) +#define FLAG_ALL 0xFFFFFFFF + +#define OPERAND_SIZE16JUST 0 +#define OPERAND_SIZE16 1 +#define OPERAND_SIZE32 2 + +#define REG_XH 0xFFFF00FF + +using namespace IA32_parms; + +int OperSize; + + + +int IA32::nRegs(void) +{ + return GENREGS+SEGREGS+SPRREGS; +} + +ac_word IA32::reg_read ( int reg ) +{ + signed char aux = 0; + uint GR_temp = 0; + + printf("reg_read %i 0x%08X\n",reg,GR.read(reg)); + if ( (reg >= 0) && (reg < GENREGS) ){ + /* if (reg == 0){ + GR_temp = GR[0];//eax + printf("GR[0]: %08X\n",GR[0]); + aux = GR[4];//ah + aux = (aux & 0xFF00); + //aux = aux << 8; + + printf("AUX: %X\n",aux ); + GR_temp = GR_temp & REG_XH; + printf("GR_temp: %08X\n",GR_temp); + GR_temp = (GR_temp | aux ); + printf("EAX: 0x%08X\n",GR_temp); + return GR_temp; + }//if*/ + return GR.read(reg); + } + else if ( (reg >= GENREGS) && (reg < (GENREGS+SPRREGS)) ) + return SPR.read(1-(reg-(GENREGS))); + else if ( (reg >= (GENREGS+SPRREGS)) && (reg < (GENREGS+SEGREGS+SPRREGS)) ) + return SR.read(reg-(GENREGS+SPRREGS)); + return INVALID_REG; +} + +void IA32::reg_write( int reg, ac_word value ) +{ + printf("reg_write\n"); + if ( (reg >= 0) && (reg < GENREGS) ) + //GR.write(reg, value); + GR.write(reg, value); + else if ( (reg >= GENREGS) && (reg < (GENREGS+SPRREGS)) ) + SPR.write((1-(reg-GENREGS)), value); + else if ( (reg >= (GENREGS+SPRREGS)) && (reg < (GENREGS+SEGREGS+SPRREGS)) ) + SR.write((reg-(GENREGS+SPRREGS)), value); +} + +unsigned char IA32::mem_read ( unsigned int address ) +{ + //return ac_resources::IM->read_byte(address); + return IM->read_byte(address); +} + +void IA32::mem_write ( unsigned int address, unsigned char byte ) +{ + //ac_resources::IM->write_byte(address,byte); + IM->write_byte(address,byte); +} + diff --git a/pdl/x86/IA32_isa.ac b/pdl/x86/IA32_isa.ac new file mode 100644 index 0000000..50d7020 --- /dev/null +++ b/pdl/x86/IA32_isa.ac @@ -0,0 +1,1068 @@ +/** + * @file IA32_isa.ac + * @author Rodolfo Jardim de Azevedo + * Valdiney Alves Pimenta (ArchC 2.0 port, new instructions, some fixed bugs) + * Team 03 - MC723 - 2005, 1st period + * Eduardo Uemura Okada + * Andre Deiano Pansani + * Ricardo Andrade + * Modified by Rafael Madeira + * readRegister8(); + * writeRegister8(); + * void ac_behavior( Type_op1bi ) + * DataManager + * + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Thu, 29 Jun 2006 14:49:07 -0300 + * + * @brief The ArchC x86 functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + */ + +AC_ISA(IA32) +{ + // No SSE2, SSE, MMX or System specific instructions declared + + // Opcode sizes in IA32 + // 1BYTE = op1b + // 2BYTES= op2b + + ac_format Type_op1b = "%op1b:8"; + ac_format Type_op2b = "%op2b:16"; + ac_format Type_op1bi = "%op1b:8 %imme:32"; + ac_format Type_op1bi8 = "%op1b:8 %imm8:8"; + ac_format Type_op1bd8 = "%op1b:8 %disp8:8"; + ac_format Type_op1bd32 = "%op1b:8 %imme:32"; // Restriction from archc, imme is a disp + ac_format Type_op2bd32 = "%op2b:16 %disp32:32"; + //ac_format Type_op1b_rm32 = "%op1b:8 %mod:2 %regop:3 %rm:3 %sib:8 %disp:32 %imm:32"; + //ac_format Type_op2b_rm32 = "%op2b:16 %mod2:2 %regop2:3 %rm2:3 %sib2:8 %disp2:32 %imm2:32"; + + ac_format Type_op1b_rm32 = "%op1b:8 %rm:3 %regop:3 %mod:2 %sib:8 %disp:32 %imm:32"; + ac_format Type_op2b_rm32 = "%op2b:16 %rm2:3 %regop2:3 %mod2:2 %sib2:8 %disp2:32 %imm2:32"; + + // Debug formats (nonexistant in the instruction set) + ac_format Type_op2b_debug = "%op2b:16 %iadd:32 %eadd:32"; + + // Instruction naming patterns: + // _[]_[] + // Note: m16:32 = m16_32 + + ac_instr ud2, cpuid, bswap_EAX_r32, bswap_ECX_r32, + bswap_EDX_r32, bswap_EBX_r32, bswap_ESP_r32, bswap_EBP_r32, + bswap_ESI_r32, bswap_EDI_r32, push_FS, push_GS, pop_FS, pop_GS, aam, + aad; + + ac_instr ja_jnbe_rel16_32, + jae_jnb_jnc_rel16_32, jb_jc_jnae_rel16_32, jbe_jna_rel16_32, + je_jz_rel16_32, jg_jnle_rel16_32, jge_jnl_rel16_32, + jl_jnge_rel16_32, jle_jng_rel16_32, jne_jnz_rel16_32, + jno_rel16_32, jnp_jpo_rel16_32, jns_rel16_32, jo_rel16_32, + jp_jpe_rel16_32, js_rel16_32; + + ac_instr lss_r32_m16_32, lfs_r32_m16_32, lgs_r32_m16_32, + cmov_a_nbe_r32_rm32, cmov_ae_nb_nc_r32_rm32, + cmov_b_c_nae_r32_rm32, cmov_be_na_r32_rm32, + cmov_e_z_r32_rm32, cmov_g_nle_r32_rm32, cmov_ge_nl_r32_rm32, + cmov_l_nge_r32_rm32, cmov_le_ng_r32_rm32, cmov_ne_nz_r32_rm32, + cmov_no_r32_rm32, cmov_np_po_r32_rm32, cmov_ns_r32_rm32, + cmov_o_r32_rm32, cmov_p_pe_r32_rm32, cmov_s_r32_rm32, + xadd_rm32_r32, cmpxchg_rm32_r32, cmpxchg8b_m64, movsx_r32_rm8, + movsx_r32_rm16, movzx_r32_rm8, movzx_r32_rm16, + shrd_rm32_r32_imm8, shrd_rm32_r32_CL, shld_rm32_r32_imm8, + shld_rm32_r32_CL, bt_rm32_r32, bt_rm32_imm8, bts_rm32_r32, + btr_rm32_r32, btc_rm32_r32, bsf_r32_rm32, bsr_r32_rm32, + seta_setnbe_rm8, setae_setnb_setnc_rm8, setb_setc_setnae_rm8, + setbe_setna_rm8, sete_setz_rm8, setg_setnle_rm8, + setge_setnl_rm8, setl_setnge_rm8, setle_setng_rm8, + setne_setnz_rm8, setno_rm8, setnp_setpo_rm8, setns_rm8, + seto_rm8, setp_setpe_rm8, sets_rm8, bts_rm32_imm8, + btr_rm32_imm8, btc_rm32_imm8, imul_r32_rm32; + + ac_instr insd, outsd, stc, clc, cmc, cld, std, lahf, sahf, pushfd, popfd, sti, + cli, nop, xlatb, push_EAX, push_ECX, push_EDX, push_EBX, push_ESP, + push_EBP, push_ESI, push_EDI, push_CS, push_SS, push_DS, push_ES, + pop_EAX, pop_ECX, pop_EDX, pop_EBX, pop_ESP, pop_EBP, pop_ESI, + pop_EDI, pop_DS, pop_ES, pop_SS, push_a_ad, pop_a_ad, in_EAX_DX, + out_DX_EAX, cwd_cwq, cbw_cwde, inc_EAX, inc_ECX, inc_EDX, inc_EBX, + inc_ESP, inc_EBP, inc_ESI, inc_EDI, dec_EAX, dec_ECX, dec_EDX, dec_EBX, + dec_ESP, dec_EBP, dec_ESI, dec_EDI, daa, das, aaa, aas, iret_iretd, + leave, movs_m32_m32, cmps_m32_m32, scas_m32, lods_m32, stos_m32, + /*xchg_EAX_EAX,*/xchg_EAX_ECX, xchg_EAX_EDX, xchg_EAX_EBX, xchg_EAX_ESP, + xchg_EAX_EBP, xchg_EAX_ESI, xchg_EAX_EDI, P_LOCK, P_REPNE_REPNZ, + P_REP_REPE_REPZ, P_CS, P_SS, P_DS, P_ES, P_FS, P_GS, P_BTAKEN, + P_BNTAKEN, P_OPSIZE, P_ADSIZE; + + ac_instr ja_jnbe_rel8, jae_jnb_jnc_rel8, jb_jc_jnae_rel8, jbe_jna_rel8, + je_jz_rel8, jg_jnle_rel8, jge_jnl_rel8, jl_jnge_rel8, + jle_jng_rel8, jne_jnz_rel8, jno_rel8, jnp_jpo_rel8, jns_rel8, + jo_rel8, jp_jpe_rel8, js_rel8, jcxz_jecxz_rel8, loop_rel8, + loope_loopz_rel8, loopne_loopnz_rel8, jmp_rel8; + + ac_instr call_rel32, jmp_rel32; + + ac_instr mov_EAX_imm32, mov_ECX_imm32, mov_EDX_imm32, mov_EBX_imm32, + mov_ESP_imm32, mov_EBP_imm32, mov_ESI_imm32, mov_EDI_imm32, + push_imm32, add_EAX_imm32, adc_EAX_imm32, sub_EAX_imm32, + sbb_EAX_imm32, cmp_EAX_imm32, and_EAX_imm32, or_EAX_imm32, + xor_EAX_imm32, test_eax_imm32; + + ac_instr mov_AL_imm8, mov_CL_imm8, mov_DL_imm8, mov_BL_imm8, + mov_AH_imm8, mov_CH_imm8, mov_DH_imm8, mov_BH_imm8, + push_imm8, cmp_AL_imm8; + + ac_instr lds_r32_m16_32, les_r32_m16_32, lea_r32_m, mov_rm32_r32, + mov_r32_rm32, mov_rm32_imm32, /*xchg_EAX_r32, xchg_ECX_r32, + xchg_EDX_r32, xchg_EBX_r32, xchg_ESP_r32, xchg_EBP_r32, + xchg_ESI_r32, xchg_EDI_r32,*/ xchg_rm32_r32, push_rm32, + pop_rm32, in_EAX_imm8, out_imm8_EAX, + add_rm32_imm32, add_rm32_r32, add_r32_rm32, + adc_rm32_r32, adc_r32_rm32, + sub_rm32_r32, sub_r32_rm32, sbb_rm32_r32, + sbb_r32_rm32, mul_rm32, imul_r32_rm32_imm8, imul_r32_rm32_imm32, + cmp_rm32_r32, cmp_r32_rm32, + and_rm32_r32, and_r32_rm32, or_rm32_r32, + or_r32_rm32, xor_rm32_r32, xor_r32_rm32, + test_rm32_r32, + jmp_ptr16_32, add_rm32_imm8, + call_ptr16_32, ret_near, ret_far, ret_near_imm16, + ret_far_imm16, int_3, int_imm8, into, bound_r32_m32_32, + enter_imm16_0_1_imm8, inc_rm32, dec_rm32, jmp_rm32, + jmp_m16_32, call_rm32, call_m16_32, sub_rm32_imm32, + sub_rm32_imm8, sbb_rm32_imm32, sbb_rm32_imm8, + adc_rm32_imm32, adc_rm32_imm8, cmp_rm32_imm32, + cmp_rm32_imm8, and_rm32_imm32, and_rm32_imm8, + or_rm32_imm32, or_rm32_imm8, xor_rm32_imm32, + xor_rm32_imm8, div_rm32, idiv_rm32, imul_rm32, + neg_rm32, not_rm32, test_rm32_imm32, + sal_shl_1_rm32, sal_shl_cl_rm32, sal_shl_rm32_imm8, + sar_1_rm32, sar_cl_rm32, + sar_rm32_imm8, shr_1_rm32, shr_cl_rm32, shr_rm32_imm8, rcl_rm32, + rcl_rm32_imm8, rcr_rm32, rcr_rm32_imm8, rol_rm32, + rol_rm32_imm8, ror_rm32, ror_rm32_imm8, mov_rm8_imm8, + mov_r8_rm8, add_r8_rm8, mov_rm8_r8, inc_rm8, + add_rm8_imm8, add_rm8_r8, sub_rm8_r8, dec_rm8, sub_rm8_imm8, + imul_rm8, mul_rm8, sal_rm8, sar_rm8, sar_rm8_imm8, cmp_rm8_imm8, + shr_rm8_imm8, div_rm8, shr_rm8, and_r8_rm8, + or_r8_rm8, xor_r8_rm8, sal_rm8_imm8, cmp_r8_rm8; + + // Debug instructions, nonexistant in the instruction set + ac_instr dump_registers, dump_memory, dump_stack; + + ISA_CTOR(IA32) + { + // ------------------------------------------- + // Debug instructions ------------------------ + // ------------------------------------------- + + dump_registers.set_asm ( "DUMP REGISTERS" ); + dump_registers.set_decoder ( op2b=0xDD00 ); + + dump_memory.set_asm ( "DUMP MEMORY" ); + dump_memory.set_decoder ( op2b=0xAAAA ); + + dump_stack.set_asm ( "DUMP STACK" ); + dump_stack.set_decoder ( op2b=0xCC00 ); + + // ------------------------------------------- + // End debug instructions -------------------- + // ------------------------------------------- + + ud2.set_asm ( "UD2" ); + ud2.set_decoder ( op2b = 0x0B0F ); + + cpuid.set_asm ( "CPUID" ); + cpuid.set_decoder ( op2b = 0xA20F ); + + lss_r32_m16_32.set_asm ( "LSS" ); + lss_r32_m16_32.set_decoder ( op2b = 0xB20F ); + + lfs_r32_m16_32.set_asm ( "LFS" ); + lfs_r32_m16_32.set_decoder ( op2b = 0xB40F ); + + lgs_r32_m16_32.set_asm ( "LGS" ); + lgs_r32_m16_32.set_decoder ( op2b = 0xB50F ); + + cmov_a_nbe_r32_rm32.set_asm ( "CMOVA CMOVNBE" ); + cmov_a_nbe_r32_rm32.set_decoder ( op2b = 0x470F ); + cmov_ae_nb_nc_r32_rm32.set_asm ( "CMOVAE CMOVNB CMOVNC" ); + cmov_ae_nb_nc_r32_rm32.set_decoder ( op2b = 0x320F ); + cmov_b_c_nae_r32_rm32.set_asm ( "CMOVB CMOVC CMOVNAE" ); + cmov_b_c_nae_r32_rm32.set_decoder ( op2b = 0x420F ); + cmov_be_na_r32_rm32.set_asm ( "CMOVBE CMOVNA" ); + cmov_be_na_r32_rm32.set_decoder ( op2b = 0x460F ); + cmov_e_z_r32_rm32.set_asm ( "CMOVE CMOVZ" ); + cmov_e_z_r32_rm32.set_decoder ( op2b = 0x440F ); + cmov_g_nle_r32_rm32.set_asm ( "CMOVG CMOVNLE" ); + cmov_g_nle_r32_rm32.set_decoder ( op2b = 0x4F0F ); + cmov_ge_nl_r32_rm32.set_asm ( "CMOVGE CMOVNL" ); + cmov_ge_nl_r32_rm32.set_decoder ( op2b = 0x4D0F ); + cmov_l_nge_r32_rm32.set_asm ( "CMOVL CMOVNGE" ); + cmov_l_nge_r32_rm32.set_decoder ( op2b = 0x4C0F ); + cmov_le_ng_r32_rm32.set_asm ( "CMOVLE CMOVNG" ); + cmov_le_ng_r32_rm32.set_decoder ( op2b = 0x4E0F ); + cmov_ne_nz_r32_rm32.set_asm ( "CMOVNE CMOVNZ" ); + cmov_ne_nz_r32_rm32.set_decoder ( op2b = 0x450F ); + cmov_no_r32_rm32.set_asm ( "CMOVNO" ); + cmov_no_r32_rm32.set_decoder ( op2b = 0x410F ); + cmov_np_po_r32_rm32.set_asm ( "CMOVNP CMOVPO" ); + cmov_np_po_r32_rm32.set_decoder ( op2b = 0x4B0F ); + cmov_ns_r32_rm32.set_asm ( "CMOVNS" ); + cmov_ns_r32_rm32.set_decoder ( op2b = 0x490F ); + cmov_o_r32_rm32.set_asm ( "CMOVO" ); + cmov_o_r32_rm32.set_decoder ( op2b = 0x400F ); + cmov_p_pe_r32_rm32.set_asm ( "CMOVP CMOVPE" ); + cmov_p_pe_r32_rm32.set_decoder ( op2b = 0x4A0F ); + cmov_s_r32_rm32.set_asm ( "CMOVS" ); + cmov_s_r32_rm32.set_decoder ( op2b = 0x480F ); + + bswap_EAX_r32.set_asm ( "BSWAP" ); + bswap_EAX_r32.set_decoder ( op2b = 0xC80F ); + bswap_ECX_r32.set_asm ( "BSWAP" ); + bswap_ECX_r32.set_decoder ( op2b = 0xC90F ); + bswap_EDX_r32.set_asm ( "BSWAP" ); + bswap_EDX_r32.set_decoder ( op2b = 0xCA0F ); + bswap_EBX_r32.set_asm ( "BSWAP" ); + bswap_EBX_r32.set_decoder ( op2b = 0xCB0F ); + bswap_ESP_r32.set_asm ( "BSWAP" ); + bswap_ESP_r32.set_decoder ( op2b = 0xCC0F ); + bswap_EBP_r32.set_asm ( "BSWAP" ); + bswap_EBP_r32.set_decoder ( op2b = 0xCD0F ); + bswap_ESI_r32.set_asm ( "BSWAP" ); + bswap_ESI_r32.set_decoder ( op2b = 0xCE0F ); + bswap_EDI_r32.set_asm ( "BSWAP" ); + bswap_EDI_r32.set_decoder ( op2b = 0xCF0F ); + + xadd_rm32_r32.set_asm ( "XADD" ); + xadd_rm32_r32.set_decoder ( op2b = 0xC10F ); + + cmpxchg_rm32_r32.set_asm ( "CMPXCHG" ); + cmpxchg_rm32_r32.set_decoder ( op2b = 0xB10F ); + + cmpxchg8b_m64.set_asm ( "CMPXCHG8B" ); + cmpxchg8b_m64.set_decoder ( op2b = 0xC70F ); + + push_FS.set_asm ( "PUSH" ); + push_FS.set_decoder ( op2b = 0xA00F ); + push_GS.set_asm ( "PUSH" ); + push_GS.set_decoder ( op2b = 0xA80F ); + + pop_FS.set_asm ( "POP" ); + pop_FS.set_decoder ( op2b = 0xA10F ); + pop_GS.set_asm ( "POP" ); + pop_GS.set_decoder ( op2b = 0xA90F ); + + movsx_r32_rm8.set_asm ( "MOVSX" ); + movsx_r32_rm8.set_decoder ( op2b = 0xBE0F ); + movsx_r32_rm16.set_asm ( "MOVSX" ); + movsx_r32_rm16.set_decoder ( op2b = 0xBF0F ); + + movzx_r32_rm8.set_asm ( "MOVZX" ); + movzx_r32_rm8.set_decoder ( op2b = 0xB60F ); + movzx_r32_rm16.set_asm ( "MOVZX" ); + movzx_r32_rm16.set_decoder ( op2b = 0xB70F ); + + imul_r32_rm32.set_asm ( "IMUL R32, RM32" ); + imul_r32_rm32.set_decoder ( op2b = 0xAF0F ); + + aam.set_asm ( "AAM" ); + aam.set_decoder ( op2b = 0x0AD4 ); + + aad.set_asm ( "AAD" ); + aad.set_decoder ( op2b = 0x0AD5 ); + + shrd_rm32_r32_imm8.set_asm ( "SHRD" ); + shrd_rm32_r32_imm8.set_decoder ( op2b = 0xAC0F ); + shrd_rm32_r32_CL.set_asm ( "SHRD" ); + shrd_rm32_r32_CL.set_decoder ( op2b = 0xAD0F ); + + shld_rm32_r32_imm8.set_asm ( "SHLD" ); + shld_rm32_r32_imm8.set_decoder ( op2b = 0xA40F ); + shld_rm32_r32_CL.set_asm ( "SHLD" ); + shld_rm32_r32_CL.set_decoder ( op2b = 0xA50F ); + + bt_rm32_r32.set_asm ( "BT" ); + bt_rm32_r32.set_decoder ( op2b = 0xA30F ); + bt_rm32_imm8.set_asm ( "BT" ); + bt_rm32_imm8.set_decoder ( op2b = 0xBA0F, regop2 = 0x04 ); + + // Expansao: + bts_rm32_imm8.set_asm ( "BTS" ); + bts_rm32_imm8.set_decoder ( op2b = 0xBA0F, regop2 = 0x05 ); + btr_rm32_imm8.set_asm ( "BTR" ); + btr_rm32_imm8.set_decoder ( op2b = 0xBA0F, regop2 = 0x06 ); + btc_rm32_imm8.set_asm ( "BTC" ); + btc_rm32_imm8.set_decoder ( op2b = 0xBA0F, regop2 = 0x07 ); + // end + + bts_rm32_r32.set_asm ( "BTS" ); + bts_rm32_r32.set_decoder ( op2b = 0xAB0F ); + + btr_rm32_r32.set_asm ( "BTR" ); + btr_rm32_r32.set_decoder ( op2b = 0xB30F ); + + btc_rm32_r32.set_asm ( "BTC" ); + btc_rm32_r32.set_decoder ( op2b = 0xBB0F ); + + bsf_r32_rm32.set_asm ( "BSF" ); + bsf_r32_rm32.set_decoder ( op2b = 0xBC0F ); + + bsr_r32_rm32.set_asm ( "BSR" ); + bsr_r32_rm32.set_decoder ( op2b = 0xBD0F ); + + seta_setnbe_rm8.set_asm ( "SETA SETNBE" ); + seta_setnbe_rm8.set_decoder ( op2b = 0x970F ); + + setae_setnb_setnc_rm8.set_asm ( "SETAE SETNB SETNC" ); + setae_setnb_setnc_rm8.set_decoder ( op2b = 0x930F ); + + setb_setc_setnae_rm8.set_asm ( "SETB SETC SETNAE" ); + setb_setc_setnae_rm8.set_decoder ( op2b = 0x920F ); + + setbe_setna_rm8.set_asm ( "SETBE SETNA" ); + setbe_setna_rm8.set_decoder ( op2b = 0x960F ); + + sete_setz_rm8.set_asm ( "SETE SETZ" ); + sete_setz_rm8.set_decoder ( op2b = 0x940F ); + + setg_setnle_rm8.set_asm ( "SETG SETNLE" ); + setg_setnle_rm8.set_decoder ( op2b = 0x9F0F ); + + setge_setnl_rm8.set_asm ( "SETGE SETNL" ); + setge_setnl_rm8.set_decoder ( op2b = 0x9D0F ); + + setl_setnge_rm8.set_asm ( "SETL SETNGE" ); + setl_setnge_rm8.set_decoder ( op2b = 0x9C0F ); + + setle_setng_rm8.set_asm ( "SETLE SETNG" ); + setle_setng_rm8.set_decoder ( op2b = 0x9E0F ); + + setne_setnz_rm8.set_asm ( "SETNE SETNZ" ); + setne_setnz_rm8.set_decoder ( op2b = 0x950F ); + + setno_rm8.set_asm ( "SETNO" ); + setno_rm8.set_decoder ( op2b = 0x910F ); + + setnp_setpo_rm8.set_asm ( "SETNP SETPO" ); + setnp_setpo_rm8.set_decoder ( op2b = 0x9B0F ); + + setns_rm8.set_asm ( "SETNS" ); + setns_rm8.set_decoder ( op2b = 0x990F ); + + seto_rm8.set_asm ( "SETO" ); + seto_rm8.set_decoder ( op2b = 0x900F ); + + setp_setpe_rm8.set_asm ( "SETP SETPE" ); + setp_setpe_rm8.set_decoder ( op2b = 0x9A0F ); + + sets_rm8.set_asm ( "SETS" ); + sets_rm8.set_decoder ( op2b = 0x980F ); + + ja_jnbe_rel16_32.set_asm ( "JA JNBE" ); + ja_jnbe_rel16_32.set_decoder ( op2b = 0x870F ); + + jae_jnb_jnc_rel16_32.set_asm ( "JAE JNB JNC" ); + jae_jnb_jnc_rel16_32.set_decoder ( op2b = 0x830F ); + + jb_jc_jnae_rel16_32.set_asm ( "JB JC JNAE" ); + jb_jc_jnae_rel16_32.set_decoder ( op2b = 0x820F ); + + jbe_jna_rel16_32.set_asm ( "JBE JNA" ); + jbe_jna_rel16_32.set_decoder ( op2b = 0x860F ); + + je_jz_rel16_32.set_asm ( "JE JZ" ); + je_jz_rel16_32.set_decoder ( op2b = 0x840F ); + + jg_jnle_rel16_32.set_asm ( "JG JNLE" ); + jg_jnle_rel16_32.set_decoder ( op2b = 0x8F0F ); + + jge_jnl_rel16_32.set_asm ( "JGE JNL" ); + jge_jnl_rel16_32.set_decoder ( op2b = 0x8D0F ); + + jl_jnge_rel16_32.set_asm ( "JL JNGE" ); + jl_jnge_rel16_32.set_decoder ( op2b = 0x8C0F ); + + jle_jng_rel16_32.set_asm ( "JLE JNG" ); + jle_jng_rel16_32.set_decoder ( op2b = 0x8E0F ); + + jne_jnz_rel16_32.set_asm ( "JNE JNZ" ); + jne_jnz_rel16_32.set_decoder ( op2b = 0x850F ); + + jno_rel16_32.set_asm ( "JNO" ); + jno_rel16_32.set_decoder ( op2b = 0x810F ); + + jnp_jpo_rel16_32.set_asm ( "JNP JPO" ); + jnp_jpo_rel16_32.set_decoder ( op2b = 0x8B0F ); + + jns_rel16_32.set_asm ( "JNS" ); + jns_rel16_32.set_decoder ( op2b = 0x890F ); + + jo_rel16_32.set_asm ( "JO" ); + jo_rel16_32.set_decoder ( op2b = 0x800F ); + + jp_jpe_rel16_32.set_asm ( "JP JPE" ); + jp_jpe_rel16_32.set_decoder ( op2b = 0x8A0F ); + + js_rel16_32.set_asm ( "JS" ); + js_rel16_32.set_decoder ( op2b = 0x880F ); + + jmp_rel32.set_asm ( "JMP" ); + jmp_rel32.set_decoder ( op1b = 0xE9 ); + + jmp_ptr16_32.set_asm ( "JMP" ); + jmp_ptr16_32.set_decoder ( op1b = 0xEA ); + + jcxz_jecxz_rel8.set_asm ( "JCXZ JECXZ" ); + jcxz_jecxz_rel8.set_decoder ( op1b = 0xE3 ); + + loop_rel8.set_asm ( "LOOP" ); + loop_rel8.set_decoder ( op1b = 0xE2 ); + + loope_loopz_rel8.set_asm ( "LOOPE LOOPZ" ); + loope_loopz_rel8.set_decoder ( op1b = 0xE1 ); + + loopne_loopnz_rel8.set_asm ( "LOOPNE LOOPNZ" ); + loopne_loopnz_rel8.set_decoder ( op1b = 0xE0 ); + + call_rel32.set_asm ( "CALL" ); + call_rel32.set_decoder ( op1b = 0xE8 ); + call_ptr16_32.set_asm ( "CALL" ); + call_ptr16_32.set_decoder ( op1b = 0x9A ); + + ret_near.set_asm ( "RET" ); + ret_near.set_decoder ( op1b = 0xC3 ); + ret_far.set_asm ( "RET" ); + ret_far.set_decoder ( op1b = 0xCB ); + ret_near_imm16.set_asm ( "RET" ); + ret_near_imm16.set_decoder ( op1b = 0xC2 ); + ret_far_imm16.set_asm ( "RET" ); + ret_far_imm16.set_decoder ( op1b = 0xCA ); + + iret_iretd.set_asm ( "IRET IRETD" ); + iret_iretd.set_decoder ( op1b = 0xCF ); + + int_3.set_asm ( "INT3" ); + int_3.set_decoder ( op1b = 0xCC ); + int_imm8.set_asm ( "INT" ); + int_imm8.set_decoder ( op1b = 0xCD ); + into.set_asm ( "INTO" ); + into.set_decoder ( op1b = 0xCE ); + + bound_r32_m32_32.set_asm ( "BOUND" ); + bound_r32_m32_32.set_decoder ( op1b = 0x62 ); + + enter_imm16_0_1_imm8.set_asm ( "ENTER" ); + enter_imm16_0_1_imm8.set_decoder ( op1b = 0xC8 ); + + leave.set_asm ( "LEAVE" ); + leave.set_decoder ( op1b = 0xC9 ); + + movs_m32_m32.set_asm ( "MOVS" ); + movs_m32_m32.set_decoder ( op1b = 0xA5 ); + + cmps_m32_m32.set_asm ( "CMPS" ); + cmps_m32_m32.set_decoder ( op1b = 0xA7 ); + + scas_m32.set_asm ( "SCAS" ); + scas_m32.set_decoder ( op1b = 0xAF ); + + lods_m32.set_asm ( "LODS" ); + lods_m32.set_decoder ( op1b = 0xAD ); + + stos_m32.set_asm ( "STOS" ); + stos_m32.set_decoder ( op1b = 0xAB ); + + insd.set_asm ( "INSD" ); + insd.set_decoder ( op1b = 0x6D ); + + outsd.set_asm ( "OUTSD" ); + outsd.set_decoder ( op1b = 0x6F ); + + stc.set_asm ( "STC" ); + stc.set_decoder ( op1b = 0xF9 ); + + clc.set_asm ( "CLC" ); + clc.set_decoder ( op1b = 0xF8 ); + + cmc.set_asm ( "CMC" ); + cmc.set_decoder ( op1b = 0xF5 ); + + cld.set_asm ( "CLD" ); + cld.set_decoder ( op1b = 0xFC ); + + std.set_asm ( "STD" ); + std.set_decoder ( op1b = 0xFD ); + + lahf.set_asm ( "LAHF" ); + lahf.set_decoder ( op1b = 0x9F ); + + sahf.set_asm ( "SAHF" ); + sahf.set_decoder ( op1b = 0x9E ); + + pushfd.set_asm ( "PUSHFD" ); + pushfd.set_decoder ( op1b = 0x9C ); + + popfd.set_asm ( "POPFD" ); + popfd.set_decoder ( op1b = 0x9D ); + + sti.set_asm ( "STI" ); + sti.set_decoder ( op1b = 0xFB ); + + cli.set_asm ( "CLI" ); + cli.set_decoder ( op1b = 0xFA ); + + nop.set_asm ( "NOP" ); + nop.set_decoder ( op1b = 0x90 ); + + xlatb.set_asm ( "XLATB" ); + xlatb.set_decoder ( op1b = 0xD7 ); + + lds_r32_m16_32.set_asm ( "LDS" ); + lds_r32_m16_32.set_decoder ( op1b = 0xC5 ); + + les_r32_m16_32.set_asm ( "LES" ); + les_r32_m16_32.set_decoder ( op1b = 0xC4 ); + + lea_r32_m.set_asm ( "LEA" ); + lea_r32_m.set_decoder ( op1b = 0x8D ); + + mov_rm32_r32.set_asm ( "MOV" ); + mov_rm32_r32.set_decoder ( op1b = 0x89 ); + mov_r32_rm32.set_asm ( "MOV" ); + mov_r32_rm32.set_decoder ( op1b = 0x8B ); + mov_EAX_imm32.set_asm ( "MOV" ); + mov_EAX_imm32.set_decoder ( op1b = 0xB8 ); + mov_ECX_imm32.set_asm ( "MOV" ); + mov_ECX_imm32.set_decoder ( op1b = 0xB9 ); + mov_EDX_imm32.set_asm ( "MOV" ); + mov_EDX_imm32.set_decoder ( op1b = 0xBA ); + mov_EBX_imm32.set_asm ( "MOV" ); + mov_EBX_imm32.set_decoder ( op1b = 0xBB ); + mov_ESP_imm32.set_asm ( "MOV" ); + mov_ESP_imm32.set_decoder ( op1b = 0xBC ); + mov_EBP_imm32.set_asm ( "MOV" ); + mov_EBP_imm32.set_decoder ( op1b = 0xBD ); + mov_ESI_imm32.set_asm ( "MOV" ); + mov_ESI_imm32.set_decoder ( op1b = 0xBE ); + mov_EDI_imm32.set_asm ( "MOV" ); + mov_EDI_imm32.set_decoder ( op1b = 0xBF ); + mov_rm32_imm32.set_asm ( "MOV" ); + mov_rm32_imm32.set_decoder ( op1b = 0xC7 ); + + // Sidenote: xchg_EAX_EAX is evaluated as NOP by Intel design decision + //xchg_EAX_EAX.set_asm ( "XCHG" ); + //xchg_EAX_EAX.set_decoder ( op1b = 0x90 ); + xchg_EAX_ECX.set_asm ( "XCHG" ); + xchg_EAX_ECX.set_decoder ( op1b = 0x91 ); + xchg_EAX_EDX.set_asm ( "XCHG" ); + xchg_EAX_EDX.set_decoder ( op1b = 0x92 ); + xchg_EAX_EBX.set_asm ( "XCHG" ); + xchg_EAX_EBX.set_decoder ( op1b = 0x93 ); + xchg_EAX_ESP.set_asm ( "XCHG" ); + xchg_EAX_ESP.set_decoder ( op1b = 0x94 ); + xchg_EAX_EBP.set_asm ( "XCHG" ); + xchg_EAX_EBP.set_decoder ( op1b = 0x95 ); + xchg_EAX_ESI.set_asm ( "XCHG" ); + xchg_EAX_ESI.set_decoder ( op1b = 0x96 ); + xchg_EAX_EDI.set_asm ( "XCHG" ); + xchg_EAX_EDI.set_decoder ( op1b = 0x97 ); + xchg_rm32_r32.set_asm ( "XCHG" ); + xchg_rm32_r32.set_decoder ( op1b = 0x87 ); + + // Expansao + inc_rm32.set_asm ( "INC" ); + inc_rm32.set_decoder ( op1b = 0xFF, regop = 0x00 ); + dec_rm32.set_asm ( "DEC" ); + dec_rm32.set_decoder ( op1b = 0xFF, regop = 0x01 ); + jmp_rm32.set_asm ( "JMP" ); + jmp_rm32.set_decoder ( op1b = 0xFF, regop = 0x04 ); + jmp_m16_32.set_asm ( "JMP" ); + jmp_m16_32.set_decoder ( op1b = 0xFF, regop = 0x05 ); + call_rm32.set_asm ( "CALL" ); + call_rm32.set_decoder ( op1b = 0xFF, regop = 0x02 ); + call_m16_32.set_asm ( "CALL" ); + call_m16_32.set_decoder ( op1b = 0xFF, regop = 0x03 ); + // end + + push_rm32.set_asm ( "PUSH" ); + push_rm32.set_decoder ( op1b = 0xFF, regop = 0x06 ); + push_EAX.set_asm ( "PUSH" ); + push_EAX.set_decoder ( op1b = 0x50 ); + push_ECX.set_asm ( "PUSH" ); + push_ECX.set_decoder ( op1b = 0x51 ); + push_EDX.set_asm ( "PUSH" ); + push_EDX.set_decoder ( op1b = 0x52 ); + push_EBX.set_asm ( "PUSH" ); + push_EBX.set_decoder ( op1b = 0x53 ); + push_ESP.set_asm ( "PUSH" ); + push_ESP.set_decoder ( op1b = 0x54 ); + push_EBP.set_asm ( "PUSH" ); + push_EBP.set_decoder ( op1b = 0x55 ); + push_ESI.set_asm ( "PUSH" ); + push_ESI.set_decoder ( op1b = 0x56 ); + push_EDI.set_asm ( "PUSH" ); + push_EDI.set_decoder ( op1b = 0x57 ); + push_imm32.set_asm ( "PUSH" ); + push_imm32.set_decoder ( op1b = 0x68 ); + push_CS.set_asm ( "PUSH" ); + push_CS.set_decoder ( op1b = 0x0E ); + push_SS.set_asm ( "PUSH" ); + push_SS.set_decoder ( op1b = 0x16 ); + push_DS.set_asm ( "PUSH" ); + push_DS.set_decoder ( op1b = 0x1E ); + push_ES.set_asm ( "PUSH" ); + push_ES.set_decoder ( op1b = 0x06 ); + + push_a_ad.set_asm ( "PUSHA PUSHAD" ); + push_a_ad.set_decoder ( op1b = 0x60 ); + + pop_a_ad.set_asm ( "POPA POPAD" ); + pop_a_ad.set_decoder ( op1b = 0x61 ); + + in_EAX_imm8.set_asm ( "IN" ); + in_EAX_imm8.set_decoder ( op1b = 0xE5 ); + in_EAX_DX.set_asm ( "IN" ); + in_EAX_DX.set_decoder ( op1b = 0xED ); + + out_imm8_EAX.set_asm ( "OUT" ); + out_imm8_EAX.set_decoder ( op1b = 0xE7 ); + out_DX_EAX.set_asm ( "OUT" ); + out_DX_EAX.set_decoder ( op1b = 0xEF ); + + cwd_cwq.set_asm ( "CWD CWQ" ); + cwd_cwq.set_decoder ( op1b = 0x99 ); + + cbw_cwde.set_asm ( "CBW CWDE" ); + cbw_cwde.set_decoder ( op1b = 0x98 ); + + pop_rm32.set_asm ( "POP" ); + pop_rm32.set_decoder ( op1b = 0x8F ); + pop_EAX.set_asm ( "POP" ); + pop_EAX.set_decoder ( op1b = 0x58 ); + pop_ECX.set_asm ( "POP" ); + pop_ECX.set_decoder ( op1b = 0x59 ); + pop_EDX.set_asm ( "POP" ); + pop_EDX.set_decoder ( op1b = 0x5A ); + pop_EBX.set_asm ( "POP" ); + pop_EBX.set_decoder ( op1b = 0x5B ); + pop_ESP.set_asm ( "POP" ); + pop_ESP.set_decoder ( op1b = 0x5C ); + pop_EBP.set_asm ( "POP" ); + pop_EBP.set_decoder ( op1b = 0x5D ); + pop_ESI.set_asm ( "POP" ); + pop_ESI.set_decoder ( op1b = 0x5E ); + pop_EDI.set_asm ( "POP" ); + pop_EDI.set_decoder ( op1b = 0x5F ); + pop_DS.set_asm ( "POP" ); + pop_DS.set_decoder ( op1b = 0x1F ); + pop_ES.set_asm ( "POP" ); + pop_ES.set_decoder ( op1b = 0x07 ); + pop_SS.set_asm ( "POP" ); + pop_SS.set_decoder ( op1b = 0x17 ); + + add_EAX_imm32.set_asm ( "ADD" ); + add_EAX_imm32.set_decoder ( op1b = 0x05 ); + add_rm32_imm32.set_asm ( "ADD" ); + add_rm32_imm32.set_decoder ( op1b = 0x81, regop = 0x00 ); + add_rm32_imm8.set_asm ( "ADD" ); + add_rm32_imm8.set_decoder ( op1b = 0x83, regop = 0x00 ); + add_rm32_r32.set_asm ( "ADD" ); + add_rm32_r32.set_decoder ( op1b = 0x01 ); + add_r32_rm32.set_asm ( "ADD" ); + add_r32_rm32.set_decoder ( op1b = 0x03 ); + + // Expansion: + sub_rm32_imm32.set_asm ( "SUB" ); + sub_rm32_imm32.set_decoder ( op1b = 0x81, regop = 0x05 ); + sub_rm32_imm8.set_asm ( "SUB" ); + sub_rm32_imm8.set_decoder ( op1b = 0x83, regop = 0x05 ); + sbb_rm32_imm32.set_asm ( "SBB" ); + sbb_rm32_imm32.set_decoder ( op1b = 0x81, regop = 0x03 ); + sbb_rm32_imm8.set_asm ( "SBB" ); + sbb_rm32_imm8.set_decoder ( op1b = 0x83, regop = 0x03 ); + adc_rm32_imm32.set_asm ( "ADC" ); + adc_rm32_imm32.set_decoder ( op1b = 0x81, regop = 0x02 ); + adc_rm32_imm8.set_asm ( "ADC" ); + adc_rm32_imm8.set_decoder ( op1b = 0x83, regop = 0x02 ); + cmp_rm32_imm32.set_asm ( "CMP" ); + cmp_rm32_imm32.set_decoder ( op1b = 0x81, regop = 0x07 ); + cmp_rm32_imm8.set_asm ( "CMP" ); + cmp_rm32_imm8.set_decoder ( op1b = 0x83, regop = 0x07 ); + and_rm32_imm32.set_asm ( "AND" ); + and_rm32_imm32.set_decoder ( op1b = 0x81, regop = 0x04 ); + and_rm32_imm8.set_asm ( "AND" ); + and_rm32_imm8.set_decoder ( op1b = 0x83, regop = 0x04 ); + or_rm32_imm32.set_asm ( "OR" ); + or_rm32_imm32.set_decoder ( op1b = 0x81, regop = 0x01 ); + or_rm32_imm8.set_asm ( "OR" ); + or_rm32_imm8.set_decoder ( op1b = 0x83, regop = 0x01 ); + xor_rm32_imm32.set_asm ( "XOR" ); + xor_rm32_imm32.set_decoder ( op1b = 0x81, regop = 0x06 ); + xor_rm32_imm8.set_asm ( "XOR" ); + xor_rm32_imm8.set_decoder ( op1b = 0x83, regop = 0x06 ); + // end + + adc_EAX_imm32.set_asm ( "ADC" ); + adc_EAX_imm32.set_decoder ( op1b = 0x15 ); + adc_rm32_r32.set_asm ( "ADC" ); + adc_rm32_r32.set_decoder ( op1b = 0x11 ); + adc_r32_rm32.set_asm ( "ADC" ); + adc_r32_rm32.set_decoder ( op1b = 0x13 ); + + sub_EAX_imm32.set_asm ( "SUB" ); + sub_EAX_imm32.set_decoder ( op1b = 0x2D ); + sub_rm32_r32.set_asm ( "SUB" ); + sub_rm32_r32.set_decoder ( op1b = 0x29 ); + sub_r32_rm32.set_asm ( "SUB" ); + sub_r32_rm32.set_decoder ( op1b = 0x2B ); + + sbb_EAX_imm32.set_asm ( "SBB" ); + sbb_EAX_imm32.set_decoder ( op1b = 0x1D ); + sbb_rm32_r32.set_asm ( "SBB" ); + sbb_rm32_r32.set_decoder ( op1b = 0x19 ); + sbb_r32_rm32.set_asm ( "SBB" ); + sbb_r32_rm32.set_decoder ( op1b = 0x1B ); + + mul_rm32.set_asm ( "MUL" ); + mul_rm32.set_decoder ( op1b = 0xF7, regop = 0x04 ); + + // Expansao: + div_rm32.set_asm ( "DIV" ); + div_rm32.set_decoder ( op1b = 0xF7, regop = 0x06 ); + idiv_rm32.set_asm ( "IDIV" ); + idiv_rm32.set_decoder ( op1b = 0xF7, regop = 0x07 ); + imul_rm32.set_asm ( "IMUL" ); + imul_rm32.set_decoder ( op1b = 0xF7, regop = 0x05 ); + neg_rm32.set_asm ( "NEG" ); + neg_rm32.set_decoder ( op1b = 0xF7, regop = 0x03 ); + not_rm32.set_asm ( "NOT" ); + not_rm32.set_decoder ( op1b = 0xF7, regop = 0x02 ); + test_rm32_imm32.set_asm ( "TEST" ); + test_rm32_imm32.set_decoder ( op1b = 0xF7, regop = 0x00 ); + // end + + imul_r32_rm32_imm8.set_asm ( "IMUL" ); + imul_r32_rm32_imm8.set_decoder ( op1b = 0x6B ); + imul_r32_rm32_imm32.set_asm ( "IMUL" ); + imul_r32_rm32_imm32.set_decoder ( op1b = 0x69 ); + + inc_EAX.set_asm ( "INC" ); + inc_EAX.set_decoder ( op1b = 0x40 ); + inc_ECX.set_asm ( "INC" ); + inc_ECX.set_decoder ( op1b = 0x41 ); + inc_EDX.set_asm ( "INC" ); + inc_EDX.set_decoder ( op1b = 0x42 ); + inc_EBX.set_asm ( "INC" ); + inc_EBX.set_decoder ( op1b = 0x43 ); + inc_ESP.set_asm ( "INC" ); + inc_ESP.set_decoder ( op1b = 0x44 ); + inc_EBP.set_asm ( "INC" ); + inc_EBP.set_decoder ( op1b = 0x45 ); + inc_ESI.set_asm ( "INC" ); + inc_ESI.set_decoder ( op1b = 0x46 ); + inc_EDI.set_asm ( "INC" ); + inc_EDI.set_decoder ( op1b = 0x47 ); + + dec_EAX.set_asm ( "DEC" ); + dec_EAX.set_decoder ( op1b = 0x48 ); + dec_ECX.set_asm ( "DEC" ); + dec_ECX.set_decoder ( op1b = 0x49 ); + dec_EDX.set_asm ( "DEC" ); + dec_EDX.set_decoder ( op1b = 0x4A ); + dec_EBX.set_asm ( "DEC" ); + dec_EBX.set_decoder ( op1b = 0x4B ); + dec_ESP.set_asm ( "DEC" ); + dec_ESP.set_decoder ( op1b = 0x4C ); + dec_EBP.set_asm ( "DEC" ); + dec_EBP.set_decoder ( op1b = 0x4D ); + dec_ESI.set_asm ( "DEC" ); + dec_ESI.set_decoder ( op1b = 0x4E ); + dec_EDI.set_asm ( "DEC" ); + dec_EDI.set_decoder ( op1b = 0x4F ); + + cmp_EAX_imm32.set_asm ( "CMP" ); + cmp_EAX_imm32.set_decoder ( op1b = 0x3D ); + cmp_rm32_r32.set_asm ( "CMP" ); + cmp_rm32_r32.set_decoder ( op1b = 0x39 ); + cmp_r32_rm32.set_asm ( "CMP" ); + cmp_r32_rm32.set_decoder ( op1b = 0x3B ); + + daa.set_asm ( "DAA" ); + daa.set_decoder ( op1b = 0x27 ); + + das.set_asm ( "DAS" ); + das.set_decoder ( op1b = 0x2F ); + + aaa.set_asm ( "AAA" ); + aaa.set_decoder ( op1b = 0x37 ); + + aas.set_asm ( "AAS" ); + aas.set_decoder ( op1b = 0x3F ); + + and_EAX_imm32.set_asm ( "AND" ); + and_EAX_imm32.set_decoder ( op1b = 0x25 ); + and_rm32_r32.set_asm ( "AND" ); + and_rm32_r32.set_decoder ( op1b = 0x21 ); + and_r32_rm32.set_asm ( "AND" ); + and_r32_rm32.set_decoder ( op1b = 0x23 ); + + or_EAX_imm32.set_asm ( "OR" ); + or_EAX_imm32.set_decoder ( op1b = 0x0D ); + or_rm32_r32.set_asm ( "OR" ); + or_rm32_r32.set_decoder ( op1b = 0x09 ); + or_r32_rm32.set_asm ( "OR" ); + or_r32_rm32.set_decoder ( op1b = 0x0B ); + + xor_EAX_imm32.set_asm ( "XOR" ); + xor_EAX_imm32.set_decoder ( op1b = 0x35 ); + xor_rm32_r32.set_asm ( "XOR" ); + xor_rm32_r32.set_decoder ( op1b = 0x31 ); + xor_r32_rm32.set_asm ( "XOR" ); + xor_r32_rm32.set_decoder ( op1b = 0x33 ); + + // Expansao + sal_shl_1_rm32.set_asm ( "SAL/SHL" ); + sal_shl_1_rm32.set_decoder ( op1b = 0xD1, regop = 0x04 ); + sal_shl_cl_rm32.set_asm ( "SAL SHL" ); + sal_shl_cl_rm32.set_decoder ( op1b = 0xD3, regop = 0x04 ); + sal_shl_rm32_imm8.set_asm ( "SAL/SHL" ); + sal_shl_rm32_imm8.set_decoder ( op1b = 0xC1, regop = 0x04 ); + sar_1_rm32.set_asm ( "SAR" ); + sar_1_rm32.set_decoder ( op1b = 0xD1, regop = 0x07 ); + sar_cl_rm32.set_asm ( "SAR" ); + sar_cl_rm32.set_decoder ( op1b = 0xD3, regop = 0x07 ); + sar_rm32_imm8.set_asm ( "SAR" ); + sar_rm32_imm8.set_decoder ( op1b = 0xC1, regop = 0x07 ); + shr_1_rm32.set_asm ( "SHR" ); + shr_1_rm32.set_decoder ( op1b = 0xD1, regop = 0x05 ); + shr_cl_rm32.set_asm ( "SHR" ); + shr_cl_rm32.set_decoder ( op1b = 0xD3, regop = 0x05 ); + shr_rm32_imm8.set_asm ( "SHR" ); + shr_rm32_imm8.set_decoder ( op1b = 0xC1, regop = 0x05 ); + rcl_rm32.set_asm ( "RCL" ); + rcl_rm32.set_decoder ( op1b = 0xD1, regop = 0x02 ); + rcl_rm32_imm8.set_asm ( "RCL" ); + rcl_rm32_imm8.set_decoder ( op1b = 0xC1, regop = 0x02 ); + rcr_rm32.set_asm ( "RCR" ); + rcr_rm32.set_decoder ( op1b = 0xD1, regop = 0x03 ); + rcr_rm32_imm8.set_asm ( "RCR" ); + rcr_rm32_imm8.set_decoder ( op1b = 0xC1, regop = 0x03 ); + rol_rm32.set_asm ( "ROL" ); + rol_rm32.set_decoder ( op1b = 0xD1, regop = 0x00 ); + rol_rm32_imm8.set_asm ( "ROL" ); + rol_rm32_imm8.set_decoder ( op1b = 0xC1, regop = 0x00 ); + ror_rm32.set_asm ( "ROR" ); + ror_rm32.set_decoder ( op1b = 0xD1, regop = 0x01 ); + ror_rm32_imm8.set_asm ( "ROR" ); + ror_rm32_imm8.set_decoder ( op1b = 0xC1, regop = 0x01 ); + // end + + test_eax_imm32.set_asm ( "TEST" ); + test_eax_imm32.set_decoder ( op1b = 0xA9 ); + test_rm32_r32.set_asm ( "TEST" ); + test_rm32_r32.set_decoder ( op1b = 0x85 ); + + ja_jnbe_rel8.set_asm ( "JA JNBE" ); + ja_jnbe_rel8.set_decoder ( op1b = 0x77 ); + + jae_jnb_jnc_rel8.set_asm ( "JAE JNB JNC" ); + jae_jnb_jnc_rel8.set_decoder ( op1b = 0x73 ); + + jb_jc_jnae_rel8.set_asm ( "JB JC JNAE" ); + jb_jc_jnae_rel8.set_decoder ( op1b = 0x72 ); + + jbe_jna_rel8.set_asm ( "JBE JNA" ); + jbe_jna_rel8.set_decoder ( op1b = 0x76 ); + + je_jz_rel8.set_asm ( "JE JZ" ); + je_jz_rel8.set_decoder ( op1b = 0x74 ); + + jg_jnle_rel8.set_asm ( "JG JNLE" ); + jg_jnle_rel8.set_decoder ( op1b = 0x7F ); + + jge_jnl_rel8.set_asm ( "JGE JNL" ); + jge_jnl_rel8.set_decoder ( op1b = 0x7D ); + + jl_jnge_rel8.set_asm ( "JL JNGE" ); + jl_jnge_rel8.set_decoder ( op1b = 0x7C ); + + jle_jng_rel8.set_asm ( "JLE JNG" ); + jle_jng_rel8.set_decoder ( op1b = 0x7E ); + + jne_jnz_rel8.set_asm ( "JNE JNZ" ); + jne_jnz_rel8.set_decoder ( op1b = 0x75 ); + + jno_rel8.set_asm ( "JNO" ); + jno_rel8.set_decoder ( op1b = 0x71 ); + + jnp_jpo_rel8.set_asm ( "JNP JPO" ); + jnp_jpo_rel8.set_decoder ( op1b = 0x7B ); + + jns_rel8.set_asm ( "JNS" ); + jns_rel8.set_decoder ( op1b = 0x79 ); + + jo_rel8.set_asm ( "JO" ); + jo_rel8.set_decoder ( op1b = 0x70 ); + + jp_jpe_rel8.set_asm ( "JP JPE" ); + jp_jpe_rel8.set_decoder ( op1b = 0x7A ); + + js_rel8.set_asm ( "JS" ); + js_rel8.set_decoder ( op1b = 0x78 ); + + P_LOCK.set_asm ( "LOCK PREFIX" ); + P_LOCK.set_decoder ( op1b = 0xF0 ); + + P_REPNE_REPNZ.set_asm ( "REPNE/REPNZ PREFIX" ); + P_REPNE_REPNZ.set_decoder ( op1b = 0xF2 ); + + P_REP_REPE_REPZ.set_asm ( "REP/REPE/REPZ PREFIX" ); + P_REP_REPE_REPZ.set_decoder ( op1b = 0xF3 ); + + P_CS.set_asm ( "CS OVERRIDE PREFIX" ); + P_CS.set_decoder ( op1b = 0x2E ); + + P_SS.set_asm ( "SS OVERRIDE PREFIX" ); + P_SS.set_decoder ( op1b = 0x36 ); + + P_DS.set_asm ( "DS OVERRIDE PREFIX" ); + P_DS.set_decoder ( op1b = 0x3E ); + + P_ES.set_asm ( "ES OVERRIDE PREFIX" ); + P_ES.set_decoder ( op1b = 0x26 ); + + P_FS.set_asm ( "FS OVERRIDE PREFIX" ); + P_FS.set_decoder ( op1b = 0x64 ); + + P_GS.set_asm ( "GS OVERRIDE PREFIX" ); + P_GS.set_decoder ( op1b = 0x65 ); + + P_BTAKEN.set_asm ( "BRANCH TAKEN PREFIX" ); + P_BTAKEN.set_decoder ( op1b = 0x3E ); + + P_BNTAKEN.set_asm ( "BRANCH NOT TAKEN PREFIX" ); + P_BNTAKEN.set_decoder ( op1b = 0x2E ); + + P_OPSIZE.set_asm ( "OPERAND SIZE OVERRIDE PREFIX" ); + P_OPSIZE.set_decoder ( op1b = 0x66 ); + + P_ADSIZE.set_asm ( "ADDRESS SIZE OVERRIDE PREFIX" ); + P_ADSIZE.set_decoder ( op1b = 0x67 ); + + mov_rm8_imm8.set_asm ( "MOV RM8, IMM8" ); + mov_rm8_imm8.set_decoder ( op1b = 0xC6 ); + + mov_r8_rm8.set_asm ( "MOVB R8, RM8" ); + mov_r8_rm8.set_decoder ( op1b = 0x8A ); + + mov_rm8_r8.set_asm ( "MOVB RM8, R8" ); + mov_rm8_r8.set_decoder ( op1b = 0x88 ); + + mov_AL_imm8.set_asm ( "MOVB AL, IMM8" ); + mov_AL_imm8.set_decoder ( op1b = 0xB0 ); + + mov_CL_imm8.set_asm ( "MOVB CL, IMM8" ); + mov_CL_imm8.set_decoder ( op1b = 0xB1 ); + + mov_DL_imm8.set_asm ( "MOVB DL, IMM8" ); + mov_DL_imm8.set_decoder ( op1b = 0xB2 ); + + mov_BL_imm8.set_asm ( "MOVB BL, IMM8" ); + mov_BL_imm8.set_decoder ( op1b = 0xB3 ); + + mov_AH_imm8.set_asm ( "MOVB AH, IMM8" ); + mov_AH_imm8.set_decoder ( op1b = 0xB4 ); + + mov_CH_imm8.set_asm ( "MOVB CH, IMM8" ); + mov_CH_imm8.set_decoder ( op1b = 0xB5 ); + + mov_DH_imm8.set_asm ( "MOVB DH, IMM8" ); + mov_DH_imm8.set_decoder ( op1b = 0xB6 ); + + mov_BH_imm8.set_asm ( "MOVB BH, IMM8" ); + mov_BH_imm8.set_decoder ( op1b = 0xB7 ); + + add_r8_rm8.set_asm ( "ADDB R8, RM8" ); + add_r8_rm8.set_decoder ( op1b = 0x02 ); + + add_rm8_imm8.set_asm ( "ADDB RM8, IMM8" ); + add_rm8_imm8.set_decoder ( op1b = 0x80, regop = 0x0 ); + + add_rm8_r8.set_asm ( "ADDB RM8, R8" ); + add_rm8_r8.set_decoder ( op1b = 0x00 ); + + inc_rm8.set_asm ( "INC RM8" ); + inc_rm8.set_decoder ( op1b = 0xFE, regop = 0x0 ); + + sub_rm8_r8.set_asm ( "SUB RM8, R8" ); + sub_rm8_r8.set_decoder ( op1b = 0x28 ); + + dec_rm8.set_asm ( "DEC RM8" ); + dec_rm8.set_decoder ( op1b = 0xFE, regop = 0x01 ); + + sub_rm8_imm8.set_asm ( "SUB RM8, IMM8" ); + sub_rm8_imm8.set_decoder ( op1b = 0x80, regop = 0x05 ); + + imul_rm8.set_asm ( "IMUL RM8" ); + imul_rm8.set_decoder ( op1b = 0xF6, regop = 0x05 ); + + mul_rm8.set_asm ( "MUL RM8" ); + mul_rm8.set_decoder ( op1b = 0xF6, regop = 0x04 ); + + sal_rm8.set_asm ( "SAL RM8" ); + sal_rm8.set_decoder ( op1b = 0xD0, regop = 0x04 ); + + sar_rm8.set_asm ( "SAR RM8" ); + sar_rm8.set_decoder ( op1b = 0xD0, regop = 0x07 ); + + sar_rm8_imm8.set_asm ( "SAR RM8, IMM8" ); + sar_rm8_imm8.set_decoder ( op1b = 0xC0, regop = 0x07 ); + + cmp_rm8_imm8.set_asm ( "CMP RM8, IMM8" ); + cmp_rm8_imm8.set_decoder ( op1b = 0x80, regop = 0x07 ); + + shr_rm8_imm8.set_asm ( "SHR RM8, IMM8" ); + shr_rm8_imm8.set_decoder ( op1b = 0xC0, regop = 0x05 ); + + div_rm8.set_asm ( "DIV RM8" ); + div_rm8.set_decoder ( op1b = 0xF6, regop = 0x06 ); + + shr_rm8.set_asm ( "SHR RM8" ); + shr_rm8.set_decoder ( op1b = 0xD0, regop = 0x05 ); + + cmp_AL_imm8.set_asm ( "CMP AL, IMM8" ); + cmp_AL_imm8.set_decoder ( op1b = 0x3C ); + + and_r8_rm8.set_asm ( "AND R8, RM8" ); + and_r8_rm8.set_decoder ( op1b = 0x22 ); + + or_r8_rm8.set_asm ( "OR R8, RM8" ); + or_r8_rm8.set_decoder ( op1b = 0x0A ); + + xor_r8_rm8.set_asm ( "XOR R8, RM8" ); + xor_r8_rm8.set_decoder ( op1b = 0x32 ); + + sal_rm8_imm8.set_asm ( "SAL RM8, IMM8" ); + sal_rm8_imm8.set_decoder ( op1b = 0xC0, regop = 0x04 ); + + jmp_rel8.set_asm ( "JMP REL8" ); + jmp_rel8.set_decoder ( op1b = 0xEB ); + + cmp_r8_rm8.set_asm ( "CMP R8, RM8" ); + cmp_r8_rm8.set_decoder ( op1b = 0x3A ); + + push_imm8.set_asm ( "PUSH IMM8" ); + push_imm8.set_decoder ( op1b = 0x6A ); + + }; +}; + diff --git a/pdl/x86/IA32_isa.cpp b/pdl/x86/IA32_isa.cpp new file mode 100644 index 0000000..d1ba02a --- /dev/null +++ b/pdl/x86/IA32_isa.cpp @@ -0,0 +1,5843 @@ +/** + * @file IA32-isa.cpp + * @author Rodolfo Jardim de Azevedo + * Valdiney Alves Pimenta (ArchC 2.0 port, new instructions, some fixed bugs) + * Team 03 - MC723 - 2005, 1st period + * Eduardo Uemura Okada + * Andre Deiano Pansani + * Ricardo Andrade + * Modified by Rafael Madeira + * readRegister8(); + * writeRegister8(); + * void ac_behavior( Type_op1bi ) + * DataManager + * + * The ArchC Team + * http://www.archc.org/ + * + * Computer Systems Laboratory (LSC) + * IC-UNICAMP + * http://www.lsc.ic.unicamp.br + * + * @version 1.0 + * @date Mon, 19 Jun 2006 15:33:29 -0300 + * + * @brief The ArchC x86 functional model. + * + * @attention Copyright (C) 2002-2006 --- The ArchC Team + * + */ + +#include "IA32_isa.H" +#include "IA32_isa_init.cpp" +#include "IA32_bhv_macros.H" +#include + +// Register definitions to register bank GR:8 +#define EAX 0 +#define ECX 1 +#define EDX 2 +#define EBX 3 +#define ESP 4 +#define EBP 5 +#define ESI 6 +#define EDI 7 +#define AX 0 +#define CX 1 +#define DX 2 +#define BX 3 +#define SP 4 +#define BP 5 +#define SI 6 +#define DI 7 +#define AL 0 +#define CL 1 +#define DL 2 +#define BL 3 +#define AH 4 +#define CH 5 +#define DH 6 +#define BH 7 +#define STACK_BOTTOM 0x01000000 +// Register definitions to register bank SR:6 +#define CS 0 +#define DS 1 +#define SS 2 +#define ES 3 +#define FS 4 +#define GS 5 +// Register definitions to register bank SPR:2 +#define EFLAGS 0 +#define EIP 1 +#define FLAG_CF (1) +#define FLAG_RESERVED_1 (1<<1) +#define FLAG_PF (1<<2) +#define FLAG_AF (1<<4) +#define FLAG_ZF (1<<6) +#define FLAG_SF (1<<7) +#define FLAG_TF (1<<8) +#define FLAG_IF (1<<9) +#define FLAG_DF (1<<10) +#define FLAG_OF (1<<11) +#define FLAG_IOPL (1<<12 | 1<<13) +#define FLAG_NT (1<<14) +#define FLAG_RF (1<<16) +#define FLAG_VM (1<<17) +#define FLAG_AC (1<<18) +#define FLAG_VIF (1<<19) +#define FLAG_VIP (1<<20) +#define FLAG_ID (1<<21) +#define FLAG_ALL 0xFFFFFFFF + +// Auxiliar Flags +#define JUST_SET 0 +#define RUNONCE 1 +#define NOT_SET 2 +#define OPER_ADD 0 +#define OPER_SUB 1 +#define OPER_MUL 2 +#define OPER_NONE 4 +#define MAXINT 0xFFFFFFFF +#define MASK_8BITS 0xFF +#define MASK_16BITS 0xFFFF +#define OPERAND_SIZE16JUST 0 +#define OPERAND_SIZE16 1 +#define OPERAND_SIZE32 2 +#define ADDRESS_SIZE16JUST 0 +#define ADDRESS_SIZE16 1 +#define ADDRESS_SIZE32 2 +#define INVALID_REGISTER 0xFFFFFFFF + + +// Output operation flags +#define VERBOSE 1 +#define GENERICVERBOSE 0 +#define OUTSTREAM stderr + +using namespace IA32_parms; + +// Auxiliar functions and data structures + +static char *reg_str[8] = {"EAX","ECX","EDX","EBX","ESP","EBP","ESI","EDI"}; +static char *reg_str16[8] = {"AX","CX","DX","BX","SP","BP","SI","DI"}; +typedef unsigned long long uint64; +int OperandSize; +int AddressSize; + +// ---------------------------------------------------------------------------- +// Auxiliar output functions -------------------------------------------------- +// ---------------------------------------------------------------------------- + +// Used to print instructions in generic format (ex."mov rm32, r32") +void acprintfg ( char *s ) +{ + + if (GENERICVERBOSE && !VERBOSE) fprintf(OUTSTREAM, "%s\n", s); + else if (GENERICVERBOSE && VERBOSE) fprintf(OUTSTREAM, "%s\t\t", s); +} + +// Used to print information +void acprintf ( char *s ) +{ + if (VERBOSE) fprintf(OUTSTREAM, s); +} + +// Used to print immediate data +void acprinti ( uint d ) +{ + if (VERBOSE) fprintf(OUTSTREAM, "0x%08X", d); +} + +void acprintfrr ( char *inst, uint reg1, uint reg2 ) +{ + if (VERBOSE && (OperandSize==OPERAND_SIZE16)) + fprintf(OUTSTREAM, "%s %s, %s\n", inst, reg_str16[reg1], reg_str16[reg2] ); + else if (VERBOSE && (OperandSize==OPERAND_SIZE32)) + fprintf(OUTSTREAM, "%s %s, %s\n", inst, reg_str[reg1], reg_str[reg2] ); +} + +void acprintfmr ( char *inst, uint a, uint reg ) +{ + if (VERBOSE && (OperandSize==OPERAND_SIZE16)) + fprintf(OUTSTREAM, "%s [0x%08X], %s\n", inst, a, reg_str16[reg] ); + else if (VERBOSE && (OperandSize==OPERAND_SIZE32)) + fprintf(OUTSTREAM, "%s [0x%08X], %s\n", inst, a, reg_str[reg] ); +} + +void acprintfrm ( char *inst, uint reg, uint a ) +{ + if (VERBOSE && (OperandSize==OPERAND_SIZE16)) + fprintf(OUTSTREAM, "%s %s, [0x%08X]\n", inst, reg_str16[reg], a ); + else if (VERBOSE && (OperandSize==OPERAND_SIZE32)) + fprintf(OUTSTREAM, "%s %s, [0x%08X]\n", inst, reg_str[reg], a ); +} + +void acprintfi16 ( char *inst, ushort i ) +{ + if (VERBOSE) fprintf(OUTSTREAM, "%s 0x%04X\n", inst, i); +} + +void acprintfi32 ( char *inst, uint i ) +{ + if (VERBOSE) fprintf(OUTSTREAM, "%s 0x%08X\n", inst, i); +} + +void acprintfri16 ( char *inst, uint reg, ushort i ) +{ + + if (VERBOSE) fprintf(OUTSTREAM, "%s %s, 0x%04X\n", inst, reg_str16[reg], i); +} + +void acprintfri32 ( char *inst, uint reg, uint i ) +{ + if (VERBOSE) fprintf(OUTSTREAM, "%s %s, 0x%08X\n", inst, reg_str[reg], i ); +} + +void acprintfri ( char *inst, uint reg, uint i ) +{ + if (VERBOSE) fprintf(OUTSTREAM, "%s %s, 0x%08X\n", inst, reg_str[reg], i); +} + +void acprintfmi ( char *inst, uint a, uint i ) +{ + if (VERBOSE) fprintf(OUTSTREAM, "%s [0x%08X], 0x%08X\n", inst, a, i ); +} + +void acprintfr16m1616 ( char *inst, uint reg, uint sel, uint offset ) +{ + if (VERBOSE) + fprintf(OUTSTREAM, "%s %s, 0x%04X:0x%04x\n",inst,reg_str16[reg],sel,offset); +} + +void acprintfr32m1632 ( char *inst, uint reg, uint sel, uint offset ) +{ + if (VERBOSE) + fprintf(OUTSTREAM, "%s %s, 0x%04X:0x%08X\n", inst, reg_str[reg], sel, offset); +} + +void acprintfr16m ( char *inst, uint reg, uint a ) +{ + if (VERBOSE) fprintf(OUTSTREAM, "%s %s, 0x%08X\n", inst, reg_str16[reg], a); +} + +void acprintfr32m ( char *inst, uint reg, uint a ) +{ + if (VERBOSE) fprintf(OUTSTREAM, "%s %s, 0x%08X\n", inst, reg_str[reg], a); +} + +// ---------------------------------------------------------------------------- +// Auxiliar shift operations -------------------------------------------------- +// ---------------------------------------------------------------------------- + +bool shiftLeft ( signed int *dest, signed char count ) +{ + bool ret_val=false; + if ( count > 0 ) + { + (*dest) = (*dest) << count - 1; + if ( (*dest) & (1<<31) ) ret_val = true; + (*dest) = (*dest) << 1; + } + else if ( count < 0 ) + { + (*dest) = (*dest) << count + 1; + if ( (*dest) & (1) ) ret_val = true; + (*dest) = (*dest) >> 1; + } + return ret_val; +} + +bool shiftRight ( signed int *dest, unsigned char count ) +{ + return shiftLeft(dest, ((~count)+0x01)); +} + +// ---------------------------------------------------------------------------- +// Bit operations ------------------------------------------------------------- +// ---------------------------------------------------------------------------- + +bool MSB32 ( uint b ) +{ + return (b&(1<<31)); +} + +bool MSB16 ( uint b ) +{ + return (b&(1<<15)); +} + +bool MSB8 ( uint b ) +{ + return (b&(1<<7)); +} + +bool LSB ( uint b ) +{ + return (b&(0x01)); +} + +bool testBit ( uint array, long index ) +{ + long realIndex = index%32; + uint mask = (uint)(1< &MEM, uint address, long index ) +{ + uint realAddress = (uint)(address + (index/8)); + long realIndex = index%8; + if ( realIndex < 0x00 ) realIndex = -realIndex; + uint mask = (uint)(1< &MEM, uint address, long index ) +{ + uint realAddress = (uint)(address + (index/8)); + long realIndex = index%8; + if ( realIndex < 0x00 ) realIndex = -realIndex; + uint mask = (uint)(1< &MEM, uint address, long index ) +{ + uint realAddress = (uint)(address + (index/8)); + long realIndex = index%8; + if ( realIndex < 0x00 ) realIndex = -realIndex; + uint mask = (~((uint)(1< &MEM, uint address, long index ) +{ + if ( testMemBit(MEM, address,index) ) resetMemBit(MEM, address,index ); + else setMemBit(MEM, address, index ); +} + +// ---------------------------------------------------------------------------- +// Stack functions ------------------------------------------------------------ +// ---------------------------------------------------------------------------- +void push (ac_memport &MEM, ac_regbank<8, ac_word, ac_Dword> & GR, uint d ) +{ + uint temp; + if ( OperandSize == OPERAND_SIZE16 ) + { + temp = GR.read(ESP) - 2; + GR.write(ESP,temp); + MEM.write_half(temp, (unsigned short)d); + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + temp = GR.read(ESP) - 4; + GR.write(ESP,temp); + MEM.write(temp, d); + } +} + +uint pop(ac_memport &MEM, ac_regbank<8, ac_word, ac_Dword> & GR) +{ + signed short r16; + signed int aux; + uint temp, ret; + temp = GR.read(ESP); + if ( OperandSize == OPERAND_SIZE16 ) + { + r16 = MEM.read_half(temp); + GR.write(ESP, temp+2); + aux = r16; + ret = aux; + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + if ( temp == STACK_BOTTOM ) + { + fprintf ( stderr, "Stack is empty!\n" ); + return 0; + } + ret = MEM.read(temp); + GR.write(ESP,temp+4); + if ((GR.read(ESP) == STACK_BOTTOM) && (ret == 0xCC00)) + { + fprintf(stderr,"ArchC: Simulation terminated, found end of program. (Need to be fixed. ac_stop doesn't work in this version!)\n"); + //stop(0); + //fprintf ( stderr, "\n" ); + //PrintStat(); + //fprintf ( stderr, "\n" ); + exit(1); + } + } + return ret; +} + +// ---------------------------------------------------------------------------- +// Flag behavior functions ---------------------------------------------------- +// ---------------------------------------------------------------------------- +void setFlag (ac_regbank<2, ac_word, ac_Dword>& SPR, uint flagId ) +{ + uint temp = SPR.read(EFLAGS)|flagId; + SPR.write(EFLAGS,temp); +} + +void resetFlag (ac_regbank<2, ac_word, ac_Dword>& SPR, uint flagId ) +{ + uint temp = SPR.read(EFLAGS)&(~flagId); + SPR.write(EFLAGS,temp); +} + +void writeFlag (ac_regbank<2, ac_word, ac_Dword>& SPR, uint flagId, bool val ) +{ + if ( val ) setFlag(SPR, flagId); + else resetFlag(SPR, flagId); +} + +void compFlag (ac_regbank<2, ac_word, ac_Dword>& SPR, uint flagId ) +{ + uint temp = SPR.read(EFLAGS); + if (temp&flagId) resetFlag(SPR, flagId); + else setFlag(SPR, flagId); +} + +bool testFlag (ac_regbank<2, ac_word, ac_Dword>& SPR, uint flagId ) +{ + uint temp = SPR.read(EFLAGS); + if ( temp & flagId ) return true; + return false; +} + + +bool checkParity ( uint res ) +{ + unsigned char aux = (unsigned char)res; + uint parity = 0; + for ( int i=0; i<8; i++ ) + if ( aux&(1< 0xFFFFFFFF ) + return true; + return false; + break; + case OPER_SUB: + if ( op1 < op2 ) return true; + return false; + break; + }; + return false; +} + +bool checkCarry16 ( uint oper, uint op1, uint op2, uint res ) +{ + unsigned short lop1 = op1; + unsigned short lop2 = op2; + unsigned long aux = lop1+lop2; + switch ( oper ) + { + case OPER_MUL: + if (res) return true; + break; + case OPER_ADD: + if ( aux > 0xFFFF ) + return true; + return false; + break; + case OPER_SUB: + if ( op1 < op2 ) return true; + return false; + break; + }; + return false; +} + +bool checkCarry8 ( uint oper, uint op1, uint op2, uint res ) +{ + unsigned char lop1 = op1; + unsigned char lop2 = op2; + unsigned int aux = lop1+lop2; + switch ( oper ) + { + case OPER_MUL: + if (res) return true; + break; + case OPER_ADD: + if ( aux > 0xFF ) + return true; + return false; + break; + case OPER_SUB: + if ( op1 < op2 ) return true; + return false; + break; + }; + return false; +} + +bool checkAdjust ( uint oper, uint op1, uint op2, uint res ) +{ + switch ( oper ) + { + case OPER_ADD: + if ( (op1&(1<<4)) && (op2&(1<<4)) && !(res&(1<<4)) ) return true; + if ( !(op1&(1<<4)) && !(op2&(1<<4)) && (res&(1<<4)) ) return true; + return false; + break; + case OPER_SUB: + op2 = (~op2) + 1; + if ( (op1&(1<<4)) && (op2&(1<<4)) && !(res&(1<<4)) ) return true; + if ( !(op1&(1<<4)) && !(op2&(1<<4)) && (res&(1<<4)) ) return true; + return false; + break; + }; + return false; +} + +bool checkOverflow ( uint oper, uint op1, uint op2, uint res ) +{ + signed int sop1 = op1; + signed int sop2 = op2; + signed int sres = res; + switch ( oper ) + { + case OPER_ADD: + if ( (sop1<0) && (sop2<0) && (sres>0) ) return true; + if ( (sop1>0) && (sop2>0) && (sres<0) ) return true; + return false; + break; + case OPER_SUB: + sop2 = -sop2; + if ( (sop1<0) && (sop2<0) && (sres>0) ) return true; + if ( (sop1>0) && (sop2>0) && (sres<0) ) return true; + return false; + break; + case OPER_MUL: + if ( res != 0 ) return true; + return false; + break; + } + return false; +} + +bool checkOverflow16 ( uint oper, uint op1, uint op2, uint res ) +{ + signed short sop1 = op1; + signed short sop2 = op2; + signed short sres = res; + switch ( oper ) + { + case OPER_ADD: + if ( (sop1<0) && (sop2<0) && (sres>0) ) return true; + if ( (sop1>0) && (sop2>0) && (sres<0) ) return true; + return false; + break; + case OPER_SUB: + sop2 = -sop2; + if ( (sop1<0) && (sop2<0) && (sres>0) ) return true; + if ( (sop1>0) && (sop2>0) && (sres<0) ) return true; + return false; + break; + case OPER_MUL: + if ( res != 0 ) return true; + return false; + break; + } + return false; +} + +bool checkOverflow8 ( uint oper, uint op1, uint op2, uint res ) +{ + signed char sop1 = op1; + signed char sop2 = op2; + signed char sres = res; + switch ( oper ) + { + case OPER_ADD: + if ( (sop1<0) && (sop2<0) && (sres>0) ) return true; + if ( (sop1>0) && (sop2>0) && (sres<0) ) return true; + return false; + break; + case OPER_SUB: + int inv_sop2 = -sop2; + if ( (sop1<0) && (inv_sop2<0) && (sres>0) ) return true; + if ( (sop1>0) && (inv_sop2>0) && (sres<0) ) return true; + return false; + break; + case OPER_MUL: + if ( res != 0 ) return true; + return false; + break; + } + return false; +} + +void checkFlags8 (ac_regbank<2, ac_word, ac_Dword>& SPR, uint oper, uint op1, uint op2, uint res, uint flags ) +{ + if ( flags&FLAG_CF ) writeFlag(SPR, FLAG_CF, checkCarry8(oper,op1,op2,res)); + if ( flags&FLAG_PF ) writeFlag(SPR, FLAG_PF, checkParity(res)); + if ( flags&FLAG_AF ) writeFlag(SPR, FLAG_AF, checkAdjust(oper,op1,op2,res)); + if ( flags&FLAG_ZF ) writeFlag(SPR, FLAG_ZF, !res); + if ( flags&FLAG_SF ) writeFlag(SPR, FLAG_SF, MSB8(res)); + if ( flags&FLAG_OF ) writeFlag(SPR, FLAG_OF, checkOverflow8(oper,op1,op2,res)); +} + +void checkFlags (ac_regbank<2, ac_word, ac_Dword>& SPR, uint oper, uint op1, uint op2, uint res, uint flags ) +{ + if ( flags&FLAG_CF ) + { + if ( OperandSize == OPERAND_SIZE16 ) + writeFlag(SPR, FLAG_CF, checkCarry16(oper,op1,op2,res) ); + else if ( OperandSize == OPERAND_SIZE32 ) + writeFlag(SPR, FLAG_CF, checkCarry(oper,op1,op2,res) ); + } + if ( flags&FLAG_PF ) writeFlag(SPR, FLAG_PF, checkParity(res)); + if ( flags&FLAG_AF ) writeFlag(SPR, FLAG_AF, checkAdjust(oper,op1,op2,res) ); + if ( flags&FLAG_ZF ) writeFlag(SPR, FLAG_ZF, !res); + if ( flags&FLAG_SF ) + { + if ( OperandSize == OPERAND_SIZE16 ) + writeFlag(SPR, FLAG_SF, MSB16(res)); + else if ( OperandSize == OPERAND_SIZE32 ) + writeFlag(SPR, FLAG_SF, MSB32(res)); + } + if ( flags&FLAG_OF ) + { + if ( OperandSize == OPERAND_SIZE16 ) + writeFlag(SPR, FLAG_OF, checkOverflow16(oper,op1,op2,res)); + else if ( OperandSize == OPERAND_SIZE32 ) + writeFlag(SPR, FLAG_OF, checkOverflow(oper,op1,op2,res)); + } +} + + +//----------------------------------- +//Flags -- Auxiliar Functions -- Begin +//---------------------------------- + + +void setFlags_af(ac_regbank<2, ac_word, ac_Dword>& SPR, uint flag,uint reg){ + +/***** +Function to set 'flag' according to the +resulting binary value in the 'reg' register +*****/ + + if ( flag&FLAG_SF ) + if ( reg >= 0 ) resetFlag(SPR, FLAG_CF ); + else setFlag(SPR, FLAG_CF ); + if ( flag&FLAG_ZF ) + if ( reg == 0 ) setFlag(SPR, FLAG_ZF ); + else resetFlag(SPR, FLAG_ZF ); + if ( flag&FLAG_PF ) + writeFlag(SPR, FLAG_PF,checkParity( reg )); +}//setFlag + +//----------------------------------- +//Flags -- Auxiliar Functions -- End +//---------------------------------- +// ---------------------------------------------------------------------------- +// Generic processed data to instructions abstraction ------------------------- +// ---------------------------------------------------------------------------- + +uint readMemory(ac_memport &MEM, uint a) +{ + signed int aux; + signed short aux16; + if ( OperandSize == OPERAND_SIZE16 ) + { + aux16 = (MEM.read_half(a) & MASK_16BITS); + aux = aux16; + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + aux = MEM.read(a); + } + return aux; +} + +uint readMemory16(ac_memport &MEM, uint a) +{ + signed int aux; + signed short aux16; + aux16 = (MEM.read_half(a) & MASK_16BITS); + aux = aux16; + return aux; +} + +uint readMemory8(ac_memport &MEM, uint a) +{ + signed char aux8; + signed int aux; + aux8 = (MEM.read(a) & MASK_8BITS); + aux = aux8; + return aux; +} + +void writeMemory(ac_memport &MEM, uint a, uint val) +{ + unsigned short aux16 = (val & MASK_16BITS); + if ( OperandSize == OPERAND_SIZE16 ) + MEM.write_half(a, aux16); + else if ( OperandSize == OPERAND_SIZE32 ) + MEM.write(a, val); +} + +void writeMemory8(ac_memport &MEM, uint a, uint val) +{ + MEM.write_byte(a, (val & MASK_8BITS)); +} + +uint readSPRegister(ac_regbank<2, ac_word, ac_Dword>& SPR, uint reg) +{ + return (SPR.read(reg)); +} + +void writeSPRegister(ac_regbank<2, ac_word, ac_Dword>& SPR, uint reg, uint val) +{ + if ( OperandSize == OPERAND_SIZE16 ) + SPR.write(reg, (SPR.read(reg)&0xFFFF0000)|(val&MASK_16BITS)); + else if ( OperandSize == OPERAND_SIZE32 ) + SPR.write(reg, val); +} + +uint readSRegister(ac_regbank<6, ac_word, ac_Dword>& SR, uint reg) +{ + return (SR.read(reg) & MASK_16BITS); +} + +void writeSRegister(ac_regbank<6, ac_word, ac_Dword>& SR, uint reg, uint val) +{ + SR.write(reg, (val & MASK_16BITS)); +} + +uint readRegister8(ac_regbank<8, ac_word, ac_Dword> & GR, uint reg) +{ + signed char aux8; + signed int aux; + switch(reg) + { + // 8bit access to registers + case AL: case CL: case DL: case BL: + aux8 = (GR.read(reg) & MASK_8BITS); + aux = aux8; + return aux; + break; + + case AH: + reg = 0;// ler de EAX + aux8 = ((GR.read(reg)>>8) & MASK_8BITS); + aux = aux8; + return aux; + break; + case CH: + reg = 1;// ler de ECX + aux8 = ((GR.read(reg)>>8) & MASK_8BITS); + aux = aux8; + return aux; + break; + case DH: + reg = 2;// ler de EDX + aux8 = ((GR.read(reg)>>8) & MASK_8BITS); + aux = aux8; + return aux; + break; + + case BH: + reg = 3;// ler de EDX + aux8 = ((GR.read(reg)>>8) & MASK_8BITS); + aux = aux8; + return aux; + break; + }; + return INVALID_REGISTER; +} + +uint readRegister(ac_regbank<8, ac_word, ac_Dword> & GR, uint reg) +{ + signed int aux; + signed short aux16; + if ( OperandSize == OPERAND_SIZE16 ) + { + switch(reg) + { + // 16bit access to registers + case AX: case CX: case DX: case BX: + case SP: case BP: case SI: case DI: + aux16 = (GR.read(reg) & MASK_16BITS); + aux = aux16; + return aux; + break; + }; + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + switch(reg) + { + // 32bit access to registers + case EAX: case ECX: case EDX: case EBX: + case ESP: case EBP: case ESI: case EDI: + return GR.read(reg); + break; + }; + } + return INVALID_REGISTER; +} + +void writeRegister8(ac_regbank<8, ac_word, ac_Dword> & GR, uint reg, uint val) +{ + + + switch(reg) + { + // 8bit access to registers + case AL: case CL: case DL: case BL: + GR.write(reg, ((GR.read(reg) & 0xFFFFFF00) | (val & MASK_8BITS))); + break; + + case AH: + reg = 0; //AH sera escrito em EAX + GR.write(reg, ( (GR.read(reg) & 0xFFFF00FF) | ((val & MASK_8BITS)<<8) )); + break; + case CH: + reg = 1; //CH sera escrito em ECX + GR.write(reg, ( (GR.read(reg) & 0xFFFF00FF) | ((val & MASK_8BITS)<<8) )); + break; + case DH: + reg = 2; //DH sera escrito em EDX + GR.write(reg, ( (GR.read(reg) & 0xFFFF00FF) | ((val & MASK_8BITS)<<8) )); + break; + case BH: + reg = 3; //BH sera escrito em EBX + GR.write(reg, ( (GR.read(reg) & 0xFFFF00FF) | ((val & MASK_8BITS)<<8) )); + break; + } +} + +void writeRegister(ac_regbank<8, ac_word, ac_Dword> & GR, uint reg, uint val) +{ + if ( OperandSize == OPERAND_SIZE16 ) + { + printf("REG 16bits: %i\n",reg); + switch(reg) + { + + // 16bit access to registers + case AX: case CX: case DX: case BX: + case BP: case SP: case SI: case DI: + GR.write(reg, ((GR.read(reg) & 0xFFFF0000) | (val & MASK_16BITS))); + break; + }; + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + printf("REG 32bits: %i\n",reg); + switch(reg) + { + // 32bit access to registers + case EAX: case ECX: case EDX: case EBX: + case EBP: case ESP: case ESI: case EDI: + GR.write(reg,val); + break; + }; + } +} + +class Data +{ +private: + uint Register1; + uint Register2; + uint Address; + unsigned char Address8; + signed int Immediate; + signed int Immediate8; + signed int Immediate16; + bool UsesMemory; +public: + Data(){}; + ~Data(){}; + bool usesMemory() {return UsesMemory;}; + void usesMemory(bool aux) {UsesMemory=aux;}; + uint reg1() {return Register1;}; + void reg1(uint r) {Register1=r;}; + uint reg2() {return Register2;}; + void reg2(uint r) {Register2=r;}; + uint address() {return Address;}; + void address(uint a) {Address=a;}; + unsigned char address8() {return Address8;}; + void address8(unsigned char a) {Address8=a;}; + uint immediate(ac_regbank<2, ac_word, ac_Dword>& SPR, ac_reg& ac_pc) { + // ac_pc+=4; SPR.write(EIP,(int)ac_pc); + if ( OperandSize == OPERAND_SIZE16){ + ac_pc+=2; SPR.write(EIP,(int)ac_pc); + acprintf("Size 16\n"); + } + else if (OperandSize == OPERAND_SIZE32){ + ac_pc+=4; SPR.write(EIP,(int)ac_pc); + acprintf("Size 32\n"); + } + return Immediate; + }; + void immediate(signed int i) {Immediate=i;}; + uint immediate8(ac_regbank<2, ac_word, ac_Dword>& SPR, ac_reg& ac_pc) {ac_pc+=1; SPR.write(EIP,(int)ac_pc); return Immediate8;}; + void immediate8(signed char i) {Immediate8=i;}; + uint immediate16(ac_regbank<2, ac_word, ac_Dword>& SPR, ac_reg& ac_pc) {ac_pc+=2; SPR.write(EIP,(int)ac_pc);return Immediate16;}; + void immediate16(signed char i) {Immediate16=i;}; + void immediates(signed int i) { immediate(i); immediate16(i); immediate8(i);}; + uint acpc_inc; +}; + + + +Data data; +int IFJustSet; + +class DataManager +{ +public: + DataManager(){}; + ~DataManager(){}; + + uint getMemOrReg1(ac_memport &MEM, ac_regbank<8, ac_word, ac_Dword> & GR) + { + if ( data.usesMemory() ) return readMemory(MEM, data.address()); + return readRegister(GR, data.reg1()); + } + + uint getMemOrReg2(ac_memport &MEM, ac_regbank<8, ac_word, ac_Dword> & GR) + { + if ( data.usesMemory() ) return readMemory(MEM, data.address()); + return readRegister(GR, data.reg2()); + } + + uint getReg1(ac_regbank<8, ac_word, ac_Dword> & GR) { return readRegister(GR, data.reg1()); }; + + uint getReg2(ac_regbank<8, ac_word, ac_Dword> & GR) { return readRegister(GR, data.reg2()); }; + + uint getImmediate(ac_regbank<2, ac_word, ac_Dword>& SPR, ac_reg& ac_pc) + { + // if ( OperandSize == OPERAND_SIZE16 ) return data.immediate16(SPR, ac_pc); + if ( OperandSize == OPERAND_SIZE16 ) return data.immediate(SPR, ac_pc); + else if ( OperandSize == OPERAND_SIZE32 ) return data.immediate(SPR, ac_pc); + return data.immediate(SPR, ac_pc); + } + + void setMemOrReg1(ac_memport &MEM, ac_regbank<8, ac_word, ac_Dword> & GR, uint val) + { + if ( data.usesMemory() ) writeMemory(MEM, data.address(),val); + else writeRegister(GR, data.reg1(),val); + } + + void setMemOrReg2(ac_memport &MEM, ac_regbank<8, ac_word, ac_Dword> & GR, uint val) + { + if ( data.usesMemory() ) writeMemory(MEM, data.address(),val); + else writeRegister(GR, data.reg2(),val); + } + + void setMem(ac_memport &MEM, uint val) { writeMemory(MEM, data.address(),val);} + + void setReg1(ac_regbank<8, ac_word, ac_Dword> & GR, uint val) { writeRegister(GR, data.reg1(),val); } + + void setReg2(ac_regbank<8, ac_word, ac_Dword> & GR, uint val) { writeRegister(GR, data.reg2(),val); } +}; + +DataManager dataManager; + +class PrintManager +{ +public: + PrintManager(){}; + ~PrintManager(){}; + + // Instructions such as: INST REG1, ADDR + void printReg1Addr ( char *g16, char *g32, char *i16, char *i32 ) + { + if ( OperandSize == OPERAND_SIZE16 ) + { + acprintfg(g16); + acprintfr16m ( i16, data.reg1(), data.address() ); + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + acprintfg(g32); + acprintfr32m ( i32, data.reg1(), data.address() ); + } + } + + // Instructions such as: INST REG1, SEL:OFFSET + void printReg1Addr ( char *g16, char *g32, char *i16, char *i32, uint s, uint o) + { + if ( OperandSize == OPERAND_SIZE16 ) + { + acprintfg(g16); + acprintfr16m1616 ( i16, data.reg1(), s, o ); + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + acprintfg(g32); + acprintfr32m1632 ( i32, data.reg1(), s, o ); + } + } + + // Instructions such as: INST REG2, MEM/REG1 + void printReg2MReg1(char *g16, char *g32, char *i16, char *i32) + { + if ( OperandSize == OPERAND_SIZE16 ) + { + acprintfg(g16); + if ( data.usesMemory() ) acprintfmr(i16,data.address(),data.reg1()); + else acprintfrr(i16,data.reg2(),data.reg1()); + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + acprintfg(g32); + if ( data.usesMemory() ) acprintfmr(i32,data.address(),data.reg1()); + else acprintfrr(i32,data.reg2(),data.reg1()); + } + } + + void printReg1MReg2(char *g16, char *g32, char *i16, char *i32) + { + if ( OperandSize == OPERAND_SIZE16 ) + { + acprintfg(g16); + if ( data.usesMemory()) acprintfrm(i16,data.reg1(),data.address()); + else acprintfrr(i16,data.reg1(),data.reg2()); + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + acprintfg(g32); + if ( data.usesMemory()) acprintfrm(i32,data.reg1(),data.address()); + else acprintfrr(i32,data.reg1(),data.reg2()); + } + } + + // Instructions such as: INST FIXED, IMMEDIATE32 + void printImm(char *g16, char *g32, char *i16, char *i32, uint i) + { + if ( OperandSize == OPERAND_SIZE16 ) + { + acprintfg(g16); + acprintfi16(i16,i); + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + acprintfg(g32); + acprintfi32(i32,i); + } + } + + // Instructions such as: INST REG/MEM, IMM16/32 + void printReg2MImm(char *g16, char *g32, char *i16, char *i32, uint i ) + { + if ( OperandSize == OPERAND_SIZE16 ) + { + //printf("16 bits\n"); + acprintfg(g16); + acprintfri16(i16, data.reg2(), i); + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + acprintfg(g32); + acprintfri32(i32, data.reg2(), i); + } + } + + // Instructions that are independent from operand and address sizes + void print(char *inst) + { + acprintfg(inst); + acprintf(inst);acprintf("\n"); + } + + // Instructions with fix-argument type + void print(char *inst16, char *inst32) + { + if ( OperandSize == OPERAND_SIZE16 ) + { + acprintfg(inst16); + acprintf(inst16);acprintf("\n"); + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + acprintfg(inst32); + acprintf(inst32);acprintf("\n"); + } + } +}; + +PrintManager printManager; + +// ---------------------------------------------------------------------------- +// Addressing modes abstraction ----------------------------------------------- +// ---------------------------------------------------------------------------- + +signed int signExtend8 ( unsigned int i ) +{ + if ( MSB8(i) ) return (0xFFFFFF00)|(i&MASK_8BITS); + return i; +} + +uint processSib(ac_regbank<8, ac_word, ac_Dword> & GR, ac_reg& ac_pc, uint mod, uint sib, uint disp, uint imm, bool *used) +{ + uint ss = (sib>>6); + uint index = (sib>>3)&(0x07); + uint base = sib&0x07; + uint scaledIndex=0; + uint baseValue=0; + + // Calculating Scaled Index + if ( index == 0x04 ) scaledIndex = 0; + else scaledIndex = GR.read(index)*((uint)pow((double)2,(double)ss)); + + // Calculating Base + if ( (base == 0x05) && (mod == 0x00) ) + { + baseValue = disp; + data.acpc_inc+= 4; + ac_pc+= 4; + data.immediates(imm); + (*used)=true; + } + else + { + baseValue = GR.read(base); + } + + return baseValue + scaledIndex; +} + +void processData(ac_regbank<8, ac_word, ac_Dword> & GR, ac_reg& ac_pc, uint mod, uint regop, uint rm, uint sib, uint disp, uint imm) +{ + bool used = false; + uint disp8, disp32; + data.usesMemory(true); + data.reg1(regop); + data.acpc_inc = 0; + switch(mod) + { + case 0x00: + disp32 = (disp<<8)|(sib&MASK_8BITS); + switch(rm) + { + case 0x04: // SIB + data.address(processSib(GR, ac_pc, mod,sib,disp,imm,&used)); + data.acpc_inc+=2; + ac_pc+= 2; + if ( !used ) data.immediates(disp); + break; + case 0x05: // DISP32 + data.address(disp32); + data.acpc_inc+=5; + ac_pc+= 5; + data.immediates((disp>>24)+(imm<<8)); + break; + default: // [E**] + data.address(GR.read(rm)); + data.acpc_inc+=1; + ac_pc+= 1; + data.immediates(disp32); + break; + }; + break; + + case 0x01: + disp8 = signExtend8(disp&MASK_8BITS); + switch(rm) + { + case 0x04: // SIB+DISP8 + data.address(processSib(GR, ac_pc, mod,sib,disp,imm,&used) + (signed)disp8); + data.acpc_inc+=3; + ac_pc+= 3; + data.immediates((imm<<24)|((disp>>8)&MASK_8BITS)); + break; + default: // [E**]+DISP8 + data.address(GR.read(rm) + (signed)signExtend8(sib)); + data.acpc_inc+=2; + ac_pc+= 2; + data.immediates(disp); + break; + }; + break; + + case 0x02: + disp32 = disp; + switch(rm) + { + case 0x04: // SIB+DISP32 + data.address(processSib(GR, ac_pc, mod,sib,disp,imm,&used) + (signed)disp32); + data.acpc_inc+=6; + ac_pc+= 6; + data.immediates(imm); + break; + default: // [E**]+DISP32 + disp32 = (disp<<8)|(sib&MASK_8BITS); + data.address(GR.read(rm) + (signed)disp32); + data.acpc_inc+=5; + ac_pc+= 5; + data.immediates(((disp>>24)&MASK_8BITS)|(imm<<8)); + break; + }; + break; + + case 0x03: + data.usesMemory(false); + data.reg2(rm); + data.acpc_inc+=1; + ac_pc+=1; + data.immediates((sib&MASK_8BITS)|(disp<<8)); + break; + }; +} + + + + +//!Behavior executed before simulation begins. +void ac_behavior( begin ) +{ + // Segmented memory is not implemented... yet + SR.write(CS,0x00000000); // Code Segment + SR.write(DS,0x00000000); // Data Segment + SR.write(ES,0x00000000); + SR.write(SS,0x00000000); // Stack Segment + + // Setting Operand size attribute behavior + OperandSize = OPERAND_SIZE32; + + // Setting Address size attribute behavior + AddressSize = ADDRESS_SIZE32; + + // Setting Stack Pointer + GR.write(ESP,STACK_BOTTOM); + + // Setting IF behavior flag + IFJustSet = NOT_SET; + setFlag(SPR, FLAG_IF); + setFlag(SPR, FLAG_RESERVED_1); //always set according Intel DatSheet + + // Setting OS return control (end of program) + push(MEM, GR, 0xCC00); +}; + +//!Behavior executed after simulation ends. +void ac_behavior( end ){}; + +//!Generic instruction behavior method. +void ac_behavior( instruction ) +{ + // IF flag behavior implementation + if (IFJustSet == RUNONCE) + { + IFJustSet = NOT_SET; + setFlag(SPR, FLAG_IF); + } + if (IFJustSet == JUST_SET) IFJustSet = RUNONCE; + // OperandSize attribute behavior implementation + if (OperandSize == OPERAND_SIZE16 ) OperandSize = OPERAND_SIZE32; + if (OperandSize == OPERAND_SIZE16JUST ) OperandSize = OPERAND_SIZE16; + // AddressSize attribute behavior implementation + if (AddressSize == ADDRESS_SIZE16 ) AddressSize = ADDRESS_SIZE32; + if (AddressSize == ADDRESS_SIZE16JUST ) AddressSize = ADDRESS_SIZE16; +}; + +//! Instruction Format behavior methods. +void ac_behavior( Type_op1b ) +{ + ac_pc+= 1; + SPR.write(EIP,(int)ac_pc); +} +void ac_behavior( Type_op2b ) +{ + ac_pc+= 2; + SPR.write(EIP,(int)ac_pc); +} +void ac_behavior( Type_op1bi ) +{ + data.immediate(imme); + ac_pc+= 1; + SPR.write(EIP,(int)ac_pc); +} +void ac_behavior( Type_op1bi8 ) +{ + data.immediate8(imm8); + ac_pc+= 1; + SPR.write(EIP,(int)ac_pc); +} +void ac_behavior( Type_op1bd8 ) +{ + data.address8(disp8); + ac_pc+= 2; + SPR.write(EIP,(int)ac_pc); +} +void ac_behavior( Type_op1bd32 ) +{ + data.address(imme); + ac_pc+= 5; + SPR.write(EIP,(int)ac_pc); +} +void ac_behavior( Type_op2bd32 ) +{ + data.address(disp32); + ac_pc+= 6; + SPR.write(EIP,(int)ac_pc); +} +void ac_behavior( Type_op1b_rm32 ) +{ + processData(GR, ac_pc, mod,regop,rm,sib,disp,imm); + ac_pc+=1; + SPR.write(EIP,(int)ac_pc); +} +void ac_behavior( Type_op2b_rm32 ) +{ + processData(GR, ac_pc, mod2,regop2,rm2,sib2,disp2,imm2); + ac_pc+=2; + SPR.write(EIP,(int)ac_pc); +} +void ac_behavior( Type_op2b_debug ) +{ + if ( op2b==0xAAAA ) + ac_pc+= 10; + else if ( op2b==0xDD00 ) + ac_pc+= 2; + else if ( op2b==0xCC00 ) + ac_pc+= 2; + SPR.write(EIP,(int)ac_pc); +} + +//!Instruction insd behavior method. +void ac_behavior( insd ) +{ + printManager.print ( "INSD " ); + // Input/Output not available +} + +//!Instruction outsd behavior method. +void ac_behavior( outsd ) +{ + printManager.print ( "OUTSD " ); + // Input/Output not available +} + +// Debug ok +//!Instruction stc behavior method. +void ac_behavior( stc ) +{ + printManager.print ( "STC" ); + setFlag(SPR, FLAG_CF); +} + +// Debug ok +//!Instruction clc behavior method. +void ac_behavior( clc ) +{ + printManager.print ( "CLC" ); + resetFlag(SPR, FLAG_CF); +} + +// Debug ok +//!Instruction cmc behavior method. +void ac_behavior( cmc ) +{ + printManager.print ( "CMC" ); + compFlag(SPR, FLAG_CF); +} + +// Debug ok +//!Instruction cld behavior method. +void ac_behavior( cld ) +{ + printManager.print ( "CLD" ); + resetFlag(SPR, FLAG_DF); +} + +// Debug ok +//!Instruction std behavior method. +void ac_behavior( std ) +{ + printManager.print ( "STD" ); + setFlag(SPR, FLAG_DF); +} + +//!Instruction lahf behavior method. +void ac_behavior( lahf ) +{ + printManager.print ( "LAHF " ); +} + +//!Instruction sahf behavior method. +void ac_behavior( sahf ) +{ + printManager.print ( "SAHF " ); +} + +// Debug 16/32 ok +//!Instruction pushfd behavior method. +void ac_behavior( pushfd ) +{ + printManager.print("PUSHF", "PUSHFD"); + push(MEM, GR, readSPRegister(SPR, EFLAGS)); +} + +// Debug 16/32 ok +//!Instruction popfd behavior method. +void ac_behavior( popfd ) +{ + printManager.print("POPF", "POPFD"); + uint aux = pop(MEM, GR); + writeSPRegister(SPR, EFLAGS, aux); +} + +// Debug ok +//!Instruction sti behavior method. +void ac_behavior( sti ) +{ + printManager.print ( "STI" ); + IFJustSet = JUST_SET; +} + +// Debug ok +//!Instruction cli behavior method. +void ac_behavior( cli ) +{ + printManager.print ( "CLI" ); + IFJustSet = NOT_SET; + resetFlag(SPR, FLAG_IF); +} + +// Debug ok +//!Instruction nop behavior method. +void ac_behavior( nop ) +{ + printManager.print ( "NOP" ); +} + +//!Instruction xlatb behavior method. +void ac_behavior( xlatb ) +{ + printManager.print ( "XLATB " ); +} + +// Debug ok +//!Instruction push_EAX behavior method. +void ac_behavior( push_EAX ) +{ + printManager.print ( "PUSH AX", "PUSH EAX" ); + push(MEM, GR, readRegister(GR, EAX) ); +} + +// Debug ok +//!Instruction push_ECX behavior method. +void ac_behavior( push_ECX ) +{ + printManager.print ( "PUSH CX", "PUSH ECX" ); + push(MEM, GR, readRegister(GR, ECX) ); +} + +// Debug ok +//!Instruction push_EDX behavior method. +void ac_behavior( push_EDX ) +{ + printManager.print ( "PUSH DX", "PUSH EDX" ); + push(MEM, GR, readRegister(GR, EDX) ); +} + +// Debug ok +//!Instruction push_EBX behavior method. +void ac_behavior( push_EBX ) +{ + printManager.print ( "PUSH BX", "PUSH EBX" ); + push(MEM, GR, readRegister(GR, EBX) ); +} + +// Debug ok +//!Instruction push_ESP behavior method. +void ac_behavior( push_ESP ) +{ + printManager.print ( "PUSH SP", "PUSH ESP" ); + push(MEM, GR, readRegister(GR, ESP) ); +} + +// Debug ok +//!Instruction push_EBP behavior method. +void ac_behavior( push_EBP ) +{ + printManager.print ( "PUSH BP", "PUSH EBP" ); + push(MEM, GR, readRegister(GR, EBP) ); +} + +// Debug ok +//!Instruction push_ESI behavior method. +void ac_behavior( push_ESI ) +{ + printManager.print ( "PUSH SI", "PUSH ESI" ); + push(MEM, GR, readRegister(GR, ESI) ); +} + +// Debug ok +//!Instruction push_EDI behavior method. +void ac_behavior( push_EDI ) +{ + printManager.print ( "PUSH DI", "PUSH EDI" ); + push(MEM, GR, readRegister(GR, EDI) ); +} + +// Debug ok +//!Instruction push_CS behavior method. +void ac_behavior( push_CS ) +{ + printManager.print ( "PUSH CS" ); + OperandSize = OPERAND_SIZE16; + push(MEM, GR, readSRegister(SR, CS) ); +} + +// Debug ok +//!Instruction push_SS behavior method. +void ac_behavior( push_SS ) +{ + printManager.print ( "PUSH SS" ); + OperandSize = OPERAND_SIZE16; + push(MEM, GR, readSRegister(SR, CS) ); +} + +// Debug ok +//!Instruction push_DS behavior method. +void ac_behavior( push_DS ) +{ + printManager.print ( "PUSH DS" ); + OperandSize = OPERAND_SIZE16; + push(MEM, GR, readSRegister(SR, DS) ); +} + +// Debug ok +//!Instruction push_ES behavior method. +void ac_behavior( push_ES ) +{ + printManager.print ( "PUSH ES" ); + OperandSize = OPERAND_SIZE16; + push(MEM, GR, readSRegister(SR, ES) ); +} + +// Debug ok +//!Instruction pop_EAX behavior method. +void ac_behavior( pop_EAX ) +{ + printManager.print ( "POP AX", "POP EAX" ); + writeRegister(GR, EAX,pop(MEM, GR)); +} + +// Debug ok +//!Instruction pop_ECX behavior method. +void ac_behavior( pop_ECX ) +{ + printManager.print ( "POP CX", "POP ECX" ); + writeRegister(GR, ECX,pop(MEM, GR)); +} + +// Debug ok +//!Instruction pop_EDX behavior method. +void ac_behavior( pop_EDX ) +{ + printManager.print ( "POP DX", "POP EDX" ); + writeRegister(GR, EDX,pop(MEM, GR)); +} + +// Debug ok +//!Instruction pop_EBX behavior method. +void ac_behavior( pop_EBX ) +{ + printManager.print ( "POP BX", "POP EBX" ); + writeRegister(GR, EBX,pop(MEM, GR)); +} + +// Debug ok +//!Instruction pop_ESP behavior method. +void ac_behavior( pop_ESP ) +{ + printManager.print ( "POP SP", "POP ESP" ); + writeRegister(GR, ESP,pop(MEM, GR)); +} + +// Debug ok +//!Instruction pop_EBP behavior method. +void ac_behavior( pop_EBP ) +{ + printManager.print ( "POP BP", "POP EBP" ); + writeRegister(GR, EBP,pop(MEM, GR)); +} + +// Debug ok +//!Instruction pop_ESI behavior method. +void ac_behavior( pop_ESI ) +{ + printManager.print ( "POP SI", "POP ESI" ); + writeRegister(GR, ESI,pop(MEM, GR)); +} + +// Debug ok +//!Instruction pop_EDI behavior method. +void ac_behavior( pop_EDI ) +{ + printManager.print ( "POP DI", "POP EDI" ); + writeRegister(GR, EDI,pop(MEM, GR)); +} + +// Debug ok +//!Instruction pop_DS behavior method. +void ac_behavior( pop_DS ) +{ + printManager.print ( "POP DS" ); + writeSRegister(SR, DS,pop(MEM, GR)); +} + +// Debug ok +//!Instruction pop_ES behavior method. +void ac_behavior( pop_ES ) +{ + printManager.print ( "POP ES" ); + writeSRegister(SR, ES,pop(MEM, GR)); +} + +// Debug ok +//!Instruction pop_SS behavior method. +void ac_behavior( pop_SS ) +{ + printManager.print ( "POP SS" ); + writeSRegister(SR, SS,pop(MEM, GR)); +} + +// Debug ok +//!Instruction push_a_ad behavior method. +void ac_behavior( push_a_ad ) +{ + printManager.print ( "PUSHA", "PUSHAD" ); + uint tempESP = readRegister(GR, ESP); + push(MEM, GR, readRegister(GR, EAX)); + push(MEM, GR, readRegister(GR, ECX)); + push(MEM, GR, readRegister(GR, EDX)); + push(MEM, GR, readRegister(GR, EBX)); + push(MEM, GR, tempESP); + push(MEM, GR, readRegister(GR, EBP)); + push(MEM, GR, readRegister(GR, ESI)); + push(MEM, GR, readRegister(GR, EDI)); +} + +// Debug ok +//!Instruction pop_a_ad behavior method. +void ac_behavior( pop_a_ad ) +{ + printManager.print ( "POPA", "POPAD" ); + uint tempESP; + writeRegister(GR, EDI,pop(MEM, GR)); + writeRegister(GR, ESI,pop(MEM, GR)); + writeRegister(GR, EBP,pop(MEM, GR)); + tempESP = pop(MEM, GR); + writeRegister(GR, EBX,pop(MEM, GR)); + writeRegister(GR, EDX,pop(MEM, GR)); + writeRegister(GR, ECX,pop(MEM, GR)); + writeRegister(GR, EAX,pop(MEM, GR)); + writeRegister(GR, ESP,tempESP); +} + +//!Instruction in_EAX_DX behavior method. +void ac_behavior( in_EAX_DX ) +{ + acprintf ( "IN EAX DX \n" ); +} + +//!Instruction out_DX_EAX behavior method. +void ac_behavior( out_DX_EAX ) +{ + acprintf ( "OUT DX EAX \n" ); +} + +//!Instruction cwd_cwq behavior method. +void ac_behavior( cwd_cwq ) +{ + printf ( "CWD/CDQ\n" ); + if ( OperandSize == OPERAND_SIZE16 ) + { + if ( MSB16(readRegister(GR, EAX)) ) writeRegister(GR, EDX,0xFFFF); + else writeRegister(GR, EDX,0); + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + if ( MSB32(readRegister(GR, EAX)) ) writeRegister(GR, EDX,0xFFFFFFFF); + else writeRegister(GR, EDX,0); + } +} + +// Debug ok +//!Instruction inc_EAX behavior method. +void ac_behavior( inc_EAX ) +{ + printManager.print ( "INC AX", "INC EAX" ); + uint op1 = readRegister(GR, EAX); + uint op2 = 1; + uint res = op1 + op2; + writeRegister(GR, EAX, res ); + checkFlags(SPR, OPER_ADD,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction inc_ECX behavior method. +void ac_behavior( inc_ECX ) +{ + printManager.print ( "INC CX", "INC ECX" ); + uint op1 = readRegister(GR, ECX); + uint op2 = 1; + uint res = op1 + op2; + writeRegister(GR, ECX,res); + checkFlags(SPR, OPER_ADD,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction inc_EDX behavior method. +void ac_behavior( inc_EDX ) +{ + printManager.print ( "INC DX", "INC EDX" ); + uint op1 = readRegister(GR, EDX); + uint op2 = 1; + uint res = op1 + op2; + writeRegister(GR, EDX,res); + checkFlags(SPR, OPER_ADD,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction inc_EBX behavior method. +void ac_behavior( inc_EBX ) +{ + printManager.print ( "INC BX", "INC EBX" ); + uint op1 = readRegister(GR, EBX); + uint op2 = 1; + uint res = op1 + op2; + writeRegister(GR, EBX,res); + checkFlags(SPR, OPER_ADD,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction inc_ESP behavior method. +void ac_behavior( inc_ESP ) +{ + printManager.print ( "INC SP", "INC ESP" ); + uint op1 = readRegister(GR, ESP); + uint op2 = 1; + uint res = op1 + op2; + writeRegister(GR, ESP, res); + checkFlags(SPR, OPER_ADD,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction inc_EBP behavior method. +void ac_behavior( inc_EBP ) +{ + printManager.print ( "INC BP", "INC EBP" ); + uint op1 = readRegister(GR, EBP); + uint op2 = 1; + uint res = op1 + op2; + writeRegister(GR, EBP, res); + checkFlags(SPR, OPER_ADD,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction inc_ESI behavior method. +void ac_behavior( inc_ESI ) +{ + printManager.print ( "INC SI", "INC ESI" ); + uint op1 = readRegister(GR, ESI); + uint op2 = 1; + uint res = op1 + op2; + writeRegister(GR, ESI, res); + checkFlags(SPR, OPER_ADD,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction inc_EDI behavior method. +void ac_behavior( inc_EDI ) +{ + printManager.print ( "INC DI", "INC EDI" ); + uint op1 = readRegister(GR, EDI); + uint op2 = 1; + uint res = op1 + op2; + writeRegister(GR, EDI, res); + checkFlags(SPR, OPER_ADD,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction dec_EAX behavior method. +void ac_behavior( dec_EAX ) +{ + printManager.print ( "DEC AX", "DEC EAX" ); + uint op1 = readRegister(GR, EAX); + uint op2 = 1; + uint res = op1 - op2; + writeRegister(GR, EAX, res); + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction dec_ECX behavior method. +void ac_behavior( dec_ECX ) +{ + printManager.print ( "DEC CX", "DEC ECX" ); + uint op1 = readRegister(GR, ECX); + uint op2 = 1; + uint res = op1 - op2; + writeRegister(GR, ECX, res); + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction dec_EDX behavior method. +void ac_behavior( dec_EDX ) +{ + printManager.print ( "DEC DX", "DEC EDX" ); + uint op1 = readRegister(GR, EDX); + uint op2 = 1; + uint res = op1 - op2; + writeRegister(GR, EDX, res); + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction dec_EBX behavior method. +void ac_behavior( dec_EBX ) +{ + printManager.print ( "DEC BX", "DEC EBX" ); + uint op1 = readRegister(GR, EBX); + uint op2 = 1; + uint res = op1 - op2; + writeRegister(GR, EBX, res); + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction dec_ESP behavior method. +void ac_behavior( dec_ESP ) +{ + printManager.print ( "DEC SP", "DEC ESP" ); + uint op1 = readRegister(GR, ESP); + uint op2 = 1; + uint res = op1 - op2; + writeRegister(GR, ESP, res); + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction dec_EBP behavior method. +void ac_behavior( dec_EBP ) +{ + printManager.print ( "DEC BP", "DEC EBP" ); + uint op1 = readRegister(GR, EBP); + uint op2 = 1; + uint res = op1 - op2; + writeRegister(GR, EBP, res); + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction dec_ESI behavior method. +void ac_behavior( dec_ESI ) +{ + printManager.print ( "DEC SI", "DEC ESI" ); + uint op1 = readRegister(GR, ESI); + uint op2 = 1; + uint res = op1 - op2; + writeRegister(GR, ESI, res); + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +// Debug ok +//!Instruction dec_EDI behavior method. +void ac_behavior( dec_EDI ) +{ + printManager.print ( "DEC DI", "DEC EDI" ); + uint op1 = readRegister(GR, EDI); + uint op2 = 1; + uint res = op1 - op2; + writeRegister(GR, EDI, res); + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + + + + + +//!Instruction iret_iretd behavior method. +void ac_behavior( iret_iretd ) +{ + acprintf ( " IRETD \n" ); +} + +// Debug ok +//!Instruction leave behavior method. +void ac_behavior( leave ) +{ + printManager.print("LEAVE"); + writeRegister(GR, ESP, readRegister(GR, EBP)); + writeRegister(GR, EBP, pop(MEM, GR)); +} + +//!Instruction movs_m32_m32 behavior method. +void ac_behavior( movs_m32_m32 ){ + acprintf ( " MOVS M32 M32\n" ); + + uint add_src = SR.read(DS)+GR.read(ESI); + uint add_dst = SR.read(ES)+GR.read(EDI); + uint df = SPR.read(EFLAGS)&(~FLAG_DF); + MEM.write(add_dst,MEM.read(add_src)); + if (df == 0) { + GR.write(ESI,GR.read(ESI)+4); + GR.write(EDI,GR.read(EDI)+4); + } else { + GR.write(ESI,GR.read(ESI)-4); + GR.write(EDI,GR.read(EDI)-4); + } +} + +//!Instruction cmps_m32_m32 behavior method. +void ac_behavior( cmps_m32_m32 ){ + acprintf ( " CMPS M32 M32\n" ); + + uint add_src1 = SR.read(DS)+GR.read(ESI); + uint add_src2 = SR.read(ES)+GR.read(EDI); + uint df = SPR.read(EFLAGS)&(~FLAG_DF); + + uint op1 = MEM.read(add_src1); + uint op2 = MEM.read(add_src2); + uint temp = op1 - op2; + checkFlags(SPR, OPER_SUB, op1, op2, temp,FLAG_ALL); + + if (df == 0) { + GR.write(ESI,GR.read(ESI)+4); + GR.write(EDI,GR.read(EDI)+4); + } else { + GR.write(ESI,GR.read(ESI)-4); + GR.write(EDI,GR.read(EDI)-4); + } +} + +//!Instruction scas_m32 behavior method. +void ac_behavior( scas_m32 ){ + acprintf ( " SCAS M32\n" ); + + uint add_src = SR.read(ES)+GR.read(EDI); + uint df = SPR.read(EFLAGS)&(~FLAG_DF); + + uint op1 = GR.read(EAX); + uint op2 = MEM.read(add_src); + uint temp = op1 - op2; + checkFlags(SPR, OPER_SUB, op1, op2, temp, FLAG_ALL); + + if (df == 0) { + GR.write(EDI,GR.read(EDI)+4); + } else { + GR.write(EDI,GR.read(EDI)-4); + } +} + +//!Instruction lods_m32 behavior method. +void ac_behavior( lods_m32 ){ + acprintf ( " LODS M32\n" ); + + uint add_src = SR.read(DS)+GR.read(ESI); + uint df = SPR.read(EFLAGS)&(~FLAG_DF); + + GR.write(EAX,MEM.read(add_src)); + + if (df == 0) { + GR.write(ESI,GR.read(ESI)+4); + } else { + GR.write(ESI,GR.read(ESI)-4); + } +} + +//!Instruction stos_m32 behavior method. +void ac_behavior( stos_m32 ){ + acprintf ( " STOS M32\n" ); + + uint add_src = SR.read(ES)+GR.read(EDI); + uint df = SPR.read(EFLAGS)&(~FLAG_DF); + + MEM.write(add_src,GR.read(EAX)); + + if (df == 0) { + GR.write(EDI,GR.read(EDI)+4); + } else { + GR.write(EDI,GR.read(EDI)-4); + } +} + +// Debug ok +//!Instruction ud2 behavior method. +void ac_behavior( ud2 ) +{ + printManager.print( "UD2 " ); +} + +// Debug ok +//!Instruction cpuid behavior method. +void ac_behavior( cpuid ) +{ + printManager.print ( "CPUID " ); + writeRegister(GR, EAX,0x00002005); + writeRegister(GR, ECX,0x00002005); + writeRegister(GR, EDX,0x00002005); + writeRegister(GR, EBX,0x00002005); +} + +// Debug ok +//!Instruction bswap_EAX_r32 behavior method. +void ac_behavior( bswap_EAX_r32 ) +{ + printManager.print ( "BSWAP AX", "BSWAP EAX" ); + uint op = readRegister(GR, EAX); + uint res = (op<<24)|((op<<8)&0xFF0000)|((op>>8)&0xFF00)|((op>>24)&0xFF); + writeRegister(GR, EAX,res); +} + +// Debug ok +//!Instruction bswap_ECX_r32 behavior method. +void ac_behavior( bswap_ECX_r32 ) +{ + printManager.print ( "BSWAP CX", "BSWAP ECX" ); + uint op = readRegister(GR, ECX); + uint res = (op<<24)|((op<<8)&0xFF0000)|((op>>8)&0xFF00)|((op>>24)&0xFF); + writeRegister(GR, ECX,res); +} + +// Debug ok +//!Instruction bswap_EDX_r32 behavior method. +void ac_behavior( bswap_EDX_r32 ) +{ + printManager.print ( "BSWAP DX", "BSWAP EDX" ); + uint op = readRegister(GR, EDX); + uint res = (op<<24)|((op<<8)&0xFF0000)|((op>>8)&0xFF00)|((op>>24)&0xFF); + writeRegister(GR, EDX,res); +} + +// Debug ok +//!Instruction bswap_EBX_r32 behavior method. +void ac_behavior( bswap_EBX_r32 ) +{ + printManager.print ( "BSWAP BX", "BSWAP EBX" ); + uint op = readRegister(GR, EBX); + uint res = (op<<24)|((op<<8)&0xFF0000)|((op>>8)&0xFF00)|((op>>24)&0xFF); + writeRegister(GR, EBX,res); +} + +// Debug ok +//!Instruction bswap_ESP_r32 behavior method. +void ac_behavior( bswap_ESP_r32 ) +{ + printManager.print ( "BSWAP SP", "BSWAP ESP" ); + uint op = readRegister(GR, ESP); + uint res = (op<<24)|((op<<8)&0xFF0000)|((op>>8)&0xFF00)|((op>>24)&0xFF); + writeRegister(GR, ESP,res); +} + +// Debug ok +//!Instruction bswap_EBP_r32 behavior method. +void ac_behavior( bswap_EBP_r32 ) +{ + printManager.print ( "BSWAP BP", "BSWAP EBP" ); + uint op = readRegister(GR, EBP); + uint res = (op<<24)|((op<<8)&0xFF0000)|((op>>8)&0xFF00)|((op>>24)&0xFF); + writeRegister(GR, EBP,res); +} + +// Debug ok +//!Instruction bswap_ESI_r32 behavior method. +void ac_behavior( bswap_ESI_r32 ) +{ + printManager.print ( "BSWAP SI", "BSWAP ESI" ); + uint op = readRegister(GR, ESI); + uint res = (op<<24)|((op<<8)&0xFF0000)|((op>>8)&0xFF00)|((op>>24)&0xFF); + writeRegister(GR, ESI,res); +} + +// Debug ok +//!Instruction bswap_EDI_r32 behavior method. +void ac_behavior( bswap_EDI_r32 ) +{ + printManager.print ( "BSWAP DI", "BSWAP EDI" ); + uint op = readRegister(GR, EDI); + uint res = (op<<24)|((op<<8)&0xFF0000)|((op>>8)&0xFF00)|((op>>24)&0xFF); + writeRegister(GR, EDI,res); +} + +// Debug ok +//!Instruction push_FS behavior method. +void ac_behavior( push_FS ) +{ + printManager.print ( "PUSH FS" ); + OperandSize = OPERAND_SIZE16; + push(MEM, GR, readSRegister(SR, FS)); +} + +// Debug ok +//!Instruction push_GS behavior method. +void ac_behavior( push_GS ) +{ + printManager.print ( "PUSH GS" ); + OperandSize = OPERAND_SIZE16; + push(MEM, GR, readSRegister(SR, GS)); +} + +// Debug ok +//!Instruction pop_FS behavior method. +void ac_behavior( pop_FS ) +{ + printManager.print ( "POP FS" ); + OperandSize = OPERAND_SIZE16; + writeSRegister(SR, FS,pop(MEM, GR)); +} + +// Debug ok +//!Instruction pop_GS behavior method. +void ac_behavior( pop_GS ) +{ + printManager.print ( "POP GS" ); + OperandSize = OPERAND_SIZE16; + writeRegister(GR, GS,pop(MEM, GR)); +} + +//!Instruction lds_r32_m16_32 behavior method. +void ac_behavior( lds_r32_m16_32 ) +{ + uint sel = readMemory16(MEM, data.address()); + uint offset = readMemory(MEM, data.address()+2); + printManager.printReg1Addr("LDS R16, M16:16","LDS R32, M16:32","LDS","LDS",sel,offset); + writeSRegister(SR, DS, sel); + writeRegister(GR, data.reg1(), offset); +} + +//!Instruction les_r32_m16_32 behavior method. +void ac_behavior( les_r32_m16_32 ) +{ + uint sel = readMemory16(MEM, data.address()); + uint offset = readMemory(MEM, data.address()+2); + printManager.printReg1Addr("LES R16, M16:16","LES R32, M16:32","LES","LES",sel,offset); + writeSRegister(SR, ES, sel); + writeRegister(GR, data.reg1(), offset); +} + +//!Instruction lea_r32_m behavior method. +void ac_behavior( lea_r32_m ) +{ + printManager.printReg1Addr ( "LEA R16, M", "LEA R32, M", "LEA", "LEA" ); + dataManager.setReg1(GR, data.address()); +} + +//!Instruction mov_rm32_r32 behavior method. +void ac_behavior( mov_rm32_r32 ) +{ + printManager.printReg2MReg1("MOV RM16, R16","MOV RM32, R32","MOV","MOV"); + dataManager.setMemOrReg2(MEM, GR, dataManager.getReg1(GR)); +} + + +//!Instruction mov_r32_rm32 behavior method. +void ac_behavior( mov_r32_rm32 ) +{ + printManager.printReg1MReg2("MOV R16, RM16","MOV R32, RM32","MOV","MOV"); + dataManager.setReg1(GR, dataManager.getMemOrReg2(MEM, GR)); +} + +//!Instruction mov_EAX_imm32 behavior method. +void ac_behavior( mov_EAX_imm32 ) +{ + uint i = dataManager.getImmediate(SPR, ac_pc); + printf("Teste EAX: %i\n",i); + printManager.printImm("MOV AX, IMM16","MOV EAX, IMM32","MOV AX,","MOV EAX,",i); + writeRegister(GR, EAX, i); +} + +//!Instruction mov_ECX_imm32 behavior method. +void ac_behavior( mov_ECX_imm32 ) +{ + uint i = dataManager.getImmediate(SPR, ac_pc); + printf("Teste ECX: %i\n",i); + printManager.printImm("MOV CX, IMM16","MOV ECX, IMM32","MOV CX,","MOV ECX,",i); + writeRegister(GR, ECX, i); +} + +//!Instruction mov_EDX_imm32 behavior method. +void ac_behavior( mov_EDX_imm32 ) +{ + uint i = dataManager.getImmediate(SPR, ac_pc); + printf("Teste EDX: %i\n",i); + printManager.printImm("MOV DX, IMM16","MOV EDX, IMM32","MOV DX,","MOV EDX,",i); + writeRegister(GR, EDX, i); +} + +//!Instruction mov_EBX_imm32 behavior method. +void ac_behavior( mov_EBX_imm32 ) +{ + uint i = dataManager.getImmediate(SPR, ac_pc); + printf("Teste EBX: %i\n",i); + printManager.printImm("MOV BX, IMM16","MOV EBX, IMM32","MOV BX,","MOV EBX,",i); + writeRegister(GR, EBX, i); +} + +//!Instruction mov_ESP_imm32 behavior method. +void ac_behavior( mov_ESP_imm32 ) +{ + uint i = dataManager.getImmediate(SPR, ac_pc); + printManager.printImm("MOV SP, IMM16","MOV ESP, IMM32","MOV SP,","MOV ESP,",i); + writeRegister(GR, ESP, i); +} + +//!Instruction mov_EBP_imm32 behavior method. +void ac_behavior( mov_EBP_imm32 ) +{ + uint i = dataManager.getImmediate(SPR, ac_pc); + printManager.printImm("MOV BP, IMM16","MOV EBP, IMM32","MOV BP,","MOV EBP,",i); + writeRegister(GR, EBP, i); +} + +//!Instruction mov_ESI_imm32 behavior method. +void ac_behavior( mov_ESI_imm32 ) +{ + uint i = dataManager.getImmediate(SPR, ac_pc); + printManager.printImm("MOV SI, IMM16","MOV ESI, IMM32","MOV SI,","MOV ESI,",i); + writeRegister(GR, ESI, i); +} + +//!Instruction mov_EDI_imm32 behavior method. +void ac_behavior( mov_EDI_imm32 ) +{ + uint i = dataManager.getImmediate(SPR, ac_pc); + printManager.printImm("MOV DI, IMM16","MOV EDI, IMM32","MOV DI,","MOV EDI,",i); + writeRegister(GR, EDI, i); +} + +//!Instruction mov_rm32_imm32 behavior method. +void ac_behavior( mov_rm32_imm32 ) +{ + + printf("�aqui!!!!!\n"); + uint i = dataManager.getImmediate(SPR, ac_pc); + printManager.printReg2MImm("MOV RM16, IMM16","MOV RM32, IMM32","MOV","MOV",i); + dataManager.setMemOrReg2(MEM, GR, i); +} + +//!Instruction xchg_EAX_r32 behavior method. +// void ac_behavior( xchg_EAX_EAX ){} + +//!Instruction xchg_ECX_r32 behavior method. +void ac_behavior( xchg_EAX_ECX ) +{ + acprintf ( "XCHG EAX, ECX\n" ); + uint aux = readRegister(GR, EAX); + writeRegister(GR, EAX, readRegister(GR, ECX)); + writeRegister(GR, ECX, aux); +} + +//!Instruction xchg_EDX_r32 behavior method. +void ac_behavior( xchg_EAX_EDX ) +{ + acprintf ( "XCHG EAX, EDX\n" ); + uint aux = readRegister(GR, EAX); + writeRegister(GR, EAX, readRegister(GR, EDX)); + writeRegister(GR, EDX, aux); +} + +//!Instruction xchg_EBX_r32 behavior method. +void ac_behavior( xchg_EAX_EBX ) +{ + acprintf ( "XCHG EAX, EBX\n" ); + uint aux = readRegister(GR, EAX); + writeRegister(GR, EAX, readRegister(GR, EBX)); + writeRegister(GR, EBX, aux); +} + +//!Instruction xchg_ESP_r32 behavior method. +void ac_behavior( xchg_EAX_ESP ) +{ + acprintf ( "XCHG EAX, ESP\n" ); + uint aux = readRegister(GR, EAX); + writeRegister(GR, EAX, readRegister(GR, ESP)); + writeRegister(GR, ESP, aux); +} + +//!Instruction xchg_EBP_r32 behavior method. +void ac_behavior( xchg_EAX_EBP ) +{ + acprintf ( "XCHG EAX, EBP\n" ); + uint aux = readRegister(GR, EAX); + writeRegister(GR, EAX, readRegister(GR, EBP)); + writeRegister(GR, EBP, aux); +} + +//!Instruction xchg_ESI_r32 behavior method. +void ac_behavior( xchg_EAX_ESI ) +{ + acprintf ( "XCHG EAX, ESI\n" ); + uint aux = readRegister(GR, EAX); + writeRegister(GR, EAX, readRegister(GR, ESI)); + writeRegister(GR, ESI, aux); +} + +//!Instruction xchg_EDI_r32 behavior method. +void ac_behavior( xchg_EAX_EDI ) +{ + acprintf ( "XCHG EAX, EDI\n" ); + uint aux = readRegister(GR, EAX); + writeRegister(GR, EAX, readRegister(GR, EDI)); + writeRegister(GR, EDI, aux); +} + +//!Instruction xchg_rm32_r32 behavior method. +void ac_behavior( xchg_rm32_r32 ) +{ + acprintf ( "XCHG RM32, R32\n" ); + uint aux; + if ( data.usesMemory() ) + { + aux = readRegister(GR, data.reg1()); + writeRegister(GR, data.reg1(), readMemory(MEM, data.address())); + writeMemory(MEM, data.address(), aux); + } + else + { + aux = readRegister(GR, data.reg1()); + writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + writeRegister(GR, data.reg2(), aux); + } +} + +//!Instruction push_rm32 behavior method. +void ac_behavior( push_rm32 ) +{ + acprintf ( "PUSH RM32\n" ); + if ( data.usesMemory() ) push(MEM, GR, readMemory(MEM, data.address())); + else push(MEM, GR, readRegister(GR, data.reg2())); +} + +//!Instruction push_imm32 behavior method. +void ac_behavior( push_imm32 ) +{ + acprintf ( "PUSH IMM32\n" ); + push(MEM, GR, dataManager.getImmediate(SPR, ac_pc)); +} + +//!Instruction pop_rm32 behavior method. +void ac_behavior( pop_rm32 ) +{ + acprintf ( "POP RM32\n" ); + if ( data.usesMemory() ) writeMemory(MEM, data.address(),pop(MEM, GR)); + else writeRegister(GR, data.reg2(),pop(MEM, GR)); +} + +//!Instruction in_EAX_imm8 behavior method. +void ac_behavior( in_EAX_imm8 ) +{ + acprintf ( "IN EAX, IMM8 \n" ); +} + +//!Instruction out_imm8_EAX behavior method. +void ac_behavior( out_imm8_EAX ) +{ + acprintf ( "OUT IMM8, EAX \n" ); +} + +//!Instruction add_EAX_imm32 behavior method. +void ac_behavior( add_EAX_imm32 ) +{ + acprintf ( "ADD EAX, IMM32\n" ); + uint op1 = readRegister(GR, EAX); + uint op2 = dataManager.getImmediate(SPR, ac_pc); + uint aux = op1 + op2; + writeRegister(GR, EAX,aux); + checkFlags(SPR, OPER_ADD,op1,op2,aux,FLAG_ALL); +} + +//!Instruction add_rm32_imm32 behavior method. +void ac_behavior( add_rm32_imm32 ) +{ + uint op1, op2, aux; + acprintf ( "ADD RM32, IMM32\n" ); + if ( data.usesMemory() ) + { + op1 = readMemory(MEM, data.address()); + op2 = dataManager.getImmediate(SPR, ac_pc); + aux = op1 + op2; + writeMemory(MEM, data.address(),aux); + } + else + { + op1 = readRegister(GR, data.reg2()); + op2 = dataManager.getImmediate(SPR, ac_pc); + aux = op1 + op2; + writeRegister(GR, data.reg2(), aux); + } + checkFlags(SPR, OPER_ADD,op1,op2,aux,FLAG_ALL); +} + +//!Instruction add_rm32_imm8 behavior method. +void ac_behavior( add_rm32_imm8 ) +{ + // acprintf ( "ADD RM32, IMM8\t\t" ); + signed char i = data.immediate8(SPR, ac_pc); + signed int ii = i; + uint op1, op2, aux; + if ( data.usesMemory() ) + { + op1 = readMemory(MEM, data.address()); + op2 = ii; + if ( op2 & (1<<7) ) op2 = op2|0xFFFFFF00; + aux = op1 + op2; + writeMemory(MEM, data.address(), aux); + } + else + { + op1 = readRegister(GR, data.reg2()); + op2 = ii; + if ( op2 & (1<<7) ) op2 = op2|0xFFFFFF00; + aux = op1 + op2; + writeRegister(GR, data.reg2(),aux); + } + if ( data.usesMemory() ) acprintfmi ( "ADD", data.address(), op2 ); + else acprintfri ( "ADD", data.reg2(), op2 ); + checkFlags(SPR, OPER_ADD,op1,op2,aux,FLAG_ALL); +} + +//!Instruction add_rm32_r32 behavior method. +void ac_behavior( add_rm32_r32 ) +{ + uint op1, op2, aux; + // acprintf ( "ADD RM32, R32\n" ); + printf ( "ADD " ); + if ( data.usesMemory() ) + { + printf ( "[0x%08X], ", data.address() ); + op1 = readMemory(MEM, data.address()); + op2 = readRegister(GR, data.reg1()); + aux = op1 + op2; + writeMemory(MEM, data.address(), aux); + } + else + { + if ( OperandSize == OPERAND_SIZE16 ) printf ( "%s, ", reg_str16[data.reg1()] ); + else printf ( "%s, ", reg_str[data.reg1()] ); + op1 = readRegister(GR, data.reg1()); + op2 = readRegister(GR, data.reg2()); + aux = op1 + op2; + writeRegister(GR, data.reg2(), aux); + } + if ( OperandSize == OPERAND_SIZE16 ) printf ( "%s\n", reg_str16[data.reg2()] ); + else printf ( "%s\n", reg_str[data.reg2()] ); + checkFlags(SPR, OPER_ADD,op1,op2,aux,FLAG_ALL); +} + +//!Instruction add_r32_rm32 behavior method. +void ac_behavior( add_r32_rm32 ) +{ + uint op1, op2, aux; + acprintf ( "ADD R32, RM32\n" ); + if ( data.usesMemory() ) + { + op1 = readRegister(GR, data.reg1()); + op2 = readMemory(MEM, data.address()); + aux = op1 + op2; + writeRegister(GR, data.reg1(),aux); + } + else + { + op1 = readRegister(GR, data.reg1()); + op2 = readRegister(GR, data.reg2()); + aux = op1 + op2; + writeRegister(GR, data.reg1(),aux); + } + checkFlags(SPR, OPER_ADD,op1,op2,aux,FLAG_ALL); +} + +//!Instruction adc_EAX_imm32 behavior method. +void ac_behavior( adc_EAX_imm32 ) +{ + acprintf ( "ADC EAX, IMM32\n" ); + uint op1, op2, aux, carry=0; + if ( testFlag (SPR, FLAG_CF ) ) carry = 1; + op1 = readRegister(GR, EAX); + op2 = dataManager.getImmediate(SPR, ac_pc) + carry; + aux = op1 + op2; + writeRegister(GR, EAX, aux); + checkFlags(SPR, OPER_ADD,op1,op2,aux,FLAG_ALL); +} + +//!Instruction adc_rm32_r32 behavior method. +void ac_behavior( adc_rm32_r32 ) +{ + acprintf ( "ADC RM32, R32\n" ); + uint op1, op2, res; + op1 = dataManager.getMemOrReg2(MEM, GR); + op2 = dataManager.getReg1(GR) + testFlag(SPR, FLAG_CF); + res = op1 + op2; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_ADD,op1,op2,res,FLAG_ALL); +} + +//!Instruction adc_r32_rm32 behavior method. +void ac_behavior( adc_r32_rm32 ) +{ + acprintf ( "ADC R32, RM32\n" ); + uint op1, op2, res; + if ( data.usesMemory() ) + { + op1 = readMemory(MEM, data.address()); + op2 = readRegister(GR, data.reg1())+testFlag(SPR, FLAG_CF); + res = op1 + op2; + writeRegister(GR, data.reg1(),res); + } + else + { + op1 = readRegister(GR, data.reg1()); + op2 = readRegister(GR, data.reg2())+testFlag(SPR, FLAG_CF); + res = op1 + op2; + GR.write(data.reg1(),res); + } + checkFlags(SPR, OPER_ADD,op1,op2,res,FLAG_ALL); +} + +//!Instruction sub_EAX_imm32 behavior method. +void ac_behavior( sub_EAX_imm32 ) +{ + acprintf ( "SUB EAX, IMM32\n" ); + uint op1, op2, res; + op1 = readRegister(GR, EAX); + op2 = dataManager.getImmediate(SPR, ac_pc); + res = op1 - op2; + writeRegister(GR, EAX, res); + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL); +} + +//!Instruction sub_rm32_r32 behavior method. +void ac_behavior( sub_rm32_r32 ) +{ + uint op1, op2, res; + //acprintf ( "SUB RM32, R32\n" ); + printf ( "SUB " ); + if ( data.usesMemory() ) printf ( "[0x%08X], ", data.address() ); + else + { + if ( OperandSize == OPERAND_SIZE16 ) printf ( "%s, ", reg_str16[data.reg2()] ); + else printf ( "%s, ", reg_str[data.reg2()] ); + } + op1 = dataManager.getMemOrReg2(MEM, GR); + op2 = dataManager.getReg1(GR); + if ( OperandSize == OPERAND_SIZE16 ) printf ( "%s\n", reg_str16[data.reg1()] ); + else printf ( "%s\n", reg_str[data.reg1()] ); + res = op1 - op2; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL); +} + +//!Instruction sub_r32_rm32 behavior method. +void ac_behavior( sub_r32_rm32 ) +{ + acprintf ( "SUB R32, RM32\n" ); + uint op1, op2, res; + op1 = dataManager.getReg1(GR); + op2 = dataManager.getMemOrReg2(MEM, GR); + res = op1 - op2; + dataManager.setReg1(GR, res); + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL); +} + +//!Instruction sbb_EAX_imm32 behavior method. +void ac_behavior( sbb_EAX_imm32 ) +{ + acprintf ( "SBB EAX, IMM32\n" ); + uint op1, op2, res, carry=0; + if ( testFlag (SPR, FLAG_CF ) ) carry=1; + op1 = readRegister(GR, EAX); + op2 = dataManager.getImmediate(SPR, ac_pc) + carry; + res = op1 - op2; + writeRegister(GR, EAX,res); + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL); +} + +//!Instruction sbb_rm32_r32 behavior method. +void ac_behavior( sbb_rm32_r32 ) +{ + acprintf ( "SBB RM32, R32\n" ); + uint op1, op2, res, carry=0; + if ( testFlag (SPR, FLAG_CF ) ) carry = 1; + op1 = dataManager.getMemOrReg2(MEM, GR); + op2 = dataManager.getReg1(GR) + carry; + res = op1 - op2; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags (SPR, OPER_SUB,op1,op2,res,FLAG_ALL ); +} + +//!Instruction sbb_r32_rm32 behavior method. +void ac_behavior( sbb_r32_rm32 ) +{ + acprintf ( "SBB R32, RM32\n" ); + uint op1, op2, res, carry=0; + if ( testFlag (SPR, FLAG_CF ) ) carry = 1; + op1 = dataManager.getReg1(GR); + op2 = dataManager.getMemOrReg2(MEM, GR) + carry; + res = op1 - op2; + dataManager.setReg1(GR, res); + checkFlags (SPR, OPER_SUB,op1,op2,res,FLAG_ALL ); +} + +//!Instruction mul_rm32 behavior method. +void ac_behavior( mul_rm32 ) +{ + acprintf ( "MUL RM32\n" ); + uint op1 = readRegister(GR, EAX); + uint op2 = dataManager.getMemOrReg2(MEM, GR); + unsigned long long lop1 = op1; + unsigned long long lop2 = op2; + unsigned long long res = lop1 * lop2; + if ( ((OperandSize==OPERAND_SIZE32)&&(res>0xFFFFFFFF))|| + ((OperandSize==OPERAND_SIZE16)&&(res>0xFFFF)) ) + { + setFlag(SPR, FLAG_OF); + setFlag(SPR, FLAG_CF); + } + else + { + resetFlag(SPR, FLAG_OF); + resetFlag(SPR, FLAG_CF); + } + uint mask = 0xFFFFFFFF; + uint disp_ = 32; + if ( OperandSize == OPERAND_SIZE16 ) + { + mask = 0xFFFF; + disp_ = 16; + } + writeRegister(GR, EDX, res >> disp_ ); + writeRegister(GR, EAX, res & mask ); +} + +//!Instruction imul_r32_rm32_imm8 behavior method. +void ac_behavior( imul_r32_rm32_imm8 ) +{ + acprintf ( " IMUL R32, RM32, IMM8\n" ); + signed int op1, op2; + signed long long aux; + uint64 mask = 0xFFFFFFFF; + mask = mask<<32; + if ( data.usesMemory() ) + { + op1 = data.immediate8(SPR, ac_pc); + op2 = MEM.read(data.address()); + aux = op1*op2; + GR.write(data.reg1(),aux); + } + else + { + op1 = data.immediate8(SPR, ac_pc); + op2 = GR.read(data.reg1()); + aux = op1*op2; + GR.write(data.reg2(),aux); + } + if ( aux & mask ) + { + setFlag(SPR, FLAG_OF); + setFlag(SPR, FLAG_CF); + } + else + { + resetFlag(SPR, FLAG_OF); + resetFlag(SPR, FLAG_CF); + } +} + +//!Instruction imul_r32_rm32_imm32 behavior method. +void ac_behavior( imul_r32_rm32_imm32 ) +{ + acprintf ( " IMUL R32, RM32, IMM32\n" ); + signed int op1, op2; + signed long long aux; + uint64 mask = 0xFFFFFFFF; + mask = mask<<32; + if ( data.usesMemory() ) + { + op1 = data.immediate(SPR, ac_pc); + op2 = MEM.read(data.address()); + aux = op1*op2; + GR.write(data.reg1(),aux); + } + else + { + op1 = data.immediate(SPR, ac_pc); + op2 = GR.read(data.reg1()); + aux = op1*op2; + GR.write(data.reg2(),aux); + } + if ( aux & mask ) + { + setFlag(SPR, FLAG_OF); + setFlag(SPR, FLAG_CF); + } + else + { + resetFlag(SPR, FLAG_OF); + resetFlag(SPR, FLAG_CF); + } +} + +//!Instruction cmp_EAX_imm32 behavior method. +void ac_behavior( cmp_EAX_imm32 ) +{ + acprintf ( "CMP EAX, IMM32\n" ); + uint op1, op2, aux; + op1 = readRegister(GR, EAX); + op2 = dataManager.getImmediate(SPR, ac_pc); + aux = op1 + (~op2) + 0x01; + checkFlags(SPR, OPER_SUB,op1,op2,aux,FLAG_ALL); +} + +//!Instruction cmp_rm32_r32 behavior method. +void ac_behavior( cmp_rm32_r32 ) +{ + acprintf ( "CMP RM32, R32\n" ); + uint op1, op2, aux; + if ( data.usesMemory() ) + { + op1 = readMemory(MEM, data.address()); + op2 = readRegister(GR, data.reg1()); + } + else + { + op2 = readRegister(GR, data.reg1()); + op1 = readRegister(GR, data.reg2()); + } + aux = op1 + (~op2) + 0x01; + checkFlags(SPR, OPER_SUB,op1,op2,aux,FLAG_ALL); +} + +//!Instruction cmp_r32_rm32 behavior method. +void ac_behavior( cmp_r32_rm32 ) +{ + acprintf ( "CMP R32, RM32\n" ); + uint op1, op2, res; + op1 = dataManager.getReg1(GR); + op2 = dataManager.getMemOrReg2(MEM, GR); + res = op1 - op2; + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL); +} + +//!Instruction and_EAX_imm32 behavior method. +void ac_behavior( and_EAX_imm32 ) +{ + acprintf ( "AND EAX, IMM32\n" ); + uint op1, op2, res; + op1 = readRegister(GR, EAX); + op2 = dataManager.getImmediate(SPR, ac_pc); + res = op1 & op2; + writeRegister(GR, EAX, res); + resetFlag ( SPR, FLAG_OF ); + resetFlag ( SPR, FLAG_CF ); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_SF|FLAG_ZF|FLAG_PF ); +} + +//!Instruction and_rm32_r32 behavior method. +void ac_behavior( and_rm32_r32 ) +{ + acprintf ( "AND RM32, R32\n" ); + uint op1, op2, res; + op1 = dataManager.getMemOrReg2(MEM, GR); + op2 = dataManager.getReg1(GR); + res = op1 & op2; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_ALL); + resetFlag(SPR, FLAG_CF); resetFlag(SPR, FLAG_OF); +} + +//!Instruction and_r32_rm32 behavior method. +void ac_behavior( and_r32_rm32 ) +{ + acprintf ( "AND R32, RM32\n" ); + uint op1, op2, res; + op1 = dataManager.getMemOrReg2(MEM, GR); + op2 = dataManager.getReg1(GR); + res = op1 & op2; + dataManager.setReg1(GR, res); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_ALL); + resetFlag(SPR, FLAG_CF); resetFlag(SPR, FLAG_OF); +} + +//!Instruction or_EAX_imm32 behavior method. +void ac_behavior( or_EAX_imm32 ) +{ + acprintf ( "OR EAX, IMM32\n" ); + uint op1, op2, res; + op1 = readRegister(GR, EAX); + op2 = dataManager.getImmediate(SPR, ac_pc); + res = op1 | op2; + writeRegister(GR, EAX, res); + resetFlag ( SPR, FLAG_OF ); + resetFlag ( SPR, FLAG_CF ); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_SF|FLAG_ZF|FLAG_PF ); +} + +//!Instruction or_rm32_r32 behavior method. +void ac_behavior( or_rm32_r32 ) +{ + acprintf ( "OR RM32, R32\n" ); + uint op1, op2, res; + op1 = dataManager.getMemOrReg2(MEM, GR); + op2 = dataManager.getReg1(GR); + res = op1 | op2; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_ALL); + resetFlag(SPR, FLAG_OF);resetFlag(SPR, FLAG_CF); +} + +//!Instruction or_r32_rm32 behavior method. +void ac_behavior( or_r32_rm32 ) +{ + acprintf ( "OR R32, RM32\n" ); + uint op1, op2, res; + op1 = dataManager.getMemOrReg2(MEM, GR); + op2 = dataManager.getReg1(GR); + res = op1|op2; + dataManager.setReg1(GR, res); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_ALL); + resetFlag(SPR, FLAG_OF); resetFlag(SPR, FLAG_CF); +} + +//!Instruction xor_EAX_imm32 behavior method. +void ac_behavior( xor_EAX_imm32 ) +{ + acprintf ( "XOR EAX, IMM32\n" ); + uint op1, op2, res; + op1 = readRegister(GR, EAX); + op2 = dataManager.getImmediate(SPR, ac_pc); + res = op1 ^ op2; + writeRegister(GR, EAX, res); + resetFlag ( SPR, FLAG_OF ); + resetFlag ( SPR, FLAG_CF ); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_SF|FLAG_ZF|FLAG_PF ); +} + +//!Instruction xor_rm32_r32 behavior method. +void ac_behavior( xor_rm32_r32 ) +{ + acprintf ( "XOR RM32, R32\n" ); + uint op1, op2, res; + op1 = dataManager.getMemOrReg2(MEM, GR); + op2 = dataManager.getReg1(GR); + res = op1 ^ op2; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_ALL); + resetFlag(SPR, FLAG_OF); resetFlag(SPR, FLAG_CF); +} + +//!Instruction xor_r32_rm32 behavior method. +void ac_behavior( xor_r32_rm32 ) +{ + acprintf ( "XOR R32, RM32\n" ); + uint op1, op2, res; + op1 = dataManager.getMemOrReg2(MEM, GR); + op2 = dataManager.getReg1(GR); + res = op1^op2; + dataManager.setReg1(GR, res); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_ALL); + resetFlag(SPR, FLAG_OF); resetFlag(SPR, FLAG_CF); +} + +//!Instruction sal_shl_1_rm32 behavior method. +void ac_behavior( sal_shl_1_rm32 ) +{ + // acprintf ( "SAL RM32\n" ); + printf ( "SAL " ); + unsigned int op = dataManager.getMemOrReg2(MEM, GR); + unsigned int res = op << 1; + dataManager.setMemOrReg2(MEM, GR, res); + if ( data.usesMemory() ) printf ( "[0x%08X]\n", data.address() ); + else + { + if ( OperandSize == OPERAND_SIZE16 ) printf ( "%s\n", reg_str16[data.reg2()] ); + else printf ( "%s\n", reg_str[data.reg2()] ); + } + if ( OperandSize == OPERAND_SIZE16 ) writeFlag(SPR, FLAG_CF, MSB16(op)); + else if ( OperandSize == OPERAND_SIZE32 ) writeFlag(SPR, FLAG_CF, MSB32(op)); + bool of16 = (testFlag(SPR, FLAG_CF)&&!MSB16(res))||(!testFlag(SPR, FLAG_CF)&&MSB16(res)); + bool of32 = (testFlag(SPR, FLAG_CF)&&!MSB32(res))||(!testFlag(SPR, FLAG_CF)&&MSB32(res)); + if ( OperandSize == OPERAND_SIZE16 ) writeFlag(SPR, FLAG_OF, of16); + else if ( OperandSize == OPERAND_SIZE32 ) writeFlag(SPR, FLAG_OF, of32); +} + + +//!Instruction sal_shl_cl_rm32 behavior method. +void ac_behavior( sal_shl_cl_rm32 ) +{ + //acprintf ( "SAL CL RM32\n" ); + printf ( "SAL CL " ); + unsigned int op = dataManager.getMemOrReg2(MEM, GR); + unsigned char cl = readRegister8(GR, CL); + unsigned int res = op << cl;//shift CL + dataManager.setMemOrReg2(MEM, GR, res); + if ( data.usesMemory() ) printf ( "[0x%08X]\n", data.address() ); + else + { + if ( OperandSize == OPERAND_SIZE16 ) printf ( "%s\n", reg_str16[data.reg2()] ); + else printf ( "%s\n", reg_str[data.reg2()] ); + } + + //set CF Flag + if (cl>0) { + unsigned int flag = (op << (cl-1)); + if ( OperandSize == OPERAND_SIZE16 ) writeFlag(SPR, FLAG_CF, MSB16(flag)); + else if ( OperandSize == OPERAND_SIZE32 ) writeFlag(SPR, FLAG_CF, MSB32(flag)); + } + + if (cl==1) { + bool of16 = (testFlag(SPR, FLAG_CF)&&!MSB16(res))||(!testFlag(SPR, FLAG_CF)&&MSB16(res)); + bool of32 = (testFlag(SPR, FLAG_CF)&&!MSB32(res))||(!testFlag(SPR, FLAG_CF)&&MSB32(res)); + if ( OperandSize == OPERAND_SIZE16 ) writeFlag(SPR, FLAG_OF, of16); + else if ( OperandSize == OPERAND_SIZE32 ) writeFlag(SPR, FLAG_OF, of32); + } + checkFlags(SPR, OPER_NONE,0,0,res,FLAG_ALL); +} + +//!Instruction sar_1_rm32 behavior method +void ac_behavior( sar_1_rm32 ) +{ + //acprintf ( "SAR RM32\n" ); + printf ( "SAR " ); + if ( data.usesMemory() ) printf ( "[0x%08X]\n", data.address() ); + else + { + if ( OperandSize == OPERAND_SIZE16 ) printf ( "%s\n", reg_str16[data.reg2()] ); + else printf ( "%s\n", reg_str[data.reg2()] ); + } + signed int op = dataManager.getMemOrReg2(MEM, GR); + signed int res = op >> 1; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_NONE,0,0,res,FLAG_ALL); + resetFlag(SPR, FLAG_OF); + writeFlag(SPR, FLAG_CF, op&0x01); +} + + +//!Instruction sar_cl_rm32 behavior method +void ac_behavior( sar_cl_rm32 ) +{ + acprintf ( "SAR CL RM32\n" ); + printf ( "SAR CL " ); + if ( data.usesMemory() ) printf ( "[0x%08X]\n", data.address() ); + else + { + if ( OperandSize == OPERAND_SIZE16 ) printf ( "%s\n", reg_str16[data.reg2()] ); + else printf ( "%s\n", reg_str[data.reg2()] ); + } + signed int op = dataManager.getMemOrReg2(MEM, GR); + unsigned char cl = readRegister8(GR, CL); + signed int res = op >> cl; //amount = CL + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_NONE,0,0,res,FLAG_ALL); + if (cl==1) resetFlag(SPR, FLAG_OF); + if (cl>0) writeFlag(SPR, FLAG_CF, (op>>(cl-1))&0x01); +} + +//!Instruction shr_1_rm32 behavior method +void ac_behavior( shr_1_rm32 ) +{ + acprintf ( "SHR RM32\n" ); + uint op = dataManager.getMemOrReg2(MEM, GR); + if ( OperandSize == OPERAND_SIZE16 ) op = op&MASK_16BITS; + uint res = op >> 1; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_NONE,0,0,res,FLAG_ALL); + writeFlag(SPR, FLAG_CF, op&0x01); + if ( OperandSize == OPERAND_SIZE16 ) writeFlag(SPR, FLAG_OF,MSB16(op)); + else if ( OperandSize == OPERAND_SIZE32 ) writeFlag(SPR, FLAG_OF,MSB32(op)); +} + +//!Instruction shr_cl_rm32 behavior method +void ac_behavior( shr_cl_rm32 ) +{ + acprintf ( "SHR CL RM32\n" ); + uint op = dataManager.getMemOrReg2(MEM, GR); + if ( OperandSize == OPERAND_SIZE16 ) op = op&MASK_16BITS; + unsigned char cl = readRegister8(GR, CL); + uint res = op >> cl; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_NONE,0,0,res,FLAG_ALL); + if (cl>0) writeFlag(SPR, FLAG_CF, (op>>(cl-1))&0x01); + if (cl==1) { + if ( OperandSize == OPERAND_SIZE16 ) writeFlag(SPR, FLAG_OF,MSB16(op)); + else if ( OperandSize == OPERAND_SIZE32 ) writeFlag(SPR, FLAG_OF,MSB32(op)); + } +} + +//!Instruction sal_shl_rm32_imm8 behavior method +void ac_behavior( sal_shl_rm32_imm8 ) +{ + //acprintf( "SAL RM32, IMM8\n" ); + acprintf("SAL "); + if ( data.usesMemory() ) printf ( "[0x%08X], ", data.address() ); + else + { + if ( OperandSize == OPERAND_SIZE16 ) printf ( "%s, ", reg_str16[data.reg2()] ); + else printf ( "%s, ", reg_str[data.reg2()] ); + } + unsigned int op = dataManager.getMemOrReg2(MEM, GR); + signed char count = data.immediate8(SPR, ac_pc); + unsigned int res = op << count; + printf ( "0x%02X\n", count ); + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_NONE,0,0,res,FLAG_ALL); + if ( OperandSize == OPERAND_SIZE16 ) writeFlag(SPR, FLAG_CF,MSB16(op)); + else if ( OperandSize == OPERAND_SIZE32 ) writeFlag(SPR, FLAG_CF,MSB32(op)); + bool of16 = (!testFlag(SPR, FLAG_CF)&&MSB16(res))||(testFlag(SPR, FLAG_CF)&&!MSB16(res)); + bool of32 = (!testFlag(SPR, FLAG_CF)&&MSB32(res))||(testFlag(SPR, FLAG_CF)&&!MSB32(res)); + if ( OperandSize == OPERAND_SIZE16 ) writeFlag(SPR, FLAG_OF, of16); + else if ( OperandSize == OPERAND_SIZE32 ) writeFlag(SPR, FLAG_OF, of32 ); +} + +//!Instruction sar_rm32_imm8 behavior method +void ac_behavior( sar_rm32_imm8 ) +{ + //acprintf ( "SAR RM32, IMM8\n" ); + printf ( "SAR " ); + if ( data.usesMemory() ) printf ( "[0x%08X], ", data.address() ); + else + { + if ( OperandSize == OPERAND_SIZE16 ) printf ( "%s, ", reg_str16[data.reg2()] ); + else printf ( "%s, ", reg_str[data.reg2()] ); + } + signed int op = dataManager.getMemOrReg2(MEM, GR); + signed char count = data.immediate8(SPR, ac_pc); + printf ( "0x%02X\n", count ); + signed int res = op >> count; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_NONE,0,0,res,FLAG_ALL); + if ( count > 0 ) writeFlag(SPR, FLAG_CF, (op>>(count-1))&0x01); +} + +//!Instruction shr_rm32_imm8 behavior method +void ac_behavior( shr_rm32_imm8 ) +{ + printf ( "SHR RM32, IMM8\n" ); + signed char count; + unsigned int op, res; + op = dataManager.getMemOrReg2(MEM, GR); + if ( OperandSize == OPERAND_SIZE16 ) op = op & MASK_16BITS; + count = data.immediate8(SPR, ac_pc); + res = op >> count; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_NONE,0,0,res,FLAG_ALL); + if ( OperandSize == OPERAND_SIZE16 ) writeFlag(SPR, FLAG_OF, MSB16(op)); + else if ( OperandSize == OPERAND_SIZE32 ) writeFlag(SPR, FLAG_OF, MSB32(op)); + if ( count > 0 ) writeFlag(SPR, FLAG_CF, (op>>(count-1))&0x01); +} + +//!Instruction test_eax_imm32 behavior method. +void ac_behavior( test_eax_imm32 ) +{ + acprintf ( " TEST EAX, IMM32\n" ); + uint op1, op2, aux; + op1 = GR.read(EAX); + op2 = data.immediate(SPR, ac_pc); + aux = op1 & op2; + resetFlag ( SPR, FLAG_OF ); + resetFlag ( SPR, FLAG_CF ); + checkFlags (SPR, OPER_NONE,op1,op2,aux,FLAG_SF|FLAG_ZF|FLAG_PF ); +} + +//!Instruction test_rm32_r32 behavior method. +void ac_behavior( test_rm32_r32 ) +{ + acprintf ( "TEST RM32, R32\n" ); + uint op1, op2, res; + op1 = dataManager.getMemOrReg2(MEM, GR); + op2 = dataManager.getReg1(GR); + res = op1 & op2; + resetFlag ( SPR, FLAG_OF ); + resetFlag ( SPR, FLAG_CF ); + checkFlags (SPR, OPER_NONE,op1,op2,res,FLAG_SF|FLAG_ZF|FLAG_PF ); +} + +//!Instruction ja_jnbe_rel8 behavior method. +void ac_behavior( ja_jnbe_rel8 ) +{ + acprintf ( " JA/JNBE REL8\n" ); + if ( testFlag(SPR, FLAG_CF)==false && testFlag(SPR, FLAG_ZF)==false ) + { + if ( data.address8()&(1<<7) ) ac_pc-= ((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jae_jnb_jnc_rel8 behavior method. +void ac_behavior( jae_jnb_jnc_rel8 ) +{ + acprintf ( " JAE/JNB/JNC REL8\n" ); + if ( testFlag(SPR, FLAG_CF)==false ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jb_jc_jnae_rel8 behavior method. +void ac_behavior( jb_jc_jnae_rel8 ) +{ + acprintf ( " JB/JC/JNAE REL8\n" ); + if ( testFlag(SPR, FLAG_CF)==true ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jbe_jna_rel8 behavior method. +void ac_behavior( jbe_jna_rel8 ) +{ + acprintf ( " JBE/JNA REL8\n" ); + if ( (testFlag(SPR, FLAG_CF)==true) || (testFlag(SPR, FLAG_ZF)==true) ) + { + printf ( "Branch taken\n" ); + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction je_jz_rel8 behavior method. +void ac_behavior( je_jz_rel8 ) +{ + acprintf ( " JE/JZ REL8\n" ); + if ( testFlag(SPR, FLAG_ZF)==true ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jg_jnle_rel8 behavior method. +void ac_behavior( jg_jnle_rel8 ) +{ + acprintf ( " JG/JNLE REL8\n" ); + if ( testFlag(SPR, FLAG_ZF)==false && (testFlag(SPR, FLAG_SF)==testFlag(SPR, FLAG_OF)) ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jge_jnl_rel8 behavior method. +void ac_behavior( jge_jnl_rel8 ) +{ + acprintf ( "JGE/JNL REL8\n" ); + if ( testFlag(SPR, FLAG_SF)==testFlag(SPR, FLAG_OF) ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jl_jnge_rel8 behavior method. +void ac_behavior( jl_jnge_rel8 ) +{ + acprintf ( " JL/JNGE REL8\n" ); + if ( testFlag(SPR, FLAG_SF)!=testFlag(SPR, FLAG_OF) ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jle_jng_rel8 behavior method. +void ac_behavior( jle_jng_rel8 ) +{ + acprintf ( "JLE/JNG REL8\n" ); + if ( (testFlag(SPR, FLAG_ZF)==true) || ((testFlag(SPR, FLAG_SF)!=testFlag(SPR, FLAG_OF))) ) + { + printf ( "Branch taken\n" ); + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jne_jnz_rel8 behavior method. +void ac_behavior( jne_jnz_rel8 ) +{ + acprintf ( " JNE/JNZ REL8\n" ); + if ( testFlag(SPR, FLAG_ZF)==false ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jno_rel8 behavior method. +void ac_behavior( jno_rel8 ) +{ + acprintf ( " JNO REL8\n" ); + if ( testFlag(SPR, FLAG_OF)==false ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jnp_jpo_rel8 behavior method. +void ac_behavior( jnp_jpo_rel8 ) +{ + acprintf ( " JNP/JPO REL8\n" ); + if ( testFlag(SPR, FLAG_PF)==false ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jns_rel8 behavior method. +void ac_behavior( jns_rel8 ) +{ + acprintf ( " JNS REL8\n" ); + if ( testFlag(SPR, FLAG_SF)==false ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jo_rel8 behavior method. +void ac_behavior( jo_rel8 ) +{ + acprintf ( " JO REL8\n" ); + if ( testFlag(SPR, FLAG_OF)==true ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jp_jpe_rel8 behavior method. +void ac_behavior( jp_jpe_rel8 ) +{ + acprintf ( " JP/JPE REL8\n" ); + if ( testFlag(SPR, FLAG_PF)==true ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction js_rel8 behavior method. +void ac_behavior( js_rel8 ) +{ + acprintf ( " JS REL8\n" ); + if ( testFlag(SPR, FLAG_SF)==true ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jmp_rel8 behavior method. +void ac_behavior( jmp_rel8 ) +{ + printf ( "JMP REL8\n" ); + signed char d = data.address8(); + ac_pc+=d; + SPR.write(EIP,(int)ac_pc); +} + +//!Instruction jcxz_jecxz_rel8 behavior method. +void ac_behavior( jcxz_jecxz_rel8 ) +{ + acprintf ( " JECXZ REL8\n" ); + if ( GR.read(ECX)==0x00000000 ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + } +} + +//!Instruction jmp_rel32 behavior method. +void ac_behavior( jmp_rel32 ) +{ + // acprintf ( " JMP REL32\t\t" ); + acprintf("JMP "); acprinti(ac_pc+data.address()); acprintf("\n"); + signed int rel = data.address(); + ac_pc+= rel; + SPR.write(EIP,(int)ac_pc); +} + +//!Instruction jmp_ptr16_32 behavior method. +void ac_behavior( jmp_ptr16_32 ) +{ + acprintf ( " JMP PTR16:32 \n" ); +} + +//!Instruction loop_rel8 behavior method. +void ac_behavior( loop_rel8 ) +{ + acprintf ( " LOOP REL8\n" ); + uint aux = GR.read(ECX); + aux--; + if ( aux > 0x00000000 ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + GR.write(ECX,aux); + } +} + +//!Instruction loope_loopz_rel8 behavior method. +void ac_behavior( loope_loopz_rel8 ) +{ + acprintf ( " LOOPE/LOOPZ REL8\n" ); + uint aux = GR.read(ECX); + aux--; + if ( (aux > 0x00000000) && testFlag(SPR, FLAG_ZF)==true ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + GR.write(ECX,aux); + } +} + +//!Instruction loopne_loopnz_rel8 behavior method. +void ac_behavior( loopne_loopnz_rel8 ) +{ + acprintf ( " LOOPNE/LOOPNZ REL8\n" ); + uint aux = GR.read(ECX); + aux--; + if ( (aux > 0x00000000) && testFlag(SPR, FLAG_ZF)==false ) + { + if ( data.address8()&(1<<7) ) ac_pc-=((~data.address8())+0x01); + else ac_pc+= data.address8(); + GR.write(ECX,aux); + } +} + +//!Instruction call_rel32 behavior method. +void ac_behavior( call_rel32 ) +{ + // acprintf ( "CALL REL32\t\t" ); + push(MEM, GR, (int)ac_pc); + signed int a = data.address(); + acprintf("CALL "); acprinti(ac_pc+a); acprintf("\n"); + ac_pc+= a; + SPR.write(EIP,(int)ac_pc); +} + +//!Instruction call_ptr16_32 behavior method. +void ac_behavior( call_ptr16_32 ) +{ + acprintf ( "CALL PTR16:32 \n" ); +} + +//!Instruction ret_near behavior method. +void ac_behavior( ret_near ) +{ + acprintf ( "RET\n" ); + ac_pc = pop(MEM, GR); + SPR.write(EIP,(int)ac_pc); +} + +//!Instruction ret_far behavior method. +void ac_behavior( ret_far ) +{ + acprintf ( "RET\n" ); + ac_pc = pop(MEM, GR); + SPR.write(EIP,(int)ac_pc); +} + +//!Instruction ret_near_imm16 behavior method. +void ac_behavior( ret_near_imm16 ) +{ + acprintf ( "RET IMM16 \n" ); +} + +//!Instruction ret_far_imm16 behavior method. +void ac_behavior( ret_far_imm16 ) +{ + acprintf ( "RET IMM16 \n" ); +} + +//!Instruction int_3 behavior method. +void ac_behavior( int_3 ) +{ + acprintf ( "INT 3 \n" ); +} + +//!Instruction int_imm8 behavior method. +void ac_behavior( int_imm8 ) +{ + acprintf ( "INT IMM8 \n" ); +} + +//!Instruction into behavior method. +void ac_behavior( into ) +{ + acprintf ( "INTO \n" ); +} + +//!Instruction bound_r32_m32_32 behavior method. +void ac_behavior( bound_r32_m32_32 ) +{ + acprintf ( "BOUND R32, M32&32 \n" ); + signed int r = GR.read(data.reg1()); + signed int lb = MEM.read(data.address()); + signed int ub = MEM.read(data.address()+4); + if ( (rub) ) + ; // Exception #BR +} + +//!Instruction enter_imm16_0_1_imm8 behavior method. +void ac_behavior( enter_imm16_0_1_imm8 ) +{ + acprintf ( "ENTER IMM16, IMM8 \n" ); +} + +//!Instruction lss_r32_m16_32 behavior method. +void ac_behavior( lss_r32_m16_32 ) +{ + acprintf ( "LSS R32, M16:32\n" ); + unsigned char b0 = MEM.read_byte(data.address()); + unsigned char b1 = MEM.read_byte(data.address()+1); + uint offset = readMemory(MEM, data.address()+2); + uint ds_data = (b1<<8) + b0; + writeSRegister(SR, SS, ds_data); + writeRegister(GR, data.reg1(), offset); +} + +//!Instruction lfs_r32_m16_32 behavior method. +void ac_behavior( lfs_r32_m16_32 ) +{ + acprintf ( "LFS R32,M16:32\n" ); + unsigned char b0 = MEM.read_byte(data.address()); + unsigned char b1 = MEM.read_byte(data.address()+1); + uint offset = readMemory(MEM, data.address()+2); + uint ds_data = (b1<<8) + b0; + writeSRegister(SR, FS, ds_data); + writeRegister(GR, data.reg1(), offset); +} + +//!Instruction lgs_r32_m16_32 behavior method. +void ac_behavior( lgs_r32_m16_32 ) +{ + acprintf ( "LGS R32,M16:32\n" ); + unsigned char b0 = MEM.read_byte(data.address()); + unsigned char b1 = MEM.read_byte(data.address()+1); + uint offset = readMemory(MEM, data.address()+2); + uint ds_data = (b1<<8) + b0; + writeSRegister(SR, GS, ds_data); + writeRegister(GR, data.reg1(), offset); +} + +//!Instruction cmov_a_nbe_r32_rm32 behavior method. +void ac_behavior( cmov_a_nbe_r32_rm32 ) +{ + acprintf ( "CMOVA/CMOVNBE R32, RM32\n" ); + if ( (testFlag(SPR, FLAG_CF)==false) && (testFlag(SPR, FLAG_ZF)==false) ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_ae_nb_nc_r32_rm32 behavior method. +void ac_behavior( cmov_ae_nb_nc_r32_rm32 ) +{ + acprintf ( "CMOVAE/CMOVNB/CMOVNC R32, RM32\n" ); + if ( testFlag(SPR, FLAG_CF)==false ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_b_c_nae_r32_rm32 behavior method. +void ac_behavior( cmov_b_c_nae_r32_rm32 ) +{ + acprintf ( "CMOVB/CMOVC/CMOVNAE R32, RM32\n" ); + if ( testFlag(SPR, FLAG_CF)==true ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_be_na_r32_rm32 behavior method. +void ac_behavior( cmov_be_na_r32_rm32 ) +{ + acprintf ( "CMOVBE/CMOVNA R32, RM32\n" ); + if ( testFlag(SPR, FLAG_CF)==true && testFlag(SPR, FLAG_ZF)==true ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_e_z_r32_rm32 behavior method. +void ac_behavior( cmov_e_z_r32_rm32 ) +{ + acprintf ( "CMOVE/CMOVZ R32, RM32\n" ); + if ( testFlag(SPR, FLAG_ZF)==true ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_g_nle_r32_rm32 behavior method. +void ac_behavior( cmov_g_nle_r32_rm32 ) +{ + acprintf ( "CMOVG/CMOVNLE R32, RM32\n" ); + if ( testFlag(SPR, FLAG_ZF)==false && (testFlag(SPR, FLAG_SF)==testFlag(SPR, FLAG_OF)) ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_ge_nl_r32_rm32 behavior method. +void ac_behavior( cmov_ge_nl_r32_rm32 ) +{ + acprintf ( "CMOVGE/CMOVNL R32, RM32\n" ); + if ( testFlag(SPR, FLAG_SF)==testFlag(SPR, FLAG_OF) ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_l_nge_r32_rm32 behavior method. +void ac_behavior( cmov_l_nge_r32_rm32 ) +{ + acprintf ( "CMOVL/CMOVNGE R32, RM32\n" ); + if ( testFlag(SPR, FLAG_SF)!=testFlag(SPR, FLAG_OF) ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_le_ng_r32_rm32 behavior method. +void ac_behavior( cmov_le_ng_r32_rm32 ) +{ + acprintf ( "CMOVLE/CMOVNG R32, RM32\n" ); + if ( testFlag(SPR, FLAG_ZF)==true || (testFlag(SPR, FLAG_SF)!=testFlag(SPR, FLAG_OF)) ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_ne_nz_r32_rm32 behavior method. +void ac_behavior( cmov_ne_nz_r32_rm32 ) +{ + acprintf ( "CMOVNE/CMOVNZ R32, RM32\n" ); + if ( testFlag(SPR, FLAG_ZF)==false ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_no_r32_rm32 behavior method. +void ac_behavior( cmov_no_r32_rm32 ) +{ + acprintf ( "CMOVNO R32, RM32\n" ); + if ( testFlag(SPR, FLAG_OF)==false ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_np_po_r32_rm32 behavior method. +void ac_behavior( cmov_np_po_r32_rm32 ) +{ + acprintf ( "CMOVNP/CMOVPO R32, RM32\n" ); + if ( testFlag(SPR, FLAG_PF)==false ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_ns_r32_rm32 behavior method. +void ac_behavior( cmov_ns_r32_rm32 ) +{ + acprintf ( "CMOVNS R32, RM32\n" ); + if ( testFlag(SPR, FLAG_SF)==false ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_o_r32_rm32 behavior method. +void ac_behavior( cmov_o_r32_rm32 ) +{ + acprintf ( "CMOVO R32, RM32\n" ); + if ( testFlag(SPR, FLAG_OF)==true ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_p_pe_r32_rm32 behavior method. +void ac_behavior( cmov_p_pe_r32_rm32 ) +{ + acprintf ( "CMOVP/CMOVPE R32, RM32\n" ); + if ( testFlag(SPR, FLAG_PF)==true ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction cmov_s_r32_rm32 behavior method. +void ac_behavior( cmov_s_r32_rm32 ) +{ + acprintf ( "CMOVS R32, RM32\n" ); + if ( testFlag(SPR, FLAG_SF)==true ) + { + if ( data.usesMemory() ) writeRegister(GR, data.reg1(),readMemory(MEM, data.address())); + else writeRegister(GR, data.reg1(), readRegister(GR, data.reg2())); + } +} + +//!Instruction xadd_rm32_r32 behavior method. +void ac_behavior( xadd_rm32_r32 ) +{ + acprintf ( "XADD RM32,R32\n" ); + uint op1, op2, aux; + if ( data.usesMemory() ) + { + op1 = readMemory(MEM, data.address()); + op2 = readRegister(GR, data.reg1()); + writeRegister(GR, data.reg1(),op1); + aux = op1 + op2; + writeMemory(MEM, data.address(),aux); + } + else + { + op1 = readRegister(GR, data.reg2()); + op2 = readRegister(GR, data.reg1()); + writeRegister(GR, data.reg1(),op1); + aux = op1 + op2; + writeRegister(GR, data.reg2(),aux); + } + checkFlags(SPR, OPER_ADD,op1,op2,aux,FLAG_ALL); +} + +//!Instruction cmpxchg_rm32_r32 behavior method. +void ac_behavior( cmpxchg_rm32_r32 ) +{ + acprintf ( " CMPXCHG RM32, R32\n" ); + uint op1, op2, aux; + if ( data.usesMemory() ) + { + op1 = readMemory(MEM, data.address()); + op2 = readRegister(GR, data.reg1()); + aux = op1 + (~readRegister(GR, EAX)) + 0x01; + if ( readRegister(GR, EAX)==op1 ) + writeMemory(MEM, data.address(), op2); + else + writeRegister(GR, EAX,op1); + } + else + { + op1 = readRegister(GR, data.reg2()); + op2 = readRegister(GR, data.reg1()); + aux = op1 + (~readRegister(GR, EAX)) + 0x01; + if ( readRegister(GR, EAX)==op1 ) + writeRegister(GR, data.reg2(),op2); + else + writeRegister(GR, EAX,op1); + } + checkFlags(SPR, OPER_SUB,op1,GR.read(EAX),aux,FLAG_ALL); +} + +//!Instruction cmpxchg8b_m64 behavior method. +void ac_behavior( cmpxchg8b_m64 ) +{ + acprintf ( "CMPXCHG8B M64\n" ); + unsigned long long dest, edxeax, aux; + dest = (((unsigned long long)readMemory(MEM, data.address()))<<32)+readMemory(MEM, data.address()+4); + edxeax = (((unsigned long long)readRegister(GR, EDX))<<32) + readRegister(GR, EAX); + aux = dest + (~edxeax) + 0x01; + if ( edxeax == dest ) + { + writeMemory(MEM, data.address(), readRegister(GR, EBX)); + writeMemory(MEM, data.address()+4, readRegister(GR, ECX)); + setFlag(SPR, FLAG_ZF); + } + else + { + writeRegister(GR, EDX, (dest>>32)); + writeRegister(GR, EAX, dest&0xFFFFFFFF); + resetFlag(SPR, FLAG_ZF); + } +} + +//!Instruction movsx_r32_rm8 behavior method. +void ac_behavior( movsx_r32_rm8 ) +{ + acprintf ( "MOVSX R32, RM8\n" ); + signed char op; + signed int res; + if ( data.usesMemory() ) + { + op = MEM.read_byte(data.address()); + res = op; + } + else + { + op = readRegister8(GR, data.reg2()); + res = op; + } + writeRegister(GR, data.reg1(),res); +} + +//!Instruction movsx_r32_rm16 behavior method. +void ac_behavior( movsx_r32_rm16 ) +{ + // acprintf ( "MOVSX R32, RM16\n" ); + printf ( "MOVSX " ); + if ( OperandSize == OPERAND_SIZE16 ) printf ( "%s, ", reg_str16[data.reg1()] ); + else printf ( "%s, ", reg_str[data.reg1()] ); + signed short op; + signed int res; + if ( data.usesMemory() ) op = MEM.read_half(data.address()); + else op = GR.read(data.reg2()); + if ( data.usesMemory() ) printf ( "[0x%08X]\n", data.address() ); + else + { + if ( OperandSize == OPERAND_SIZE16 ) printf ( "%s\n", reg_str16[data.reg2()] ); + else printf ( "%s\n", reg_str[data.reg2()] ); + } + res = op; + writeRegister(GR, data.reg1(),res); +} + +//!Instruction movzx_r32_rm8 behavior method. +void ac_behavior( movzx_r32_rm8 ) +{ + acprintf ( "MOVZX R32, RM8\n" ); + unsigned char op; + if ( data.usesMemory() ) op = MEM.read_byte(data.address()); + else op = readRegister8(GR, data.reg2()); + writeRegister(GR, data.reg1(),op); +} + +//!Instruction movzx_r32_rm16 behavior method. +void ac_behavior( movzx_r32_rm16 ) +{ + acprintf ( "MOVZX R32, RM16\n" ); + unsigned short op; + if ( data.usesMemory() ) op = MEM.read_half(data.address()); + else op = (readRegister(GR, data.reg2())&MASK_16BITS); + writeRegister(GR, data.reg1(),op); +} + +//!Instruction shrd_rm32_r32_imm8 behavior method. +void ac_behavior( shrd_rm32_r32_imm8 ) +{ + printf ( "SHRD RM32, R32, IMM8\n" ); + if ( OperandSize == OPERAND_SIZE16 ) + { + printf ( "NOT IMPLEMENTED!\n" ); + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + signed char count = data.immediate8(SPR, ac_pc); + unsigned int op1 = dataManager.getMemOrReg2(MEM, GR); + unsigned long long op2 = dataManager.getReg1(GR); + unsigned long long op = (op2<<32)|(op1); + unsigned long long res = op >> count; + dataManager.setMemOrReg2(MEM, GR, res); + dataManager.setReg1(GR, res>>31); + if ( count > 0 ) checkFlags(SPR, OPER_NONE,0,0,res,FLAG_ALL); + if ( count > 0 ) writeFlag(SPR, FLAG_CF, (op>>(count-1))&0x01); + if ( count == 1 ) writeFlag(SPR, FLAG_OF, MSB32(op1) != MSB32(res)); + } +} + +//!Instruction shrd_rm32_r32_CL behavior method. +void ac_behavior( shrd_rm32_r32_CL ) +{ + acprintf ( "SHRD RM32, R32, CL \n" ); +} + +//!Instruction shld_rm32_r32_imm8 behavior method. +void ac_behavior( shld_rm32_r32_imm8 ) +{ + printf ( "SHLD RM32, R32, IMM8\n" ); + if ( OperandSize == OPERAND_SIZE16 ) + { + printf ( "NOT IMPLEMENTED!\n" ); + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + signed char count = data.immediate8(SPR, ac_pc); + unsigned long long op1 =dataManager.getMemOrReg2(MEM, GR); + unsigned int op2 = dataManager.getReg1(GR); + unsigned long long op = (op1<<32)|(op2); + unsigned long long res = op << count; + dataManager.setMemOrReg2(MEM, GR, res>>32); + dataManager.setReg1(GR, res>>1); + if ( count > 0 ) checkFlags(SPR, OPER_NONE,0,0,res,FLAG_ALL); + if ( count > 0 ) writeFlag(SPR, FLAG_CF, MSB32(op<<(count-1)) ); + if ( count == 1 ) writeFlag(SPR, FLAG_OF, MSB32(op1) != MSB32(res)); + } +} + +//!Instruction shld_rm32_r32_CL behavior method. +void ac_behavior( shld_rm32_r32_CL ) +{ + acprintf ( "SHLD RM32, R32, CL \n" ); +} + +//!Instruction bt_rm32_r32 behavior method. +void ac_behavior( bt_rm32_r32 ) +{ + acprintf ( " BT RM32,R32\n" ); + if ( data.usesMemory() ) + { + if ( testMemBit(MEM, data.address(), data.reg1()) ) setFlag(SPR, FLAG_CF); + else resetFlag ( SPR, FLAG_CF ); + } + else + { + if ( testBit ( readRegister(GR, data.reg2()), readRegister(GR, data.reg1()) ) ) setFlag(SPR, FLAG_CF); + else resetFlag ( SPR, FLAG_CF ); + } +} + +//!Instruction bt_rm32_imm8 behavior method. +void ac_behavior( bt_rm32_imm8 ) +{ + acprintf ( "BT RM32, IMM8\n" ); + signed char i = data.immediate8(SPR, ac_pc); + signed int op = i; + if ( data.usesMemory() ) + { + if ( testMemBit(MEM, data.address(), op) ) setFlag(SPR, FLAG_CF); + else resetFlag ( SPR, FLAG_CF ); + } + else + { + if ( testBit ( readRegister(GR, data.reg2()), op ) ) setFlag(SPR, FLAG_CF); + else resetFlag ( SPR, FLAG_CF ); + } +} + +//!Instruction bts_rm32_r32 behavior method. +void ac_behavior( bts_rm32_r32 ) +{ + uint target; + acprintf ( "BTS RM32,R32\n" ); + if ( data.usesMemory() ) + { + if ( testMemBit(MEM, data.address(),GR.read(data.reg1())) ) setFlag(SPR, FLAG_CF ); + else resetFlag ( SPR, FLAG_CF ); + setMemBit(MEM, data.address(), GR.read(data.reg1()) ); + } + else + { + target = GR.read(data.reg2()); + if ( testBit ( target, GR.read(data.reg1()) ) ) setFlag(SPR, FLAG_CF); + else resetFlag ( SPR, FLAG_CF ); + setBit ( &target, GR.read(data.reg1()) ); + GR.write(data.reg2(),target); + } +} + +//!Instruction btr_rm32_r32 behavior method. +void ac_behavior( btr_rm32_r32 ) +{ + uint target; + acprintf ( "BTR RM32,R32\n" ); + if ( data.usesMemory() ) + { + if ( testMemBit(MEM, data.address(),GR.read(data.reg1())) ) setFlag(SPR, FLAG_CF ); + else resetFlag ( SPR, FLAG_CF ); + resetMemBit(MEM, data.address(), GR.read(data.reg1()) ); + } + else + { + target = GR.read(data.reg2()); + if ( testBit ( target, GR.read(data.reg1()) ) ) setFlag(SPR, FLAG_CF); + else resetFlag ( SPR, FLAG_CF ); + resetBit ( &target, GR.read(data.reg1()) ); + GR.write(data.reg2(),target); + } +} + +//!Instruction btc_rm32_r32 behavior method. +void ac_behavior( btc_rm32_r32 ) +{ + uint target; + acprintf ( "BTC RM32,R32\n" ); + if ( data.usesMemory() ) + { + if ( testMemBit(MEM, data.address(),GR.read(data.reg1())) ) setFlag(SPR, FLAG_CF ); + else resetFlag ( SPR, FLAG_CF ); + compMemBit(MEM, data.address(), GR.read(data.reg1()) ); + } + else + { + target = GR.read(data.reg2()); + if ( testBit ( target, GR.read(data.reg1()) ) ) setFlag(SPR, FLAG_CF); + else resetFlag ( SPR, FLAG_CF ); + compBit ( &target, GR.read(data.reg1()) ); + GR.write(data.reg2(),target); + } +} + +//!Instruction bsf_r32_rm32 behavior method. +void ac_behavior( bsf_r32_rm32 ) +{ + acprintf ( "BSF R32, RM32\n" ); + uint source, index=32; + if ( data.usesMemory() ) source = readMemory(MEM, data.address()); + else source = readRegister(GR, data.reg2()); + for ( uint i=0; i<32; i++ ) + if (testBit(source,i)) index = i; + if ( index > 31 ) setFlag(SPR, FLAG_ZF ); + else resetFlag ( SPR, FLAG_ZF ); + writeRegister(GR, data.reg1(),index); +} + +//!Instruction bsr_r32_rm32 behavior method. +void ac_behavior( bsr_r32_rm32 ) +{ + acprintf ( "BSR R32, RM32\n" ); + uint source, index = 32; + if ( data.usesMemory() ) source = readMemory(MEM, data.address()); + else source = readRegister(GR, data.reg2()); + for ( int i=31; i>=0; i-- ) + if ( testBit(source,i)) { + index = i; + break; + } + if ( index < 31 ) setFlag(SPR, FLAG_ZF ); + else resetFlag ( SPR, FLAG_ZF ); + writeRegister(GR, data.reg1(),index); +} + + +//!Instruction seta_setnbe_rm8 behavior method. +void ac_behavior( seta_setnbe_rm8 ) +{ + acprintf ( " SETA/SETNBE RM8 \n" ); +} + +//!Instruction setae_setnb_setnc_rm8 behavior method. +void ac_behavior( setae_setnb_setnc_rm8 ) +{ + acprintf ( "SETAE/SETNB/SETNC RM8\n" ); + if ( testFlag(SPR, FLAG_CF)==false ) + { + if ( data.usesMemory() ) MEM.write_byte(data.address(),1); + else writeRegister8(GR, data.reg2(),1); + } + else + { + if ( data.usesMemory() ) MEM.write_byte(data.address(),0); + else writeRegister8(GR, data.reg2(),0); + } +} + +//!Instruction setb_setc_setnae_rm8 behavior method. +void ac_behavior( setb_setc_setnae_rm8 ) +{ + acprintf ( " SETB/SETC/SETNAE RM8 \n" ); +} + +//!Instruction setbe_setna_rm8 behavior method. +void ac_behavior( setbe_setna_rm8 ) +{ + acprintf ( " SETBE/SETNA RM8 \n" ); +} + +//!Instruction sete_setz_rm8 behavior method. +void ac_behavior( sete_setz_rm8 ) +{ + acprintf ( " SETE/SETZ RM8 \n" ); +} + +//!Instruction setg_setnle_rm8 behavior method. +void ac_behavior( setg_setnle_rm8 ) +{ + acprintf ( " SETG/SETNLE RM8 \n" ); +} + +//!Instruction setge_setnl_rm8 behavior method. +void ac_behavior( setge_setnl_rm8 ) +{ + acprintf ( " SETGE/SETNL RM8 \n" ); +} + +//!Instruction setl_setnge_rm8 behavior method. +void ac_behavior( setl_setnge_rm8 ) +{ + acprintf ( " SETL/SETNGE RM8 \n" ); +} + +//!Instruction setle_setng_rm8 behavior method. +void ac_behavior( setle_setng_rm8 ) +{ + acprintf ( " SETLE/SETNG RM8 \n" ); +} + +//!Instruction setne_setnz_rm8 behavior method. +void ac_behavior( setne_setnz_rm8 ) +{ + acprintf ( " SETNE/SETNZ RM8 \n" ); +} + +//!Instruction setno_rm8 behavior method. +void ac_behavior( setno_rm8 ) +{ + acprintf ( " SETNO RM8 \n" ); +} + +//!Instruction setnp_setpo_rm8 behavior method. +void ac_behavior( setnp_setpo_rm8 ) +{ + acprintf ( " SETNP/SETPO RM8 \n" ); +} + +//!Instruction setns_rm8 behavior method. +void ac_behavior( setns_rm8 ) +{ + acprintf ( " SETNS RM8 \n" ); +} + +//!Instruction seto_rm8 behavior method. +void ac_behavior( seto_rm8 ) +{ + acprintf ( " SETO RM8 \n" ); +} + +//!Instruction setp_setpe_rm8 behavior method. +void ac_behavior( setp_setpe_rm8 ) +{ + acprintf ( " SETP/SETPE RM8 \n" ); +} + +//!Instruction sets_rm8 behavior method. +void ac_behavior( sets_rm8 ) +{ + acprintf ( " SETS RM8 \n" ); +} + +//!Instruction ja_jnbe_rel16_32 behavior method. +void ac_behavior( ja_jnbe_rel16_32 ) +{ + acprintf ( " JA/JNBE REL32\n" ); + if ( testFlag(SPR, FLAG_CF)==false && testFlag(SPR, FLAG_ZF)==false ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } +} + +//!Instruction jae_jnb_jnc_rel16_32 behavior method. +void ac_behavior( jae_jnb_jnc_rel16_32 ) +{ + acprintf ( " JAE/JNB/JNC REL32\n" ); + if ( testFlag(SPR, FLAG_CF)==false ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } +} + + //!Instruction jb_jc_jnae_rel16_32 behavior method. + void ac_behavior( jb_jc_jnae_rel16_32 ) + { + acprintf ( " JB/JC/JNAE REL32\n" ); + if ( testFlag(SPR, FLAG_CF)==true ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } + } + + //!Instruction jbe_jna_rel16_32 behavior method. + void ac_behavior( jbe_jna_rel16_32 ) + { + acprintf ( " JBE/JNA REL32\n" ); + if ( testFlag(SPR, FLAG_CF)==true || testFlag(SPR, FLAG_ZF)==true ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } + } + + //!Instruction je_jz_rel16_32 behavior method. + void ac_behavior( je_jz_rel16_32 ) + { + acprintf ( " JE/JZ REL32\n" ); + if ( testFlag(SPR, FLAG_ZF)==true ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } + } + + //!Instruction jg_jnle_rel16_32 behavior method. + void ac_behavior( jg_jnle_rel16_32 ) + { + acprintf ( " JG/JNLE REL32\n" ); + if ( testFlag(SPR, FLAG_ZF)==false && (testFlag(SPR, FLAG_SF)==testFlag(SPR, FLAG_OF)) ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } + } + + //!Instruction jge_jnl_rel16_32 behavior method. + void ac_behavior( jge_jnl_rel16_32 ) + { + acprintf ( " JGE/JNL REL32\n" ); + if ( testFlag(SPR, FLAG_SF)==testFlag(SPR, FLAG_OF) ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } + } + + //!Instruction jl_jnge_rel16_32 behavior method. + void ac_behavior( jl_jnge_rel16_32 ) + { + acprintf ( " JL/JNGE REL32\n" ); + if ( testFlag(SPR, FLAG_SF)!=testFlag(SPR, FLAG_OF) ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } + } + + //!Instruction jle_jng_rel16_32 behavior method. + void ac_behavior( jle_jng_rel16_32 ) + { + acprintf ( " JLE/JNG REL32\n" ); + if ( testFlag(SPR, FLAG_ZF)==true || (testFlag(SPR, FLAG_SF)!=testFlag(SPR, FLAG_OF)) ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } + } + + //!Instruction jne_jnz_rel16_32 behavior method. + void ac_behavior( jne_jnz_rel16_32 ) + { + acprintf ( " JNE/JNZ REL32\n" ); + if ( testFlag(SPR, FLAG_ZF)==false ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } + } + + //!Instruction jno_rel16_32 behavior method. + void ac_behavior( jno_rel16_32 ) + { + acprintf ( " JNO REL32\n" ); + if ( testFlag(SPR, FLAG_OF)==false ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } + } + + //!Instruction jnp_jpo_rel16_32 behavior method. + void ac_behavior( jnp_jpo_rel16_32 ) + { + acprintf ( " JNP/JPO REL32\n" ); + if ( testFlag(SPR, FLAG_PF)==false ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } + } + + //!Instruction jns_rel16_32 behavior method. +void ac_behavior( jns_rel16_32 ) +{ + acprintf ( " JNS REL32\n" ); + if ( testFlag(SPR, FLAG_SF)==false ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } +} + +//!Instruction jo_rel16_32 behavior method. +void ac_behavior( jo_rel16_32 ) +{ + acprintf ( " JO REL32\n" ); + if ( testFlag(SPR, FLAG_OF)==true ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } +} + +//!Instruction jp_jpe_rel16_32 behavior method. +void ac_behavior( jp_jpe_rel16_32 ) +{ + acprintf ( " JP/JPE REL32\n" ); + if ( testFlag(SPR, FLAG_PF)==true ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + } +} + +//!Instruction js_rel16_32 behavior method. +void ac_behavior( js_rel16_32 ) +{ + acprintf ( " JS REL32\n" ); + if ( testFlag(SPR, FLAG_SF)==true ) + { + if ( data.address()&(1<<31) ) ac_pc-=((~data.address())+0x01); + else ac_pc+= data.address(); + SPR.write(EIP,(int)ac_pc); + } +} + +//!Instruction bts_rm32_imm8 behavior method +void ac_behavior( bts_rm32_imm8 ) +{ + acprintf ( " BTS RM32, IMM8\n" ); + signed char i = data.immediate8(SPR, ac_pc); + int op = i; + uint target; + acprintf ( " BTS RM32,R32\n" ); + if ( data.usesMemory() ) + { + if ( testMemBit(MEM, data.address(),op) ) setFlag(SPR, FLAG_CF ); + else resetFlag ( SPR, FLAG_CF ); + setMemBit(MEM, data.address(), op ); + } + else + { + target = GR.read(data.reg2()); + if ( testBit ( target, op ) ) setFlag(SPR, FLAG_CF); + else resetFlag ( SPR, FLAG_CF ); + setBit ( &target, op ); + GR.write(data.reg2(),target); + } +} + +//!Instruction btr_rm32_imm8 behavior method +void ac_behavior( btr_rm32_imm8 ) +{ + acprintf ( " BTR RM32, IMM8\n" ); + signed char i = data.immediate8(SPR, ac_pc); + int op = i; + uint target; + if ( data.usesMemory() ) + { + if ( testMemBit(MEM, data.address(),op) ) setFlag(SPR, FLAG_CF ); + else resetFlag ( SPR, FLAG_CF ); + resetMemBit(MEM, data.address(), op ); + } + else + { + target = GR.read(data.reg2()); + if ( testBit ( target, op ) ) setFlag(SPR, FLAG_CF); + else resetFlag ( SPR, FLAG_CF ); + resetBit ( &target, op ); + GR.write(data.reg2(),target); + } +} + +//!Instruction btc_rm32_imm8 behavior method +void ac_behavior( btc_rm32_imm8 ) +{ + acprintf ( " BTC RM32, IMM8\n" ); + signed char i =data.immediate8(SPR, ac_pc); + int op = i; + uint target; + if ( data.usesMemory() ) + { + if ( testMemBit(MEM, data.address(),op) ) setFlag(SPR, FLAG_CF ); + else resetFlag ( SPR, FLAG_CF ); + compMemBit(MEM, data.address(), op ); + } + else + { + target = GR.read(data.reg2()); + if ( testBit ( target, op ) ) setFlag(SPR, FLAG_CF); + else resetFlag ( SPR, FLAG_CF ); + compBit ( &target, op ); + GR.write(data.reg2(),target); + } +} + +//!Instruction inc_rm32 behavior method +void ac_behavior( inc_rm32 ) +{ + acprintf ( "INC RM32\n" ); + uint op, res; + op = dataManager.getMemOrReg2(MEM, GR); + res = op + 1; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_ADD,op,1,res,FLAG_ALL&(~FLAG_CF)); +} + +//!Instruction dec_rm32 behavior method +void ac_behavior( dec_rm32 ) +{ + acprintf ( "DEC RM32\n" ); + if ( OperandSize == OPERAND_SIZE16 ) + { + ushort op1, op2, res; + op1 = dataManager.getMemOrReg2(MEM, GR); + op2 = 1; + res = op1 - op2; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL&(~FLAG_CF)); + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + uint op1, op2, res; + op1 = dataManager.getMemOrReg2(MEM, GR); + op2 = 1; + res = op1 - op2; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL&(~FLAG_CF)); + } +} + +//!Instruction jmp_rm32 behavior method +void ac_behavior( jmp_rm32 ) +{ + acprintf ( " JMP RM32\n" ); + if (data.usesMemory()) ac_pc=MEM.read(data.address()); + else ac_pc=GR.read(data.reg2()); + SPR.write(EIP,(int)ac_pc); +} + +//!Instruction jmp_m16_32 behavior method +void ac_behavior( jmp_m16_32 ) +{ + acprintf ( " JMP M16:32 \n" ); +} + +//!Instruction call_rm32 behavior method +void ac_behavior( call_rm32 ) +{ + acprintf ( " CALL RM32\n" ); + push(MEM, GR, ac_pc); + if ( data.usesMemory() ) ac_pc=MEM.read(data.address()); + else ac_pc=GR.read(data.reg2()); + SPR.write(EIP,(int)ac_pc); +} + +//!Instruction call_m16_32 behavior method +void ac_behavior( call_m16_32 ) +{ + acprintf ( " CALL M16:32 \n" ); +} + +//!Instruction sub_rm32_imm32 behavior method +void ac_behavior( sub_rm32_imm32 ) +{ + // acprintf ( "SUB RM32, IMM32\t\t" ); + uint op1, op2, aux; + op1 = data.immediate(SPR, ac_pc); + if ( data.usesMemory() ) op2 = MEM.read(data.address()); + else op2 = GR.read(data.reg2()); + aux = op2 - op1; + if ( data.usesMemory() ) MEM.write(data.address(),aux); + else GR.write(data.reg2(),aux); + if ( data.usesMemory() ) acprintfmi ( "SUB", data.address(), op1 ); + else acprintfri ( "SUB", data.reg2(), op1 ); + checkFlags(SPR, OPER_SUB,op2,op1,aux,FLAG_ALL); +} + +//!Instruction sub_rm32_imm8 behavior method +void ac_behavior( sub_rm32_imm8 ) +{ + // acprintf ( "SUB RM32, IMM8\t\t" ); + signed char i = data.immediate8(SPR, ac_pc); + signed int j = i; + uint op1, op2, aux; + if ( data.usesMemory() ) acprintfmi ( "SUB", data.address(), j ); + else acprintfri ( "SUB", data.reg2(), j ); + op1 = (unsigned)j; + if ( data.usesMemory() ) op2 = MEM.read(data.address()); + else op2 = GR.read(data.reg2()); + aux = op2 - op1; + if ( data.usesMemory() ) MEM.write(data.address(),aux); + else GR.write(data.reg2(),aux); + checkFlags(SPR, OPER_SUB,op2,op1,aux,FLAG_ALL); +} + +//!Instruction sbb_rm32_imm32 behavior method +void ac_behavior( sbb_rm32_imm32 ) +{ + acprintf ( " SBB RM32, IMM32\n" ); + uint op1, op2, aux; + op1 = data.immediate(SPR, ac_pc) + testFlag(SPR, FLAG_CF); + if ( data.usesMemory() ) op2 = MEM.read(data.address()); + else op2 = GR.read(data.reg2()); + aux = op2 - op1; + if ( data.usesMemory() ) MEM.write(data.address(),aux); + else GR.write(data.reg2(),aux); + checkFlags(SPR, OPER_SUB,op2,op1,aux,FLAG_ALL); +} + +//!Instruction sbb_rm32_imm8 behavior method +void ac_behavior( sbb_rm32_imm8 ) +{ + acprintf ( " SBB RM32, IMM8\n" ); + signed char i = data.immediate8(SPR, ac_pc); + signed int j = i; + uint op1, op2, aux; + op1 = (unsigned)j; + if ( data.usesMemory() ) op2 = MEM.read(data.address()); + else op2 = GR.read(data.reg2()); + op1+= testFlag(SPR, FLAG_CF); + aux = op2 - op1; + if ( data.usesMemory() ) MEM.write(data.address(),aux); + else GR.write(data.reg2(),aux); + checkFlags(SPR, OPER_SUB,op2,op1,aux,FLAG_ALL); +} + +//!Instruction adc_rm32_imm32 behavior method +void ac_behavior( adc_rm32_imm32 ) +{ + acprintf ( " ADC RM32, IMM32\n" ); + uint op1, op2, aux; + op1 = data.immediate(SPR, ac_pc) + testFlag(SPR, FLAG_CF); + if ( data.usesMemory() ) op2 = MEM.read(data.address()); + else op2 = GR.read(data.reg2()); + aux = op1 + op2; + if ( data.usesMemory() ) MEM.write(data.address(),aux); + else GR.write(data.reg2(),aux); + checkFlags(SPR, OPER_ADD,op1,op2,aux,FLAG_ALL); +} + + //!Instruction adc_rm32_imm8 behavior method + void ac_behavior( adc_rm32_imm8 ) + { + acprintf ( "ADC RM32, IMM8\n" ); + signed char i = data.immediate8(SPR, ac_pc); + signed int aux = i; + uint op1, op2, res; + op1 = aux + testFlag(SPR, FLAG_CF); + op2 = dataManager.getMemOrReg2(MEM, GR); + res = op1 + op2; + dataManager.setMemOrReg2(MEM, GR, res); + checkFlags(SPR, OPER_ADD,op1,op2,aux,FLAG_ALL); + } + +//!Instruction cmp_rm32_imm32 behavior method +void ac_behavior( cmp_rm32_imm32 ) +{ + acprintf ( " CMP RM32, IMM32\n" ); + signed int op1, op2, aux; + op1 = data.immediate(SPR, ac_pc); + if ( data.usesMemory() ) op2 = MEM.read(data.address()); + else op2 = GR.read(data.reg2()); + aux = op1-op2; + checkFlags(SPR, OPER_SUB,op1,op2,aux,FLAG_ALL); +} + +//!Instruction cmp_rm32_imm8 behavior method +void ac_behavior( cmp_rm32_imm8 ) +{ + acprintf ( "CMP RM32, IMM8\n" ); + signed char i = data.immediate8(SPR, ac_pc); + signed int op1 = dataManager.getMemOrReg2(MEM, GR); + signed int op2 = i; + signed int res = op1 - op2; + checkFlags(SPR, OPER_SUB,op1,op2,res,FLAG_ALL); +} + +//!Instruction and_rm32_imm32 behavior method +void ac_behavior( and_rm32_imm32 ) +{ + acprintf ( "AND RM32, IMM32\n" ); + uint op1, op2, res; + op1 = dataManager.getImmediate(SPR, ac_pc); + op2 = dataManager.getMemOrReg2(MEM, GR); + res = op1&op2; + dataManager.setMemOrReg2(MEM, GR, res); + resetFlag(SPR, FLAG_CF); + resetFlag(SPR, FLAG_OF); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_SF|FLAG_ZF|FLAG_PF); +} + +//!Instruction and_rm32_imm8 behavior method +void ac_behavior( and_rm32_imm8 ) +{ + acprintf ( "AND RM32, IMM8\n" ); + signed char i = data.immediate8(SPR, ac_pc); + signed int aux = i; + uint op1, op2, res; + op1 = aux; + op2 = dataManager.getMemOrReg2(MEM, GR); + res = op1&op2; + dataManager.setMemOrReg2(MEM, GR, res); + resetFlag(SPR, FLAG_CF); + resetFlag(SPR, FLAG_OF); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_SF|FLAG_ZF|FLAG_PF); +} + +//!Instruction or_rm32_imm32 behavior method +void ac_behavior( or_rm32_imm32 ) +{ + acprintf ( "OR RM32, IMM32\n" ); + uint op1, op2, res; + op1 = dataManager.getImmediate(SPR, ac_pc); + op2 = dataManager.getMemOrReg2(MEM, GR); + res = op1|op2; + dataManager.setMemOrReg2(MEM, GR, res); + resetFlag(SPR, FLAG_CF); + resetFlag(SPR, FLAG_OF); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_SF|FLAG_ZF|FLAG_PF); +} + +//!Instruction or_rm32_imm8 behavior method +void ac_behavior( or_rm32_imm8 ) +{ + acprintf ( "OR RM32, IMM8\n" ); + signed char i = data.immediate8(SPR, ac_pc); + signed int aux = i; + uint op1, op2, res; + op1 = aux; + op2 = dataManager.getMemOrReg2(MEM, GR); + res = op1|op2; + dataManager.setMemOrReg2(MEM, GR, res); + resetFlag(SPR, FLAG_CF); + resetFlag(SPR, FLAG_OF); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_SF|FLAG_ZF|FLAG_PF); +} + +//!Instruction xor_rm32_imm32 behavior method +void ac_behavior( xor_rm32_imm32 ) +{ + acprintf ( "XOR RM32, IMM32\n" ); + uint op1, op2, res; + op1 = dataManager.getImmediate(SPR, ac_pc); + op2 = dataManager.getMemOrReg2(MEM, GR); + res = op1^op2; + dataManager.setMemOrReg2(MEM, GR, res); + resetFlag(SPR, FLAG_CF); + resetFlag(SPR, FLAG_OF); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_SF|FLAG_ZF|FLAG_PF); +} + +//!Instruction xor_rm32_imm8 behavior method +void ac_behavior( xor_rm32_imm8 ) +{ + acprintf ( "XOR RM32, IMM8\n" ); + signed char i = data.immediate8(SPR, ac_pc); + signed int aux = i; + uint op1, op2, res; + op1 = aux; + op2 = dataManager.getMemOrReg2(MEM, GR); + res = op1^op2; + dataManager.setMemOrReg2(MEM, GR, res); + resetFlag(SPR, FLAG_CF); + resetFlag(SPR, FLAG_OF); + checkFlags(SPR, OPER_NONE,op1,op2,res,FLAG_SF|FLAG_ZF|FLAG_PF); +} + +//!Instruction div_rm32 behavior method +void ac_behavior( div_rm32 ) +{ + acprintf ( "DIV RM32\n" ); + if ( OperandSize == OPERAND_SIZE16 ) + { + unsigned int op1 = (readRegister(GR, DX)<<16)|((readRegister(GR, AX)&MASK_16BITS)); + unsigned short op2 = dataManager.getMemOrReg2(MEM, GR); + writeRegister(GR, AX, op1/op2); + writeRegister(GR, DX, op1%op2); + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + unsigned long long edx = readRegister(GR, EDX); + unsigned long long op1 = (edx<<32)|(readRegister(GR, EAX)); + unsigned int op2 = dataManager.getMemOrReg2(MEM, GR); + writeRegister(GR, EAX, op1/op2); + writeRegister(GR, EDX, op1%op2); + } +} + +//!Instruction idiv_rm32 behavior method +void ac_behavior( idiv_rm32 ) +{ + acprintf ( "IDIV RM32\n" ); + if ( OperandSize == OPERAND_SIZE16 ) + { + signed int op1 = (readRegister(GR, DX)<<16)|((readRegister(GR, AX)&MASK_16BITS)); + signed short op2 = dataManager.getMemOrReg2(MEM, GR); + writeRegister(GR, AX, op1/op2); + writeRegister(GR, DX, op1%op2); + } + else if ( OperandSize == OPERAND_SIZE32 ) + { + signed long long edx = readRegister(GR, EDX); + signed long long op1 = (edx<<32)|(readRegister(GR, EAX)); + signed int op2 = dataManager.getMemOrReg2(MEM, GR); + writeRegister(GR, EAX, op1/op2); + writeRegister(GR, EDX, op1%op2); + } +} + +//!Instruction imul_rm32 behavior method +void ac_behavior( imul_rm32 ) +{ + acprintf ( "IMUL RM32\n" ); + signed int op1 = readRegister(GR, EAX); + signed int op2 = dataManager.getMemOrReg2(MEM, GR); + signed long long lop1 = op1; + signed long long lop2 = op2; + signed long long res = lop1 * lop2; + if ( (res>0xFFFF&&(OperandSize==OPERAND_SIZE16))||(res>0xFFFFFFFF&&(OperandSize==OPERAND_SIZE32)) ) + { + setFlag(SPR, FLAG_CF); + setFlag(SPR, FLAG_OF); + } + else + { + resetFlag(SPR, FLAG_CF); + resetFlag(SPR, FLAG_OF); + } + uint mask = 0xFFFFFFFF; + uint disp_ = 32; + if ( OperandSize == OPERAND_SIZE16 ) + { + mask = 0xFFFF; + disp_ = 16; + } + writeRegister(GR, EDX, res >> disp_ ); + writeRegister(GR, EAX, res & mask); +} + +//!Instruction neg_rm32 behavior method +void ac_behavior( neg_rm32 ) +{ + acprintf ( " NEG RM32\n" ); + uint op, aux; + if ( data.usesMemory() ) + { + op = MEM.read(data.address()); + aux = (~op)+0x01; + MEM.write(data.address(),aux); + } + else + { + op = GR.read(data.reg2()); + aux = (~op)+0x01; + GR.write(data.reg2(),aux); + } + if ( !op ) resetFlag(SPR, FLAG_CF); + else setFlag(SPR, FLAG_CF); + checkFlags(SPR, OPER_ADD,(~op),1,aux,FLAG_OF|FLAG_SF|FLAG_ZF|FLAG_AF|FLAG_PF); +} + +//!Instruction not_rm32 behavior method +void ac_behavior( not_rm32 ) +{ + acprintf ( "NOT RM32\n" ); + uint op = dataManager.getMemOrReg2(MEM, GR); + dataManager.setMemOrReg2(MEM, GR, ~op); +} + +//!Instruction test_rm32_imm32 behavior method +void ac_behavior( test_rm32_imm32 ) +{ + acprintf ( " TEST RM32, IMM32\n" ); + uint op1, op2, aux; + if ( data.usesMemory() ) op1 = MEM.read(data.address()); + else op1 = GR.read(data.reg2()); + op2 = data.immediate(SPR, ac_pc); + aux = op1 & op2; + resetFlag(SPR, FLAG_OF); + resetFlag(SPR, FLAG_CF); + checkFlags(SPR, OPER_NONE,op1,op2,aux,FLAG_SF|FLAG_ZF|FLAG_PF); +} + +//!Instruction rcl_rm32 behavior method +void ac_behavior( rcl_rm32 ) +{ + acprintf ( " RCL RM32\n" ); + unsigned char count = 1; + unsigned char tempCount = count & 0x1F; + uint destination; + bool tempCF; + if ( data.usesMemory() ) destination = MEM.read(data.address()); + else destination = GR.read(data.reg2()); + while ( tempCount != 0 ) + { + tempCF = (destination&(1<<31)); + destination = (destination<<1) + testFlag(SPR, FLAG_CF); + if ( tempCF ) setFlag(SPR, FLAG_CF); + else resetFlag(SPR, FLAG_CF); + tempCount--; + } + if ( count==1 ) + { + if ((destination&(1<<31))^(testFlag(SPR, FLAG_CF))) setFlag(SPR, FLAG_OF); + else resetFlag(SPR, FLAG_OF); + } + if ( data.usesMemory() ) MEM.write(data.address(),destination); + else GR.write(data.reg2(),destination); +} + +//!Instruction rcl_rm32_imm8 behavior method +void ac_behavior( rcl_rm32_imm8 ) +{ + acprintf ( " RCL RM32, IMM8\n" ); + unsigned char count = data.immediate8(SPR, ac_pc); + unsigned char tempCount = count & 0x1F; + uint destination; + bool tempCF; + if ( data.usesMemory() ) destination = MEM.read(data.address()); + else destination = GR.read(data.reg2()); + while ( tempCount != 0 ) + { + tempCF = (destination&(1<<31)); + destination = (destination<<1) + testFlag(SPR, FLAG_CF); + if ( tempCF ) setFlag(SPR, FLAG_CF); + else resetFlag(SPR, FLAG_CF); + tempCount--; + } + if ( count==1 ) + { + if ((destination&(1<<31))^(testFlag(SPR, FLAG_CF))) setFlag(SPR, FLAG_OF); + else resetFlag(SPR, FLAG_OF); + } + if ( data.usesMemory() ) MEM.write(data.address(),destination); + else GR.write(data.reg2(),destination); +} + +//!Instruction rcr_rm32 behavior method +void ac_behavior( rcr_rm32 ) +{ + acprintf ( " RCR RM32\n" ); + unsigned char count = 1; + unsigned char tempCount = count & 0x1F; + uint destination; + bool tempCF; + if ( data.usesMemory() ) destination = MEM.read(data.address()); + else destination = GR.read(data.reg2()); + if ( count == 1 ) + { + if ((destination&(1<<31))^(testFlag(SPR, FLAG_CF))) setFlag(SPR, FLAG_OF); + else resetFlag(SPR, FLAG_OF); + } + while ( tempCount != 0 ) + { + tempCF = (destination&0x01); + destination = (destination>>1)+(testFlag(SPR, FLAG_CF)*(1<<31)); + if ( tempCF ) setFlag(SPR, FLAG_CF); + else resetFlag(SPR, FLAG_CF); + tempCount--; + } + if ( data.usesMemory() ) MEM.write(data.address(),destination); + else GR.write(data.reg2(),destination); +} + +//!Instruction rcr_rm32_imm8 behavior method +void ac_behavior( rcr_rm32_imm8 ) +{ + acprintf ( " RCR RM32, IMM8\n" ); + unsigned char count = data.immediate8(SPR, ac_pc); + unsigned char tempCount = count & 0x1F; + uint destination; + bool tempCF; + if ( data.usesMemory() ) destination = MEM.read(data.address()); + else destination = GR.read(data.reg2()); + if ( count == 1 ) + { + if ((destination&(1<<31))^(testFlag(SPR, FLAG_CF))) setFlag(SPR, FLAG_OF); + else resetFlag(SPR, FLAG_OF); + } + while ( tempCount != 0 ) + { + tempCF = (destination&0x01); + destination = (destination>>1)+(testFlag(SPR, FLAG_CF)*(1<<31)); + if ( tempCF ) setFlag(SPR, FLAG_CF); + else resetFlag(SPR, FLAG_CF); + tempCount--; + } + if ( data.usesMemory() ) MEM.write(data.address(),destination); + else GR.write(data.reg2(),destination); +} + +//!Instruction rol_rm32 behavior method +void ac_behavior( rol_rm32 ) +{ + acprintf ( " ROL RM32\n" ); + unsigned char count = 1; + unsigned char tempCount = count % 32; + bool tempCF; + uint destination; + if ( data.usesMemory() ) destination = MEM.read(data.address()); + else destination = GR.read(data.reg2()); + while ( tempCount != 0 ) + { + tempCF = (destination & (1<<31)); + destination = (destination<<1) + tempCF; + tempCount--; + } + if ( destination & 0x01 ) setFlag(SPR, FLAG_CF); + else resetFlag(SPR, FLAG_CF); + if ( data.usesMemory() ) MEM.write(data.address(),destination); + else GR.write(data.reg2(),destination); + if ( count == 1 ) + { + if ((destination&(1<<31))^(testFlag(SPR, FLAG_CF))) setFlag(SPR, FLAG_OF); + else resetFlag(SPR, FLAG_OF); + } +} + +//!Instruction rol_rm32_imm8 behavior method +void ac_behavior( rol_rm32_imm8 ) +{ + acprintf ( " ROL RM32, IMM8\n" ); + unsigned char count = data.immediate8(SPR, ac_pc); + unsigned char tempCount = count % 32; + bool tempCF; + uint destination; + if ( data.usesMemory() ) destination = MEM.read(data.address()); + else destination = GR.read(data.reg2()); + while ( tempCount != 0 ) + { + tempCF = (destination & (1<<31)); + destination = (destination<<1) + tempCF; + tempCount--; + } + if ( destination & 0x01 ) setFlag(SPR, FLAG_CF); + else resetFlag(SPR, FLAG_CF); + if ( data.usesMemory() ) MEM.write(data.address(),destination); + else GR.write(data.reg2(),destination); + if ( count == 1 ) + { + if ((destination&(1<<31))^(testFlag(SPR, FLAG_CF))) setFlag(SPR, FLAG_OF); + else resetFlag(SPR, FLAG_OF); + } +} + +//!Instruction ror_rm32 behavior method +void ac_behavior( ror_rm32 ) +{ + acprintf ( " ROR RM32\n" ); + unsigned char count = 1; + unsigned char tempCount = count % 32; + bool tempCF; + uint destination; + if ( data.usesMemory() ) destination = MEM.read(data.address()); + else destination = GR.read(data.reg2()); + while ( tempCount != 0 ) + { + tempCF = destination & (0x01); + destination = (destination>>1)+(tempCF*(1<<31)); + tempCount--; + } + if ( data.usesMemory() ) MEM.write(data.address(),destination); + else GR.write(data.reg2(),destination); + if ( destination&(1<<31) ) setFlag(SPR, FLAG_CF); + else resetFlag(SPR, FLAG_CF); + if ( count == 1 ) + { + if ((destination&(1<<31))^(destination&(1<<30))) setFlag(SPR, FLAG_OF); + else resetFlag(SPR, FLAG_OF); + } +} + +//!Instruction ror_rm32_imm8 behavior method +void ac_behavior( ror_rm32_imm8 ) +{ + acprintf ( " ROR RM32, IMM8\n" ); + unsigned char count = (data.immediate8(SPR, ac_pc)&0x1F); + unsigned char tempCount = count % 32; + bool tempCF; + uint destination; + if ( data.usesMemory() ) destination = MEM.read(data.address()); + else destination = GR.read(data.reg2()); + while ( tempCount != 0 ) + { + tempCF = destination & (0x01); + destination = (destination>>1)+(tempCF*(1<<31)); + tempCount--; + } + if ( data.usesMemory() ) MEM.write(data.address(),destination); + else GR.write(data.reg2(),destination); + if ( destination&(1<<31) ) setFlag(SPR, FLAG_CF); + else resetFlag(SPR, FLAG_CF); + if ( count == 1 ) + { + if ((destination&(1<<31))^(destination&(1<<30))) setFlag(SPR, FLAG_OF); + else resetFlag(SPR, FLAG_OF); + } +} + +//!Instruction P_LOCK behavior method +void ac_behavior( P_LOCK ) +{ + acprintf ( " LOCK prefix \n" ); +} + +//!Instruction P_REPNE_REPNZ behavior method +void ac_behavior( P_REPNE_REPNZ ) +{ + acprintf ( " REPNE/REPNZ prefix \n" ); +} + +//!Instruction P_REP_REPE_REPZ behavior method +void ac_behavior( P_REP_REPE_REPZ ) +{ + acprintf ( " REP/REPE/REPZ prefix \n" ); +} + +//!Instruction P_CS behavior method +void ac_behavior( P_CS ) +{ + acprintf ( " CS override prefix \n" ); +} + +//!Instruction P_SS behavior method +void ac_behavior( P_SS ) +{ + acprintf ( " SS override prefix \n" ); +} + +//!Instruction P_DS behavior method +void ac_behavior( P_DS ) +{ + acprintf ( " DS override prefix \n" ); +} + +//!Instruction P_ES behavior method +void ac_behavior( P_ES ) +{ + acprintf ( " ES override prefix \n" ); +} + +//!Instruction P_FS behavior method +void ac_behavior( P_FS ) +{ + acprintf ( " FS override prefix \n" ); +} + +//!Instruction P_GS behavior method +void ac_behavior( P_GS ) +{ + acprintf ( " GS override prefix \n" ); +} + +//!Instruction P_BTAKEN behavior method +void ac_behavior( P_BTAKEN ) +{ + acprintf ( " BRANCH TAKEN prefix \n" ); +} + +//!Instruction P_BNTAKEN behavior method +void ac_behavior( P_BNTAKEN ) +{ + acprintf ( " BRANCH NOT TAKEN prefix \n" ); +} + +//!Instruction P_OPSIZE behavior method +void ac_behavior( P_OPSIZE ) +{ + acprintf ( "OPERAND SIZE is 16Bits for next instruction\n" ); + OperandSize = OPERAND_SIZE16JUST; + // OperandSize = OPERAND_SIZE32; +} + +//!Instruction P_ADSIZE behavior method +void ac_behavior( P_ADSIZE ) +{ + acprintf ( " ADDRESS SIZE if 16Bits for next instruction\n" ); + AddressSize = ADDRESS_SIZE16JUST; +} + +//!Instruction movb_rm32_imm8 behavior method +void ac_behavior( mov_rm8_imm8 ) +{ + acprintf ( "CALLED MOV RM8, IMM8\n" ); + if ( data.usesMemory() ) MEM.write_byte(data.address(),data.immediate8(SPR, ac_pc)); + else GR.write(data.reg2(),data.immediate8(SPR, ac_pc)); +} + +//!Instruction mov_r8_rm8 behavior method +void ac_behavior( mov_r8_rm8 ) +{ + acprintf ( "CALLED MOV R8, RM8\n" ); + unsigned char op; + if ( data.usesMemory() ) op = MEM.read_byte(data.address()); + else op = readRegister8(GR, data.reg2()); + writeRegister8(GR, data.reg1(),op); +} + +//!Instruction mov_rm8_r8 behavior method +void ac_behavior( mov_rm8_r8 ) +{ + acprintf ( "CALLED MOV RM8, R8\n" ); + unsigned char op = readRegister8(GR, data.reg1()); + if ( data.usesMemory() ) MEM.write_byte(data.address(),op); + else writeRegister8(GR, data.reg2(),op); +} + +//!Instruction mov_AL_imm8 behavior method +void ac_behavior( mov_AL_imm8 ) +{ + acprintf ( "CALLED MOV AL, IMM8\n" ); + writeRegister8(GR, AL,data.immediate8(SPR, ac_pc)); +} + +//!Instruction mov_CL_imm8 behavior method +void ac_behavior( mov_CL_imm8 ) +{ + acprintf ( "CALLED MOV CL, IMM8\n" ); + writeRegister8(GR, CL,data.immediate8(SPR, ac_pc)); +} + +//!Instruction mov_DL_imm8 behavior method +void ac_behavior( mov_DL_imm8 ) +{ + acprintf ( "CALLED MOV DL, IMM8\n" ); + writeRegister8(GR, DL,data.immediate8(SPR, ac_pc)); +} + +//!Instruction mov_BL_imm8 behavior method +void ac_behavior( mov_BL_imm8 ) +{ + acprintf ( "CALLED MOV BL, IMM8\n" ); + writeRegister8(GR, BL,data.immediate8(SPR, ac_pc)); +} + +//!Instruction mov_AH_imm8 behavior method +void ac_behavior( mov_AH_imm8 ) +{ + acprintf ( "CALLED MOV AH, IMM8\n" ); + writeRegister8(GR, AH,data.immediate8(SPR, ac_pc)); +} + +//!Instruction mov_CH_imm8 behavior method +void ac_behavior( mov_CH_imm8 ) +{ + acprintf ( "CALLED MOV CH, IMM8\n" ); + writeRegister8(GR, CH,data.immediate8(SPR, ac_pc)); +} + +//!Instruction mov_DH_imm8 behavior method +void ac_behavior( mov_DH_imm8 ) +{ + acprintf ( "CALLED MOV DH, IMM8\n" ); + writeRegister8(GR, DH,data.immediate8(SPR, ac_pc)); +} + +//!Instruction mov_BH_imm8 behavior method +void ac_behavior( mov_BH_imm8 ) +{ + acprintf ( "CALLED MOV BH, IMM8\n" ); + writeRegister8(GR, BH,data.immediate8(SPR, ac_pc)); +} + +//!Instruction add_r8_rm8 behavior method +void ac_behavior( add_r8_rm8 ) +{ + acprintf ( "CALLED ADD R8, RM8\n" ); + unsigned char op1; + if ( data.usesMemory() ) op1 = MEM.read_byte(data.address()); + else op1 = readRegister8(GR, data.reg2()); + unsigned char op2 = readRegister8(GR, data.reg1()); + unsigned char res = op1 + op2; + writeRegister8(GR, data.reg1(),res); + checkFlags8(SPR, OPER_ADD,op1,op2,res,FLAG_ALL); +} + +//!Instruction add_rm8_r8 behavior method +void ac_behavior( add_rm8_r8 ) +{ + acprintf ( "CALLED ADD RM8, R8\n" ); + unsigned char op1; + if ( data.usesMemory() ) op1 = MEM.read_byte(data.address()); + else op1 = readRegister8(GR, data.reg2()); + unsigned char op2 = readRegister8(GR, data.reg1()); + unsigned char res = op1 + op2; + if ( data.usesMemory() ) MEM.write_byte(data.address(), res ); + else writeRegister8(GR, data.reg2(),res); + checkFlags8(SPR, OPER_ADD,op1,op2,res,FLAG_ALL); +} + +//!Instruction add_rm8_imm8 behavior method +void ac_behavior( add_rm8_imm8 ) +{ + acprintf ( "CALLED ADD RM8, IMM8\n" ); + unsigned char op1; + if ( data.usesMemory() ) op1 = MEM.read_byte(data.address()); + else op1 = readRegister8(GR, data.reg2()); + unsigned char op2 = data.immediate8(SPR, ac_pc); + unsigned char res = op1 + op2; + if ( data.usesMemory() ) MEM.write_byte(data.address(), res); + else writeRegister8(GR, data.reg2(), res); + checkFlags8(SPR, OPER_ADD,op1,op2,res,FLAG_ALL); +} + +//!Instruction sub_rm8_r8 behavior method +void ac_behavior( sub_rm8_r8 ) +{ + acprintf ( "CALLED SUB RM8, R8\n" ); + unsigned char op1, op2, res; + if ( data.usesMemory() ) op1 = MEM.read_byte(data.address()); + else op1 = readRegister8(GR, data.reg2()); + op2 = readRegister8(GR, data.reg1()); + res = op1 - op2; + if ( data.usesMemory() ) MEM.write_byte(data.address(),res); + else writeRegister8(GR, data.reg2(),res); + checkFlags8(SPR, OPER_SUB,op1,op2,res,FLAG_ALL); +} + +//!Instruction sub_rm8_imm8 behavior method +void ac_behavior( sub_rm8_imm8 ) +{ + acprintf ( "CALLED SUB RM8, IMM8\n" ); + unsigned char op1; + if ( data.usesMemory() ) op1 = MEM.read_byte(data.address()); + else op1 = readRegister8(GR, data.reg2()); + unsigned char op2 = data.immediate8(SPR, ac_pc); + unsigned char res = op1 - op2; + if ( data.usesMemory() ) MEM.write_byte(data.address(), res); + else writeRegister8(GR, data.reg2(), res); + checkFlags8(SPR, OPER_SUB,op1,op2,res,FLAG_ALL); +} + +//!Instruction inc_rm8 behavior method +void ac_behavior( inc_rm8 ) +{ + acprintf ( "CALLED INC RM8\n" ); + unsigned char op1; + if ( data.usesMemory() ) op1 = MEM.read_byte(data.address()); + else op1 = readRegister8(GR, data.reg2()); + unsigned char op2 = 1; + unsigned char res = op1 + op2; + if ( data.usesMemory() ) MEM.write_byte(data.address(),res); + else writeRegister8(GR, data.reg2(),res); + checkFlags8(SPR, OPER_ADD,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +//!Instruction dec_rm8 behavior method +void ac_behavior( dec_rm8 ) +{ + acprintf ( "CALLED DEC RM8\n" ); + unsigned char op1; + if ( data.usesMemory() ) op1 = MEM.read_byte(data.address()); + else op1 = readRegister8(GR, data.reg2()); + unsigned char op2 = 1; + unsigned char res = op1 - op2; + if ( data.usesMemory() ) MEM.write_byte(data.address(), res); + else writeRegister8(GR, data.reg2(), res); + checkFlags8(SPR, OPER_SUB,op1,op2,res,FLAG_ALL&(~FLAG_CF)); +} + +//!Instruction imul_rm8 behavior method +void ac_behavior( imul_rm8 ) +{ + printf ( "IMUL RM8\n" ); + signed char op1 = readRegister8(GR, AL); + signed char op2; + signed short res; + if ( data.usesMemory() ) op2 = MEM.read_byte(data.address()); + else op2 = readRegister8(GR, data.reg2()); + res = op1 * op2; + if ( res & 0xFF00 ) + { + setFlag(SPR, FLAG_CF); + setFlag(SPR, FLAG_OF); + } + else + { + resetFlag(SPR, FLAG_CF); + resetFlag(SPR, FLAG_OF); + } + OperandSize = OPERAND_SIZE16; + writeRegister(GR, AX, res); +} + +//!Instruction imul_r32_rm32 behavior method +void ac_behavior( imul_r32_rm32 ) +{ + printf ( "IMUL R32, RM32\n" ); + signed int op1 = dataManager.getReg1(GR); + signed int op2 = dataManager.getMemOrReg2(MEM, GR); + signed long long res = op1 * op2; + if ( res > 0xFFFFFFFF ) + { + setFlag(SPR, FLAG_CF); + setFlag(SPR, FLAG_OF); + } + else + { + resetFlag(SPR, FLAG_CF); + resetFlag(SPR, FLAG_OF); + } + dataManager.setReg1(GR, res); +} + +//!Instruction mul_rm8 behavior method +void ac_behavior( mul_rm8 ) +{ + printf ( "MUL RM8\n" ); + unsigned char op1 = readRegister8(GR, AL); + unsigned char op2; + unsigned short res; + if ( data.usesMemory() ) op2 = MEM.read_byte(data.address()); + else op2 = readRegister8(GR, data.reg2()); + res = op1 * op2; + if ( res & 0xFF00 ) + { + setFlag(SPR, FLAG_CF); + setFlag(SPR, FLAG_OF); + } + else + { + resetFlag(SPR, FLAG_CF); + resetFlag(SPR, FLAG_OF); + } + OperandSize = OPERAND_SIZE16; + writeRegister(GR, AX, res); +} + +//!Instruction sal_rm8 behavior method +void ac_behavior( sal_rm8 ) +{ + printf ( "SAL RM8\n" ); + unsigned char op, res; + if ( data.usesMemory() ) op = MEM.read_byte(data.address()); + else op = readRegister8(GR, data.reg2()); + res = op << 1; + if ( data.usesMemory() ) MEM.write_byte(data.address(),res); + else writeRegister8(GR, data.reg2(),res); + checkFlags8(SPR, OPER_NONE,0,0,res,FLAG_ALL); + writeFlag(SPR, FLAG_CF, op&0x80); + bool ofcond = (!MSB8(res)&&testFlag(SPR, FLAG_CF))||(MSB8(res)&&!testFlag(SPR, FLAG_CF)); + writeFlag(SPR, FLAG_OF, ofcond); +} + +//!Instruction sal_rm8_imm8 behavior method +void ac_behavior( sal_rm8_imm8 ) +{ + printf ( "SAL RM8, IMM8\n" ); + unsigned char op, res; + signed char count = data.immediate8(SPR, ac_pc); + if ( data.usesMemory() ) op = MEM.read_byte(data.address()); + else op = readRegister8(GR, data.reg2()); + res = op << count; + if ( data.usesMemory() ) MEM.write_byte(data.address(),res); + else writeRegister(GR, data.reg2(),res); + checkFlags8(SPR, OPER_NONE,0,0,res,FLAG_ALL); + if ( count > 0 ) writeFlag(SPR, FLAG_CF, (op<<(count-1))&0x80); + bool ofcond = (!MSB8(res)&&testFlag(SPR, FLAG_CF))||(MSB8(res)&&!testFlag(SPR, FLAG_CF)); + if ( count == 1 ) writeFlag(SPR, FLAG_OF, ofcond); +} + +//!Instruction shr_rm8 behavior method +void ac_behavior( shr_rm8 ) +{ + printf ( "SHR RM8\n" ); + unsigned char op, res; + if ( data.usesMemory() ) op = MEM.read_byte(data.address()); + else op = readRegister8(GR, data.reg2()); + res = op >> 1; + if ( data.usesMemory() ) MEM.write_byte(data.address(),res); + else writeRegister8(GR, data.reg2(),res); + checkFlags8(SPR, OPER_NONE,0,0,res,FLAG_ALL); + writeFlag(SPR, FLAG_CF, op&0x01); + writeFlag(SPR, FLAG_OF, op&0x80); +} + +//!Instruction sar_rm8 behavior method +void ac_behavior( sar_rm8 ) +{ + printf ( "SAR RM8\n" ); + signed char op, res; + if ( data.usesMemory() ) op = MEM.read_byte(data.address()); + else op = readRegister8(GR, data.reg2()); + res = op>>1; + if ( data.usesMemory() ) MEM.write_byte(data.address(),res); + else writeRegister8(GR, data.reg2(),res); + checkFlags8(SPR, OPER_NONE,0,0,res,FLAG_ALL); + writeFlag(SPR, FLAG_CF, op&0x01); + resetFlag(SPR, FLAG_OF); +} + +//!Instruction sar_rm8_imm8 behavior method +void ac_behavior( sar_rm8_imm8 ) +{ + printf ( "SAR RM8, IMM8\n" ); + signed char count; + signed char op, res; + if ( data.usesMemory() ) op = MEM.read_byte(data.address()); + else op = readRegister8(GR, data.reg2()); + count = data.immediate8(SPR, ac_pc); + res = op >> count; + if ( data.usesMemory() ) MEM.write_byte(data.address(),res); + else writeRegister8(GR, data.reg2(),res); + checkFlags8(SPR, OPER_NONE,0,0,res,FLAG_ALL); + if ( count > 0 ) writeFlag(SPR, FLAG_CF, (op>>(count-1))&0x01); + if ( count == 1 ) resetFlag(SPR, FLAG_OF); +} + +//!Instruction cmp_rm8_imm8 behavior method +void ac_behavior( cmp_rm8_imm8 ) +{ + printf ( "CMP RM8, IMM8\n" ); + unsigned char op1, res; + signed char op2; + if ( data.usesMemory() ) op1 = MEM.read_byte(data.address()); + else op1 = readRegister8(GR, data.reg2()); + op2 = data.immediate8(SPR, ac_pc); + res = op1 - op2; + checkFlags8(SPR, OPER_SUB,op1,op2,res,FLAG_ALL); +} + +//!Instruction cmp_AL_imm8 behavior method +void ac_behavior( cmp_AL_imm8 ) +{ + printf ( "CMP AL, IMM8\n" ); + unsigned char op1, res; + signed char op2; + op1 = readRegister8(GR, AL); + op2 = data.immediate8(SPR, ac_pc); + res = op1 - op2; + checkFlags8(SPR, OPER_SUB,op1,op2,res,FLAG_ALL); +} + +//!Instruction shr_rm8_imm8 behavior method +void ac_behavior( shr_rm8_imm8 ) +{ + printf ( "SHR RM8, IMM8\n" ); + signed char count; + unsigned char op, res; + if ( data.usesMemory() ) op = MEM.read_byte(data.address()); + else op = readRegister8(GR, data.reg2()); + count = data.immediate8(SPR, ac_pc); + res = op >> count; + if ( data.usesMemory() ) MEM.write_byte(data.address(),res); + else writeRegister8(GR, data.reg2(),res); + checkFlags8(SPR, OPER_NONE,0,0,res,FLAG_ALL); + if ( count == 1 ) writeFlag(SPR, FLAG_OF, op&0x80); + if ( count > 0 ) writeFlag(SPR, FLAG_CF, (op>>(count-1))&0x01); +} + +//!Instruction div_rm8 behavior method +void ac_behavior( div_rm8 ) +{ + printf ( "DIV RM8\n" ); + OperandSize = OPERAND_SIZE16; + unsigned short op1 = readRegister(GR, AX); + OperandSize = OPERAND_SIZE32; + unsigned char op2; + if ( data.usesMemory() ) op2 = MEM.read_byte(data.address()); + else op2 = readRegister8(GR, data.reg2()); + writeRegister8(GR, AL, op1/op2); + writeRegister8(GR, AH, op1%op2); +} + +//!Instruction or_r8_rm8 behavior method +void ac_behavior( or_r8_rm8 ) +{ + printf ( "OR R8, RM8\n" ); + unsigned char op1 = readRegister8(GR, data.reg1()); + unsigned char op2, res; + if ( data.usesMemory() ) op2 = MEM.read_byte(data.address()); + else op2 = readRegister8(GR, data.reg2()); + res = op1|op2; + writeRegister8(GR, data.reg1(),res); + checkFlags8(SPR, OPER_NONE,op1,op2,res,FLAG_ALL); + resetFlag(SPR, FLAG_OF); + resetFlag(SPR, FLAG_CF); +} + +//!Instruction and_r8_rm8 behavior method +void ac_behavior( and_r8_rm8 ) +{ + printf ( "AND R8, RM8\n" ); + unsigned char op1 = readRegister8(GR, data.reg1()); + unsigned char op2, res; + if ( data.usesMemory() ) op2 = MEM.read_byte(data.address()); + else op2 = readRegister8(GR, data.reg2()); + res = op1&op2; + writeRegister8(GR, data.reg1(),res); + checkFlags8(SPR, OPER_NONE,op1,op2,res,FLAG_ALL); + resetFlag(SPR, FLAG_OF); + resetFlag(SPR, FLAG_CF); +} + +//!Instruction xor_r8_rm8 behavior method +void ac_behavior( xor_r8_rm8 ) +{ + printf ( "XOR R8, RM8\n" ); + unsigned char op1 = readRegister8(GR, data.reg1()); + unsigned char op2, res; + if ( data.usesMemory() ) op2 = MEM.read_byte(data.address()); + else op2 = readRegister8(GR, data.reg2()); + res = op1^op2; + writeRegister8(GR, data.reg1(),res); + checkFlags8(SPR, OPER_NONE,op1,op2,res,FLAG_ALL); + resetFlag(SPR, FLAG_OF); + resetFlag(SPR, FLAG_CF); +} + +//!Instruction cmp_r8_rm8 behavior method. +void ac_behavior( cmp_r8_rm8 ) +{ + printf ( "CMP R8, RM8\n" ); + unsigned char op1, op2, res; + op1 = readRegister8(GR, data.reg1()); + if ( data.usesMemory() ) op2 = MEM.read_byte(data.address()); + else op2 = readRegister8(GR, data.reg2()); + res = op1 - op2; + checkFlags8(SPR, OPER_SUB,op1,op2,res,FLAG_ALL); +} + +//!Instruction push_imm8 behavior method. +void ac_behavior( push_imm8 ) +{ + printf ( "PUSH IMM8\n" ); + signed char i = data.immediate8(SPR, ac_pc); + signed int aux = i; + push(MEM, GR, aux); +} + +//!Instruction dump_registers behavior method. +void ac_behavior( dump_registers ) +{ + if ( VERBOSE ) { + printf ( "------------------ Register dumping begin --------------------\n" ); + printf ( "- General Purpose --------------------------------------------\n" ); + printf ( "EAX = %08X\tECX = %08X\t", GR.read(EAX), GR.read(ECX) ); + printf ( "EDX = %08X\tEBX = %08X\n", GR.read(EDX), GR.read(EBX) ); + printf ( "ESP = %08X\tEBP = %08X\t", GR.read(ESP), GR.read(EBP) ); + printf ( "ESI = %08X\tEDI = %08X\n", GR.read(ESI), GR.read(EDI) ); + printf ( "- Segment ----------------------------------------------------\n" ); + printf ( "CS = %04X\tDS = %04X\tSS = %04X\n", SR.read(CS), SR.read(DS), SR.read(SS) ); + printf ( "ES = %04X\tFS = %04X\tGS = %04X\n", SR.read(ES), SR.read(FS), SR.read(GS) ); + printf ( "- Flags ------------------------------------------------------\n" ); + printf ( "EFLAGS = %08X\n", SPR.read(EFLAGS) ); + printf ( "OF FLAG = %d\n", testFlag(SPR, FLAG_OF) ); + printf ( "SF FLAG = %d\n", testFlag(SPR, FLAG_SF) ); + printf ( "ZF FLAG = %d\n", testFlag(SPR, FLAG_ZF) ); + printf ( "AF FLAG = %d\n", testFlag(SPR, FLAG_AF) ); + printf ( "CF FLAG = %d\n", testFlag(SPR, FLAG_CF) ); + printf ( "PF FLAG = %d\n", testFlag(SPR, FLAG_PF) ); + printf ( "- Program counter --------------------------------------------\n" ); + printf ( "EIP = %08X\n", SPR.read(EIP) ); + printf ( "------------------ Register dumping end ----------------------\n\n" ); + } +} + +//!Instruction dump_memory behavior method. +void ac_behavior( dump_memory ) +{ + if ( VERBOSE ) { + printf ( "------------------ Memory dump begin --------------------\n" ); + printf ( "From : %08X\tTo : %08X\n", iadd, eadd ); + printf ( "- Data --------------------------------------------------\n" ); + unsigned int numBytes = (eadd-iadd); + unsigned int counter = 0; + unsigned char d; + if ( eadd < iadd ) numBytes = 0; + while ( counter <= numBytes ) + { + if ( !(counter%8) ) printf ( "%08X\t", iadd+counter ); + d = MEM.read(iadd+counter); + printf ( "%02X", d ); + counter++; + if ( !(counter%8) ) printf ( "\n" ); + else printf ( " " ); + } + if ( counter%8 ) printf ( "\n" ); + printf ( "------------------ Memory dump end ----------------------\n\n" ); + } +} + +//!Instruction dumpt_stack behavior method. +void ac_behavior( dump_stack ) +{ + if ( VERBOSE ) { + printf ( "------------------ Stack dump begin ---------------------\n" ); + printf ( "Top : %08X\tBottom : %08X\n", GR.read(ESP), STACK_BOTTOM ); + printf ( "- Data --------------------------------------------------\n" ); + for ( unsigned int i=0; i<(STACK_BOTTOM-GR.read(ESP)); i+=4 ) + printf ( "%08X\t %08X\n", GR.read(ESP)+i, MEM.read(GR.read(ESP)+i) ); + printf ( "------------------ Stack dump end -----------------------\n\n" ); + } +} + +//!Instruction sahf behavior method. +//void ac_behavior( sahf ) +//{ +//printManager.print ( "SAHF " ); +//} + + +//!Instruction aaa description + +/* ********************************************* +Description: +Adjusts the sum of two unpacked BCD values to create an unpacked BCD result. The AL +register is the implied source and destination operand for this instruction. The AAA instruction +is only useful when it follows an ADD instruction that adds (binary addition) two unpacked +BCD values and stores a byte result in the AL register. The AAA instruction then adjusts the +contents of the AL register to contain the correct 1-digit unpacked BCD result. +If the addition produces a decimal carry, the AH register increments by 1, and the CF and AF +flags are set. If there was no decimal carry, the CF and AF flags are cleared and the AH register +is unchanged. In either case, bits 4 through 7 of the AL register are set to 0. +********************************************** */ + + + +//!Instruction aaa behavior method. +void ac_behavior( aaa ){ + signed int aux; + acprintf( "AAA - not tested\n" ); + + aux = GR[AL]; + if ( ( (aux & 0x0F) > 9 ) or ( testFlag(SPR, FLAG_AF) ) ){ + aux+=6; + GR[AL] = aux; + // aux = GR[AH]; + aux = readRegister8(GR, AH); + aux+=1; + writeRegister8(GR, AH,aux); + writeFlag(SPR, FLAG_AF, 1); + writeFlag(SPR, FLAG_CF, 1); + aux = GR[AL]; + aux = ( aux & 0x0F ); + GR[AL] = aux; + }//if + else{ + resetFlag(SPR, FLAG_AF); + resetFlag(SPR, FLAG_CF); + aux = GR[AL]; + aux = ( aux & 0x0F ); + GR[AL] = aux; + }//else +}//ac_behavior(aaa) + + +//!Instruction aad description +/************************************************** +Description: +Adjusts two unpacked BCD digits (the least-significant digit in the AL register and the mostsignificant +digit in the AH register) so that a division operation performed on the result will yield +a correct unpacked BCD value. The AAD instruction is only useful when it precedes a DIV +instruction that divides (binary division) the adjusted value in the AX register by an unpacked +BCD value. +The AAD instruction sets the value in the AL register to (AL + (10 * AH)), and then clears the +AH register to 00H. The value in the AX register is then equal to the binary equivalent of the +original unpacked two-digit (base 10) number in registers AH and AL. +****************************************************/ +//!Instruction aad behavior method. +void ac_behavior( aad ){ + signed int tempAL,tempAH; + acprintf ( " AAD - not tested\n" ); + tempAL = GR[AL]; + //tempAH = GR[AH]; + tempAH = readRegister8(GR, AH); + GR[AL] = (( tempAL + ( tempAH*0x0A) ) & 0xFF); + writeRegister8(GR, AH,0); + //GR[AH] = 0; + setFlags_af(SPR, FLAG_SF, GR[AL] ); + setFlags_af(SPR, FLAG_ZF, GR[AL] ); + setFlags_af(SPR, FLAG_PF, GR[AL] ); +}//ac_behavior( aad ) + + +//!Instruction aam description +/* ************************************ +Description: +Adjusts the result of the multiplication of two unpacked BCD values to create a pair of unpacked +(base 10) BCD values. The AX register is the implied source and destination operand for this +instruction. The AAM instruction is only useful when it follows an MUL instruction that multiplies +(binary multiplication) two unpacked BCD values and stores a word result in the AX +register. The AAM instruction then adjusts the contents of the AX register to contain the correct +2-digit unpacked (base 10) BCD result. +************************************ */ +//!Instruction aam behavior method. +void ac_behavior( aam ){ + uint tempAL; + acprintf ( " AAM - not tested\n" ); + tempAL = GR[AL]; + //GR[AH] = ( tempAL / 0x0A ); + writeRegister8(GR, AH, ( tempAL / 0x0A)); + GR[AL] = ( tempAL % 0x0A ); + setFlags_af(SPR, FLAG_SF,GR[AL] ); + setFlags_af(SPR, FLAG_ZF,GR[AL] ); + setFlags_af(SPR, FLAG_PF,GR[AL] ); +} //ac_behavior( aam ) + +//!Instruction aas description +/* ***************************************************** +Adjusts the result of the subtraction of two unpacked BCD values to create a unpacked BCD +result. The AL register is the implied source and destination operand for this instruction. The +AAS instruction is only useful when it follows a SUB instruction that subtracts (binary subtraction) +one unpacked BCD value from another and stores a byte result in the AL register. The AAA +instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked +BCD result. +If the subtraction produced a decimal carry, the AH register decrements by 1, and the CF and +AF flags are set. If no decimal carry occurred, the CF and AF flags are cleared, and the AH +register is unchanged. In either case, the AL register is left with its top nibble set to 0. +******************************************************* */ +//!Instruction aas behavior method. +void ac_behavior( aas ){ + uint aux; + acprintf ( " AAS \n" ); + if ( ((GR[AL] & 0x0F) > 9) || ( testFlag(SPR, FLAG_AF )) ){ + aux = GR[AL]; + aux = aux - 6; + aux = (aux & 0x0F); + GR[AL] = aux; + aux = readRegister8(GR, AH); + //aux = GR[AH]; + aux = aux - 1; + // GR[AH] = aux; + writeRegister8(GR, AH,aux); + setFlag(SPR, FLAG_AF ); + setFlag(SPR, FLAG_CF ); + }//if + else{ + resetFlag(SPR, FLAG_CF ); + resetFlag(SPR, FLAG_AF ); + aux = GR[AL]; + aux = ( aux & 0x0F ); + }//else + +} //ac_behavior( aas ) + + +//!Instruction cbw_cwde description +/**************************************** +Description +Double the size of the source operand by means of sign extension. The CBW (convert byte to +word) instruction copies the sign (bit 7) in the source operand into every bit in the AH register. +The CWDE (convert word to doubleword) instruction copies the sign (bit 15) of the word in the +AX register into the high 16 bits of the EAX register. +CBW and CWDE reference the same opcode. The CBW instruction is intended for use when the +operand-size attribute is 16; CWDE is intended for use when the operand-size attribute is 32. +Some assemblers may force the operand size. Others may treat these two mnemonics as +synonyms (CBW/CWDE) and use the setting of the operand-size attribute to determine the size +of values to be converted. +*****************************************/ + +//!Instruction cbw_cwde behavior method. +void ac_behavior( cbw_cwde ) +{ + signed int tempGR; + if ( OperandSize == OPERAND_SIZE16 ){ //Instruction = CBW + acprintf ( " CBW \n" ); + tempGR = GR[AL]; + if (MSB8(tempGR))//negativo + GR[AX] = 0xFF00 | (tempGR & MASK_8BITS); + else + GR[AX] = 0x0000 | (tempGR & MASK_8BITS); + }//if + else if ( OperandSize == OPERAND_SIZE32 ){//Instruction = CWDE + acprintf ( "CWDE \n" ); + tempGR = GR[AX]; + if (MSB16(tempGR))//negativo + GR[EAX] = 0xFFFF0000 | (tempGR & MASK_16BITS); + else + GR[EAX] = 0x00000000 | (tempGR & MASK_16BITS); + + }//else +}//ac_behavior (cbw_cwde) + +//!Instruction daa description +/********************************************* +Description +Adjusts the sum of two packed BCD values to create a packed BCD result. The AL register is +the implied source and destination operand. The DAA instruction is only useful when it follows +an ADD instruction that adds (binary addition) two 2-digit, packed BCD values and stores a byte +result in the AL register. The DAA instruction then adjusts the contents of the AL register to +contain the correct 2-digit, packed BCD result. If a decimal carry is detected, the CF and AF +flags are set accordingly. +*********************************************/ +//!Instruction daa behavior method. +void ac_behavior( daa ){ + acprintf ( " DAA \n" ); + uint tempAL,old_AL,old_FLAG_CF; + uint op1, res; //para checar Flags + old_AL = GR[AL]; + old_FLAG_CF = SPR[FLAG_CF]; + + if( ((GR[AL] & 0x0F) > 9) || (testFlag(SPR, FLAG_AF)) ){ + tempAL = GR[AL]; + op1 = tempAL; + tempAL += 6; + res = tempAL; + GR[AL] = tempAL; + writeFlag(SPR, FLAG_CF,( old_FLAG_CF ||( ( (unsigned int)tempAL) > 0xFF ))); + setFlag(SPR, FLAG_AF); + + checkFlags8(SPR, OPER_ADD, op1,6,res,FLAG_SF ); + checkFlags8(SPR, OPER_ADD, op1,6,res,FLAG_ZF ); + checkFlags8(SPR, OPER_ADD, op1,6,res,FLAG_PF ); + + }//if + else + resetFlag(SPR, FLAG_AF); + + if ((old_AL > 0x99) || (old_FLAG_CF == 1)){ + tempAL = GR[AL]; + op1 = tempAL; + tempAL += 0x60; + res = tempAL; + GR[AL] = tempAL; + setFlag(SPR, FLAG_CF); + + checkFlags8(SPR, OPER_ADD, op1,0x60,res,FLAG_SF ); + checkFlags8(SPR, OPER_ADD, op1,0x60,res,FLAG_ZF ); + checkFlags8(SPR, OPER_ADD, op1,0x60,res,FLAG_PF ); + }//if + else + resetFlag(SPR, FLAG_CF); + + +}//ac_behavior( daa ) + + + + + +/************************************** +//!Instruction das description +Description +Adjusts the result of the subtraction of two packed BCD values to create a packed BCD result. +The AL register is the implied source and destination operand. The DAS instruction is only +useful when it follows a SUB instruction that subtracts (binary subtraction) one 2-digit, packed +BCD value from another and stores a byte result in the AL register. The DAS instruction then +adjusts the contents of the AL register to contain the correct 2-digit, packed BCD result. If a +decimal borrow is detected, the CF and AF flags are set accordingly. +**************************************/ +//!Instruction das behavior method. +void ac_behavior( das ){ + acprintf ( " DAS \n" ); + + uint tempAL,old_AL,old_FLAG_CF; + uint op1, res; //para checar Flags + old_AL = GR[AL]; + old_FLAG_CF = SPR[FLAG_CF]; + + if( ((GR[AL] & 0x0F) > 9) || (testFlag(SPR, FLAG_AF)) ){ + tempAL = GR[AL]; + op1 = tempAL; + tempAL = tempAL - 6; + res = tempAL; + GR[AL] = tempAL; + writeFlag(SPR, FLAG_CF,( old_FLAG_CF || ( checkCarry8(OPER_SUB,op1,6,0) )) ); + setFlag(SPR, FLAG_AF); + + checkFlags8(SPR, OPER_SUB, op1,6,res,FLAG_SF ); + checkFlags8(SPR, OPER_SUB, op1,6,res,FLAG_ZF ); + checkFlags8(SPR, OPER_SUB, op1,6,res,FLAG_PF ); + + }//if + else + resetFlag(SPR, FLAG_AF); + + if ((old_AL > 0x99) || (old_FLAG_CF == 1)){ + tempAL = GR[AL]; + op1 = tempAL; + tempAL = tempAL - 0x60; + res = tempAL; + GR[AL] = tempAL; + setFlag(SPR, FLAG_CF); + + checkFlags8(SPR, OPER_SUB, op1,0x60,res,FLAG_SF ); + checkFlags8(SPR, OPER_SUB, op1,0x60,res,FLAG_ZF ); + checkFlags8(SPR, OPER_SUB, op1,0x60,res,FLAG_PF ); + }//if + else + resetFlag(SPR, FLAG_CF); + + + +}//ac_behavior ( das ); + + + + + + +/* + + + + + + + +//!Instruction aam behavior method. +void ac_behavior( aam ){ + acprintf ( " AAM \n" ); +} //ac_behavior( aam ) + + + +//!Instruction aam behavior method. +void ac_behavior( aam ){ + acprintf ( " AAM \n" ); +} //ac_behavior( aam ) + + +//!Instruction aam behavior method. +void ac_behavior( aam ){ + acprintf ( " AAM \n" ); +} //ac_behavior( aam ) + + +*/ diff --git a/pdl/x86/compiler_info.ac b/pdl/x86/compiler_info.ac new file mode 100644 index 0000000..7e00ad7 --- /dev/null +++ b/pdl/x86/compiler_info.ac @@ -0,0 +1,27 @@ +//=====================-- Registers definitions --============================// + +define registers GPR:regs as ( + x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 + x17 x18 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 x31 +); + +define operand spec as size 32 like int; + +redefine operand tgtimm size to 16; + +define abi as ( + define callee save registers as (x14); + define reserved registers as (x1 x2); + define auxiliar registers as (x11); + //define calling convention for int as stack size 4 alignment 4; + define calling convention for int as (x3); + define calling convention for int as stack size 4 alignment 4; + define return convention for int as (x3 x4); + //define programcounter register as PC; + define stackpointer register as x13; + define framepointer register as x14; + define return register as LR; + define stack grows down alignment 8; + define pcoffset -8; +); + diff --git a/pharo/GNUmakefile b/pharo/GNUmakefile index 78e7150..1deae2d 100644 --- a/pharo/GNUmakefile +++ b/pharo/GNUmakefile @@ -16,12 +16,10 @@ MACHINEARITHMETIC_BRANCH ?= pure-z3 $(eval $(call git-clone-local,MACHINEARITHMETIC_DIR,$(MACHINEARITHMETIC_URL),$(MACHINEARITHMETIC_BRANCH))) endif -ifndef ARCHC_PDL_DIR -ARCHC_PDL_DIR := ../pdl -ARCHC_PDL_URL ?= https://github.com/janvrany/Pharo-ArchC-PDL.git -ARCHC_PDL_BRANCH ?= master -$(eval $(call git-clone-local,ARCHC_PDL_DIR,$(ARCHC_PDL_URL),$(ARCHC_PDL_BRANCH))) -endif +prereq:: ../pdl/riscv/riscv-opcodes/opcodes-rv32i + +../pdl/riscv/riscv-opcodes/opcodes-rv32i: + git submodule update --init --recursive $(dir $@) build: prereq $(PROJECT).image @echo "" @@ -36,10 +34,10 @@ $(PROJECT).image: ../src/*/*.st $(call pharo-load-local, $@, ArchC, ../src) run: build - ARCHC_PDL_DIR=$(ARCHC_PDL_DIR)/ $(PHARO_VM) $(PROJECT).image + $(PHARO_VM) $(PROJECT).image test: build - ARCHC_PDL_DIR=$(ARCHC_PDL_DIR)/ $(PHARO_VM_HEADLESS) $(PROJECT).image test --fail-on-failure \ + $(PHARO_VM_HEADLESS) $(PROJECT).image test --fail-on-failure \ "ArchC-Core-Tests" \ "ArchC-RISCV-Tests" \ "ArchC-DSL-Tests" diff --git a/src/ArchC-Core/AcProcessorDescriptions.class.st b/src/ArchC-Core/AcProcessorDescriptions.class.st index 3a0e14c..504de68 100644 --- a/src/ArchC-Core/AcProcessorDescriptions.class.st +++ b/src/ArchC-Core/AcProcessorDescriptions.class.st @@ -24,23 +24,13 @@ AcProcessorDescriptions class >> armv5 [ { #category : #'working directory' } AcProcessorDescriptions class >> baseDirectory [ - "Return a directory where PDLs are looked up. - - The directory is determined as follows: - - 1. environment variable named ARCHC_PDL_DIR, - if not set then - 1. `pdl` directory in local git working copy - (as created by `get-pdls.sh` script) - " + "Return a directory where PDLs are looked up." | base slash | - base := 'ARCHC_PDL_DIR' getOSEnvironment. + + base := self baseDirectoryGuess. base isNil ifTrue:[ - base := self baseDirectoryGuess. - base isNil ifTrue:[ - self error: 'Failed to guess the base directory for PDLs, please run `get-pdls.sh` or set ''ARCHC_PDL_DIR'' environment.' - ]. + self error: 'Failed to determine the base directory for PDLs.' ]. "Make sure it has a slash at the end!" @@ -57,30 +47,11 @@ AcProcessorDescriptions class >> baseDirectory [ " AcProcessorDescriptions baseDirectory " - -] - -{ #category : #'working directory' } -AcProcessorDescriptions class >> baseDirectory: aString [ - "Set directory where to look for PDLs" - - ((Smalltalk respondsTo: #isSmalltalkX) and: [ Smalltalk isSmalltalkX ]) ifTrue: [ - #OperatingSystem asClass setEnvironment: 'ARCHC_PDL_DIR' to: aString - ] ifFalse: [ - #OSEnvironment asClass current at: 'ARCHC_PDL_DIR' put: aString - ]. - - " - AcProcessorDescriptions baseDirectory: '/home/jv/Projects/Phoenix/ArchC/pdl/' - AcProcessorDescriptions baseDirectory - AcProcessorDescriptions powerpc - " - ] { #category : #'working directory' } AcProcessorDescriptions class >> baseDirectoryGuess [ - "Try to guess where the PDLs might be." + "Determine PDL directory" ((Smalltalk respondsTo: #isSmalltalkX) and: [ Smalltalk isSmalltalkX ]) ifTrue: [ @@ -115,7 +86,6 @@ AcProcessorDescriptions class >> baseDirectoryGuess [ " AcProcessorDescriptions baseDirectoryGuess " - ] { #category : #cache } diff --git a/stx/GNUmakefile b/stx/GNUmakefile index 2f818f8..47d37e0 100644 --- a/stx/GNUmakefile +++ b/stx/GNUmakefile @@ -16,12 +16,10 @@ MACHINEARITHMETIC_BRANCH ?= pure-z3 $(eval $(call git-clone-local,MACHINEARITHMETIC_DIR,$(MACHINEARITHMETIC_URL),$(MACHINEARITHMETIC_BRANCH))) endif -ifndef ARCHC_PDL_DIR -ARCHC_PDL_DIR := ../pdl -ARCHC_PDL_URL ?= https://github.com/janvrany/Pharo-ArchC-PDL.git -ARCHC_PDL_BRANCH ?= master -$(eval $(call git-clone-local,ARCHC_PDL_DIR,$(ARCHC_PDL_URL),$(ARCHC_PDL_BRANCH))) -endif +prereq:: ../pdl/riscv/riscv-opcodes/opcodes-rv32i + +../pdl/riscv/riscv-opcodes/opcodes-rv32i: + git submodule update --init --recursive $(dir $@) build: prereq @echo "To run Smalltalk/X with $(PROJECT) loaded, run:" @@ -31,14 +29,14 @@ build: prereq run: build - ARCHC_PDL_DIR=$(ARCHC_PDL_DIR)/ $(STX) \ + $(STX) \ --quick \ --package-path $(MACHINEARITHMETIC_DIR) \ --package-path ../src \ --load BaselineOf$(PROJECT) \ test: build - ARCHC_PDL_DIR=$(ARCHC_PDL_DIR)/ $(STX) \ + $(STX) \ --package-path $(MACHINEARITHMETIC_DIR) \ --package-path ../src \ --load BaselineOf$(PROJECT) \