Questions Regarding Cache Latency Configuration in MGPUSim #225
Description
I am currently using the recent versions of MGPUSim (8ef2478) and Akita (84556383eb9faf6d9d470809e823abc79be154f4), but I have encountered some confusion regarding the cache latency configuration.
In the ShaderArray setup, the L1VCache has its bank latency set to 60 cycles, whereas both L1SCache and L1ICache are configured with only 1 cycle. Additionally, the L2 Cache bank latency is only 20 cycles, and the directory latency is set to 0.
These values seem quite different from what I have seen in prior works. Most papers configure GPU cache hierarchies with L1 latencies around 20–30 cycles and L2 latencies around 160–200 cycles, for example, in “Marching Page Walks: Batching and Concurrent Page Table Walks for Enhancing GPU Throughput.”
Could you please help me understand the reasoning behind these parameter choices? Are these values intended to represent simplified timing models, or are they calibrated against specific hardware or frequency assumptions?