Restructure is an interface to ABC for local resynthesis. The package allows
logic restructuring that targets area or timing. It extracts a cloud of logic
using the OpenSTA timing engine, and passes it to ABC through blif interface.
Multiple recipes for area or timing are run to obtain multiple structures from ABC;
the most desirable among these is used to improve the netlist.
The ABC output is read back by a blif reader which is integrated to OpenDB.
blif writer and reader also support constants from and to OpenDB. Reading
back of constants requires insertion of tie cells which should be provided
by the user as per the interface described below.
Restructuring can be done in two modes: area or delay.
restructure -liberty_file <liberty_file>
-target "area"
-tielo_pin <tielo_pin_name>
-tiehi_pin <tiehi_pin_name>
restructure -liberty_file <liberty_file>
-target "delay"
-slack_threshold <slack_val>
-depth_threshold <depth_threshold>
-tielo_pin <tielo_pin_name>
-tiehi_pin <tiehi_pin_name>
Argument Description:
liberty_fileLiberty file with description of cells used in design. This is passed to ABC.targetcould be area or delay. In area mode, the focus is area reduction and timing may degrade. In delay mode, delay is likely reduced but area may increase.-slack_thresholdspecifies a (setup) timing slack value below which timing paths need to be analyzed for restructuring.-depth_thresholdspecifies the path depth above which a timing path would be considered for restructuring.tielo_pinspecifies the tie cell pin which can drive constant zero. Format is lib/cell/pintiehi_pinspecifies the tie cell pin which can drive constant one. Format is lib/cell/pin
Check out GitHub discussion about this tool.
- Sanjiv Mathur
- Ahmad El Rouby
BSD 3-Clause License. See LICENSE file.