Merge pull request #224 from szediwy/master

Lesson 2 - Exercise 2 & Lesson 3 - Exercise 1,2

exercises/lesson02/2/szediwy/Makefile

@@ -0,0 +1,34 @@
+ARMGNU ?= aarch64-linux-gnu
+
+COPS = -Wall -nostdlib -nostartfiles -ffreestanding -Iinclude
+ASMOPS = -Iinclude 
+
+BUILD_DIR = build
+SRC_DIR = src
+
+.PHONY: clean
+
+all : kernel8.img
+
+clean :
+	rm -rf $(BUILD_DIR) *.img
+	@echo "clean: [SUCCESS]"
+
+$(BUILD_DIR)/%_c.o: $(SRC_DIR)/%.c
+	mkdir -p $(@D)
+	$(ARMGNU)-gcc $(COPS) -MMD -c $< -o $@
+
+$(BUILD_DIR)/%_s.o: $(SRC_DIR)/%.S
+	$(ARMGNU)-gcc $(ASMOPS) -MMD -c $< -o $@
+
+C_FILES = $(wildcard $(SRC_DIR)/*.c)
+ASM_FILES = $(wildcard $(SRC_DIR)/*.S)
+OBJ_FILES = $(C_FILES:$(SRC_DIR)/%.c=$(BUILD_DIR)/%_c.o)
+OBJ_FILES += $(ASM_FILES:$(SRC_DIR)/%.S=$(BUILD_DIR)/%_s.o)
+
+DEP_FILES = $(OBJ_FILES:%.o=%.d)
+-include $(DEP_FILES)
+
+kernel8.img: $(SRC_DIR)/linker.ld $(OBJ_FILES)
+	$(ARMGNU)-ld -T $(SRC_DIR)/linker.ld -o $(BUILD_DIR)/kernel8.elf  $(OBJ_FILES)
+	$(ARMGNU)-objcopy $(BUILD_DIR)/kernel8.elf -O binary kernel8.img

exercises/lesson02/2/szediwy/build.bat

@@ -0,0 +1 @@
+docker run --rm -v %cd%:/app -w /app smatyukevich/raspberry-pi-os-builder make %1

exercises/lesson02/2/szediwy/build.sh

@@ -0,0 +1,3 @@
+#!/bin/bash
+
+docker run --rm -v $(pwd):/app -w /app smatyukevich/raspberry-pi-os-builder make $1

exercises/lesson02/2/szediwy/include/custom_printf.h

@@ -0,0 +1,108 @@
+/*
+File: printf.h
+
+Copyright (C) 2004  Kustaa Nyholm
+
+This library is free software; you can redistribute it and/or
+modify it under the terms of the GNU Lesser General Public
+License as published by the Free Software Foundation; either
+version 2.1 of the License, or (at your option) any later version.
+
+This library is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+See the GNU Lesser General Public License for more details.
+
+You should have received a copy of the GNU Lesser General Public
+License along with this library; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+This library is really just two files: 'printf.h' and 'printf.c'.
+
+They provide a simple and small (+200 loc) printf functionality to
+be used in embedded systems.
+
+I've found them so usefull in debugging that I do not bother with a
+debugger at all.
+
+They are distributed in source form, so to use them, just compile them
+into your project.
+
+Two printf variants are provided: printf and sprintf.
+
+The formats supported by this implementation are: 'd' 'u' 'c' 's' 'x' 'X'.
+
+Zero padding and field width are also supported.
+
+If the library is compiled with 'PRINTF_SUPPORT_LONG' defined then the
+long specifier is also
+supported. Note that this will pull in some long math routines (pun intended!)
+and thus make your executable noticably longer.
+
+The memory foot print of course depends on the target cpu, compiler and
+compiler options, but a rough guestimate (based on a H8S target) is about
+1.4 kB for code and some twenty 'int's and 'char's, say 60 bytes of stack space.
+Not too bad. Your milage may vary. By hacking the source code you can
+get rid of some hunred bytes, I'm sure, but personally I feel the balance of
+functionality and flexibility versus  code size is close to optimal for
+many embedded systems.
+
+To use the printf you need to supply your own character output function,
+something like :
+
+	void putc ( void* p, char c)
+		{
+		while (!SERIAL_PORT_EMPTY) ;
+		SERIAL_PORT_TX_REGISTER = c;
+		}
+
+Before you can call printf you need to initialize it to use your
+character output function with something like:
+
+	init_printf(NULL,putc);
+
+Notice the 'NULL' in 'init_printf' and the parameter 'void* p' in 'putc',
+the NULL (or any pointer) you pass into the 'init_printf' will eventually be
+passed to your 'putc' routine. This allows you to pass some storage space (or
+anything really) to the character output function, if necessary.
+This is not often needed but it was implemented like that because it made
+implementing the sprintf function so neat (look at the source code).
+
+The code is re-entrant, except for the 'init_printf' function, so it
+is safe to call it from interupts too, although this may result in mixed output.
+If you rely on re-entrancy, take care that your 'putc' function is re-entrant!
+
+The printf and sprintf functions are actually macros that translate to
+'tfp_printf' and 'tfp_sprintf'. This makes it possible
+to use them along with 'stdio.h' printf's in a single source file.
+You just need to undef the names before you include the 'stdio.h'.
+Note that these are not function like macros, so if you have variables
+or struct members with these names, things will explode in your face.
+Without variadic macros this is the best we can do to wrap these
+fucnction. If it is a problem just give up the macros and use the
+functions directly or rename them.
+
+For further details see source code.
+
+regs Kusti, 23.10.2004
+*/
+
+
+#ifndef __TFP_PRINTF__
+#define __TFP_PRINTF__
+
+#include <stdarg.h>
+
+void init_printf(void* putp,void (*putf) (void*,char));
+
+void tfp_printf(char *fmt, ...);
+void tfp_sprintf(char* s,char *fmt, ...);
+
+void tfp_format(void* putp,void (*putf) (void*,char),char *fmt, va_list va);
+
+void test (char c);
+
+#define printf tfp_printf
+#define sprintf tfp_sprintf
+
+#endif

exercises/lesson02/2/szediwy/include/entry.h

@@ -0,0 +1,26 @@
+#ifndef _ENTRY_H
+#define _ENTRY_H
+
+#define S_FRAME_SIZE			256 		// size of all saved registers 
+
+#define SYNC_INVALID_EL1t		0 
+#define IRQ_INVALID_EL1t		1 
+#define FIQ_INVALID_EL1t		2 
+#define ERROR_INVALID_EL1t		3 
+
+#define SYNC_INVALID_EL1h		4 
+#define IRQ_INVALID_EL1h		5 
+#define FIQ_INVALID_EL1h		6 
+#define ERROR_INVALID_EL1h		7 
+
+#define SYNC_INVALID_EL0_64	    8 
+#define IRQ_INVALID_EL0_64	    9 
+#define FIQ_INVALID_EL0_64		10 
+#define ERROR_INVALID_EL0_64	11 
+
+#define SYNC_INVALID_EL0_32		12 
+#define IRQ_INVALID_EL0_32		13 
+#define FIQ_INVALID_EL0_32		14 
+#define ERROR_INVALID_EL0_32	15 
+
+#endif

exercises/lesson02/2/szediwy/include/irq.h

@@ -0,0 +1,10 @@
+#ifndef	_IRQ_H
+#define	_IRQ_H
+
+void enable_interrupt_controller( void );
+
+void irq_vector_init( void );
+void enable_irq( void );
+void disable_irq( void );
+
+#endif  /*_IRQ_H */

exercises/lesson02/2/szediwy/include/mini_uart.h

@@ -0,0 +1,10 @@
+#ifndef _MINI_UART_H
+#define _MINI_UART_H
+
+void uart_init(void);
+char uart_recv(void);
+void uart_send(char c);
+void uart_send_string(char *str);
+void putc(void *p, char c);
+
+#endif /*_MINI_UART_H */

exercises/lesson02/2/szediwy/include/mm.h

@@ -0,0 +1,19 @@
+#ifndef	_MM_H
+#define	_MM_H
+
+#define PAGE_SHIFT	 		    12
+#define TABLE_SHIFT 			9
+#define SECTION_SHIFT			(PAGE_SHIFT + TABLE_SHIFT)
+
+#define PAGE_SIZE   			(1 << PAGE_SHIFT)	
+#define SECTION_SIZE			(1 << SECTION_SHIFT)	
+
+#define LOW_MEMORY              (2 * SECTION_SIZE)
+
+#ifndef __ASSEMBLER__
+
+void memzero(unsigned long src, unsigned long n);
+
+#endif
+
+#endif  /*_MM_H */

exercises/lesson02/2/szediwy/include/peripherals/base.h

@@ -0,0 +1,20 @@
+#ifndef	_P_BASE_H
+#define	_P_BASE_H
+
+// #define PBASE 0x3F000000
+// So a peripheral described in this document as being at legacy address 0x7Enn_nnnn is available in the 35-bit address
+// space at 0x4_7Enn_nnnn, and visible to the ARM at 0x0_FEnn_nnnn if Low Peripheral mode is enabled.
+// 0x7E000000 (legacy) -> 0x4_7E00_0000 (35-bit) -> 0x0_FE00_0000 (low peripheral)
+#define PBASE 0xFE000000
+
+// The base address of the GIC-400 is 0x4c0040000. Note that, unlike other peripheral addresses in this document, this is an
+// ARM-only address and not a legacy master address. If Low Peripheral mode is enabled this base address becomes
+// 0xff840000.
+// The GIC-400 is configured with "NUM_CPUS=4" and "NUM_SPIS=192". For full register details, please refer to the ARM
+// GIC-400 documentation on the ARM Developer website.
+#define GIC_BASE 0xFF840000
+
+// The ARMC register base address is 0x7e00b000 -> 0x4_7E00B000 -> 0x0FE00B000
+#define ARMC_BASE 0x0FE00B000
+
+#endif  /*_P_BASE_H */

exercises/lesson02/2/szediwy/include/peripherals/gpio.h

@@ -0,0 +1,20 @@
+#ifndef	_P_GPIO_H
+#define	_P_GPIO_H
+
+#include "peripherals/base.h"
+
+#define GPFSEL1         (PBASE+0x00200004)
+// #define GPSET0          (PBASE+0x0020001C)
+// #define GPCLR0          (PBASE+0x00200028)
+// #define GPPUD           (PBASE+0x00200094)
+// #define GPPUDCLK0       (PBASE+0x00200098)
+#define GPIO_PUP_PDN_CNTRL_REG0 (PBASE+0x002000E4)
+#define UART0_DR                (PBASE+0x00201000)
+#define UART0_FR                (PBASE+0x00201018)
+#define UART0_IBRD              (PBASE+0x00201024)
+#define UART0_FBRD              (PBASE+0x00201028)
+#define UART0_LCRH              (PBASE+0x0020102C)
+#define UART0_CR                (PBASE+0x00201030)
+#define UART0_IMSC              (PBASE+0x00201038)
+
+#endif  /*_P_GPIO_H */

exercises/lesson02/2/szediwy/include/peripherals/irq.h

@@ -0,0 +1,23 @@
+#ifndef	_P_IRQ_H
+#define	_P_IRQ_H
+
+#include "peripherals/base.h"
+
+#define IRQ_PENDING_0_CORE_0   	    (PBASE+0x0000B200)
+#define IRQ_PENDING_1_CORE_0		(PBASE+0x0000B204)
+#define IRQ_PENDING_2_CORE_0		(PBASE+0x0000B208)
+//#define FIQ_CONTROL		    (PBASE+0x0000B20C)
+#define ENABLE_IRQS_0_CORE_0		(PBASE+0x0000B210)
+#define ENABLE_IRQS_1_CORE_0		(PBASE+0x0000B214)
+#define ENABLE_IRQS_2_CORE_0		(PBASE+0x0000B218)
+
+#define DISABLE_IRQS_0_CORE_0		(PBASE+0x0000B220)
+#define DISABLE_IRQS_1_CORE_0		(PBASE+0x0000B224)
+#define DISABLE_IRQS_2_CORE_0		(PBASE+0x0000B228)
+
+#define SYSTEM_TIMER_IRQ_0	(1 << 0)
+#define SYSTEM_TIMER_IRQ_1	(1 << 1)
+#define SYSTEM_TIMER_IRQ_2	(1 << 2)
+#define SYSTEM_TIMER_IRQ_3	(1 << 3)
+
+#endif  /*_P_IRQ_H */

exercises/lesson02/2/szediwy/include/peripherals/mini_uart.h

@@ -0,0 +1,19 @@
+#ifndef	_P_MINI_UART_H
+#define	_P_MINI_UART_H
+
+#include "peripherals/base.h"
+
+#define AUX_ENABLES     (PBASE+0x00215004)
+#define AUX_MU_IO_REG   (PBASE+0x00215040)
+#define AUX_MU_IER_REG  (PBASE+0x00215044)
+#define AUX_MU_IIR_REG  (PBASE+0x00215048)
+#define AUX_MU_LCR_REG  (PBASE+0x0021504C)
+#define AUX_MU_MCR_REG  (PBASE+0x00215050)
+#define AUX_MU_LSR_REG  (PBASE+0x00215054)
+#define AUX_MU_MSR_REG  (PBASE+0x00215058)
+#define AUX_MU_SCRATCH  (PBASE+0x0021505C)
+#define AUX_MU_CNTL_REG (PBASE+0x00215060)
+#define AUX_MU_STAT_REG (PBASE+0x00215064)
+#define AUX_MU_BAUD_REG (PBASE+0x00215068)
+
+#endif  /*_P_MINI_UART_H */

exercises/lesson02/2/szediwy/include/peripherals/timer.h

@@ -0,0 +1,19 @@
+#ifndef	_P_TIMER_H
+#define	_P_TIMER_H
+
+#include "peripherals/base.h"
+
+#define TIMER_CS        (PBASE+0x00003000)
+#define TIMER_CLO       (PBASE+0x00003004)
+#define TIMER_CHI       (PBASE+0x00003008)
+#define TIMER_C0        (PBASE+0x0000300C)
+#define TIMER_C1        (PBASE+0x00003010)
+#define TIMER_C2        (PBASE+0x00003014)
+#define TIMER_C3        (PBASE+0x00003018)
+
+#define TIMER_CS_M0	(1 << 0)
+#define TIMER_CS_M1	(1 << 1)
+#define TIMER_CS_M2	(1 << 2)
+#define TIMER_CS_M3	(1 << 3)
+
+#endif  /*_P_TIMER_H */

exercises/lesson02/2/szediwy/include/sysregs.h

@@ -0,0 +1,55 @@
+#ifndef _SYSREGS_H
+#define _SYSREGS_H
+
+// ***************************************
+// SCTLR_EL1, System Control Register (EL1), Page 2654 of AArch64-Reference-Manual.
+// ***************************************
+
+#define SCTLR_RESERVED                  (3 << 28) | (3 << 22) | (1 << 20) | (1 << 11)
+#define SCTLR_EE_LITTLE_ENDIAN          (0 << 25)
+#define SCTLR_EOE_LITTLE_ENDIAN         (0 << 24)
+#define SCTLR_I_CACHE_DISABLED          (0 << 12)
+#define SCTLR_D_CACHE_DISABLED          (0 << 2)
+#define SCTLR_MMU_DISABLED              (0 << 0)
+#define SCTLR_MMU_ENABLED               (1 << 0)
+
+#define SCTLR_VALUE_MMU_DISABLED	(SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_I_CACHE_DISABLED | SCTLR_D_CACHE_DISABLED | SCTLR_MMU_DISABLED)
+
+// ***************************************
+// HCR_EL2, Hypervisor Configuration Register (EL2), Page 2487 of AArch64-Reference-Manual.
+// ***************************************
+
+#define HCR_RW	    		(1 << 31)
+#define HCR_VALUE			HCR_RW
+
+// ***************************************
+// SCR_EL3, Secure Configuration Register (EL3), Page 2648 of AArch64-Reference-Manual.
+// ***************************************
+
+#define SCR_RESERVED	    (3 << 4)
+#define SCR_RW				(1 << 10)
+#define SCR_NS				(1 << 0)
+#define SCR_VALUE	    	(SCR_RESERVED | SCR_RW | SCR_NS)
+
+// ***************************************
+// SPSR_EL3, Saved Program Status Register (EL3) Page 389 of AArch64-Reference-Manual.
+// ***************************************
+
+#define SPSR_MASK_ALL 	(7 << 6)
+#define SPSR_EL1h			  (5 << 0)
+#define SPSR_VALUE			(SPSR_MASK_ALL | SPSR_EL1h)
+
+#define BYTE_TO_BINARY_PATTERN "%c%c%c%c%c%c%c%c"
+#define BYTE_TO_BINARY(byte)  \
+  (byte & 0x80 ? '1' : '0'), \
+  (byte & 0x40 ? '1' : '0'), \
+  (byte & 0x20 ? '1' : '0'), \
+  (byte & 0x10 ? '1' : '0'), \
+  (byte & 0x08 ? '1' : '0'), \
+  (byte & 0x04 ? '1' : '0'), \
+  (byte & 0x02 ? '1' : '0'), \
+  (byte & 0x01 ? '1' : '0') 
+
+#define CPACR_EL1_MASK (1 << 28 | 3 << 20 | 3 << 16)
+
+#endif

exercises/lesson02/2/szediwy/include/timer.h

@@ -0,0 +1,7 @@
+#ifndef	_TIMER_H
+#define	_TIMER_H
+
+void timer_init ( void );
+void handle_timer_irq ( void );
+
+#endif  /*_TIMER_H */