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1 parent 6341f50 commit 783b632Copy full SHA for 783b632
rp235x-hal/src/arch.rs
@@ -123,6 +123,17 @@ mod inner {
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riscv::register::mstatus::read().mie()
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}
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+ /// Enable co-processors.
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+ ///
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+ /// The riscv core in rp2350 does not have any co-processors.
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+ /// As such, this function does nothing, and only exists to
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+ /// provide compatibility between arm and riscv targets.
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+ /// # Safety
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+ /// No safety requirements for riscv targets, as this function does nothing.
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+ pub unsafe fn enable_coprocessors() {}
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+
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#[no_mangle]
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#[allow(non_snake_case)]
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fn MachineExternal() {
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