Skip to content

Commit 9d5de2f

Browse files
SRausSRaus
committed
Update Vivado version to 2020.2
Update vivado version to 2020.2: - update default vivado version from 2020.1 to 2020.2 - add conditions to apply specific contraints only in Out Of Context mode. - update DDR controler parameters for vcu118 and kcu105 dev boards
1 parent 907b750 commit 9d5de2f

File tree

9 files changed

+20
-13
lines changed

9 files changed

+20
-13
lines changed

‎library/scripts/adi_ip_xilinx.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
44
# check tool version
55

66
if {![info exists REQUIRED_VIVADO_VERSION]} {
7-
set REQUIRED_VIVADO_VERSION "2020.1"
7+
set REQUIRED_VIVADO_VERSION "2020.2"
88
}
99

1010
if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {

‎library/xilinx/axi_xcvrlb/axi_xcvrlb.v‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -39,10 +39,10 @@ module axi_xcvrlb #(
3939

4040
// parameters
4141

42-
parameter CPLL_FBDIV = 1,
43-
parameter CPLL_FBDIV_4_5 = 5,
42+
parameter integer CPLL_FBDIV = 1,
43+
parameter integer CPLL_FBDIV_4_5 = 5,
4444
parameter NUM_OF_LANES = 1,
45-
parameter XCVR_TYPE = 2) (
45+
parameter integer XCVR_TYPE = 2) (
4646

4747
// transceiver interface
4848

‎library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,10 @@ adi_ip_properties_lite axi_xcvrlb
1717
adi_init_bd_tcl
1818
adi_ip_bd axi_xcvrlb "bd/bd.tcl"
1919

20+
adi_ip_add_core_dependencies { \
21+
analog.com:user:util_cdc:1.0 \
22+
}
23+
2024
ipx::remove_all_bus_interface [ipx::current_core]
2125

2226
set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]

‎library/xilinx/util_adxcvr/util_adxcvr_constr.xdc‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11

2-
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
3-
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
4-
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_rate*}]
5-
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *tx_rate*}]
2+
set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
3+
set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
4+
set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *rx_rate*}]
5+
set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *tx_rate*}]
66

77
set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
88
set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]

‎projects/ad9082_fmca_ebz/vcu118/system_project.tcl‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,11 @@ adi_project_files ad9082_fmca_ebz_vcu118 [list \
5353
"$ad_hdl_dir/library/common/ad_iobuf.v" \
5454
"$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" ]
5555

56+
# Avoid critical warning in OOC mode from the clock definitions
57+
# since at that stage the submodules are not stiched together yet
58+
if {$ADI_USE_OOC_SYNTHESIS == 1} {
59+
set_property used_in_synthesis false [get_files timing_constr.xdc]
60+
}
5661

5762
adi_project_run ad9082_fmca_ebz_vcu118
5863

‎projects/common/kcu105/kcu105_system_bd.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,7 @@ ad_ip_parameter sys_200m_rstgen CONFIG.C_EXT_RST_WIDTH 1
7575

7676
ad_ip_instance ip:ddr4 axi_ddr_cntrl
7777
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_CLOCK_BOARD_INTERFACE default_sysclk_300
78-
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_DDR4_BOARD_INTERFACE ddr4_sdram
78+
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_DDR4_BOARD_INTERFACE ddr4_sdram_DR
7979
ad_ip_parameter axi_ddr_cntrl CONFIG.RESET_BOARD_INTERFACE reset
8080
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ 200
8181

‎projects/common/kcu105/kcu105_system_constr.xdc‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -50,8 +50,6 @@ set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 44]
5050
set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 45]
5151
set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 46]
5252

53-
create_clock -name phy_clk -period 1.60 [get_ports phy_clk_p]
54-
5553
#Setting the Configuration Bank Voltage Select
5654
set_property CFGBVS GND [current_design]
5755
set_property CONFIG_VOLTAGE 1.8 [current_design]

‎projects/common/vcu118/vcu118_system_bd.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ ad_ip_parameter sys_500m_rstgen CONFIG.C_EXT_RST_WIDTH 1
7878

7979
ad_ip_instance ip:ddr4 axi_ddr_cntrl
8080
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_CLOCK_BOARD_INTERFACE default_250mhz_clk2
81-
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_DDR4_BOARD_INTERFACE ddr4_sdram_c2
81+
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_DDR4_BOARD_INTERFACE ddr4_sdram_c2_083
8282
ad_ip_parameter axi_ddr_cntrl CONFIG.RESET_BOARD_INTERFACE reset
8383
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ 250
8484
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 500

‎projects/scripts/adi_project_xilinx.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11

22
## Define the supported tool version
33
if {![info exists REQUIRED_VIVADO_VERSION]} {
4-
set REQUIRED_VIVADO_VERSION "2020.1"
4+
set REQUIRED_VIVADO_VERSION "2020.2"
55
}
66

77
## Define the ADI_IGNORE_VERSION_CHECK environment variable to skip version check

0 commit comments

Comments
 (0)