how to understand bit 63 in mstateen0 is defined to control access to the matching sstateen and hstateen CSRs?

[ZeyueShen]

In spec：
https://github.com/riscvarchive/riscv-state-enable/blob/main/content.adoc

It describes that access to hstateen0 csr is controlled by mstateen0[63], but does not specify whether failure to access will result in an exception. Similarly, access to sstateen0 csr is controlled by hstateen0[63], and there is no mention of non-access handling.

But in spike:

It means that when mstateen0[63] is zero, access to hstateen0 in privileged mode less than m mode will cause an illegal instruction exception.

It means that when mstateen0[63] & hstateen0[63] is zero, accessing sstateen0 in virtualization mode causes a virtual instruction exception.

So can you describe in detail the controlled access of hstateen0 and sstateen0? I am looking forward to your answer!

[gfavor]

The spec (section 4.1) says:

"when a stateen CSR prevents access to state by less privileged levels, an attempt in one of those privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction exception, or, if executing in VS or VU mode
and the circumstances for a virtual instruction exception apply, raises a virtual instruction exception
instead of an illegal instruction exception."

[ZeyueShen]

ok, Thanks for your reply!