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RTL pass fail to tell value used is constant #271
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hmmm ... what would the ideal Verilog be though? Should we turn clog2 into |
Or try to evaluate the expression, replace it with a constant int value, and catch it only when the evaluated result is not int. To aid readability, we can add a comment next to the evaluated number to indicate this is coming from an evaluated expression. |
Interesting idea! I don't think we do any of that currently ... we don't do any kind of constant evaluation during translation ... it is very much a source-to-source transpilation process ... |
If this is fully implemented, one main advantage would be that more native constructs like A simple case use I can think of is we can convert the following
to
|
But to be clear you can definitely do what you are showing above at elaboration time outside an update block ... you just cannot do it in an update block ... this idea of partial evaluation during translation of an update block seems like an interest research direction! |
We definitely have some degree of partial evaluation during the translation pass. For example, the free variable Again, like Chris mentioned above, you can totally use any Python constructs or advanced syntaxes for structural composition outside the update block. |
The
VerilogTranslationPass
fail to tell the value used is a constant.will produce the following error
I can fix the problem by doing the following
But it is more intuitive to do it the first way.
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