Pulp CDC constraints fixup on FPGA, remote boot in device-tree, add cva6-sdk subrepo (#261)

* fpga: Correct pulp island CDC constraints

* fpga: Select mac_addr by env variable

* fpga: Add safety+spatz config and correct jtag chain

* sdk: Update cva6-sdk with https buildroot dependancy

* carfield.mk: Update CI hash

Author: CyrilKoe

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "sw/deps/cva6-sdk"]
+	path = sw/deps/cva6-sdk
+	url = https://github.com/pulp-platform/cva6-sdk.git

Bender.yml

@@ -59,6 +59,10 @@ sources:
     files:
       - hw/configs/carfield_l2dual_safe_periph.sv
 
+  - target: carfield_l2dual_safe_spatz_periph
+    files:
+      - hw/configs/carfield_l2dual_safe_spatz_periph.sv
+
   - target: carfield_l2dual_spatz_periph
     files:
       - hw/configs/carfield_l2dual_spatz_periph.sv

carfield.mk

@@ -44,7 +44,7 @@ include $(CAR_ROOT)/bender-safed.mk
 ######################
 
 CAR_NONFREE_REMOTE ?= [email protected]:carfield/carfield-nonfree.git
-CAR_NONFREE_COMMIT ?= 54ce7e49
+CAR_NONFREE_COMMIT ?= 59e53134
 
 ## @section Carfield platform nonfree components
 ## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC

docs/tg/xilinx.md

@@ -60,9 +60,9 @@ See below some typical building time for reference:
 
 | Config                                 | Board  | Duration   |
 |----------------------------------------|--------|------------|
-| carfield_l2dual_pulp_periph            | vcu128 | __ISSUE__  |
-| carfield_l2dual_safe_periph            | vcu128 | 6h01min    |
-| carfield_l2dual_spatz_periph           | vcu128 | 3h31min    |
+| carfield_l2dual_pulp_periph            | vcu128 | ~5h        |
+| carfield_l2dual_safe_periph            | vcu128 | ~5h        |
+| carfield_l2dual_spatz_periph           | vcu128 | ~5h        |
 | carfield_l2dual_secure_periph          | vcu128 | __ISSUE__  |
 
 You can find which sources are used by looking at `Bender.yml` (target `all(xilinx, fpga,
@@ -104,14 +104,15 @@ See the argument list below:
 | GEN_EXT_JTAG    | vcu128    | `0` Connect the JTAG debugger to the board's JTAG (see [vcu128](#xilinx-vcu128)) <br>`1` Connect the JTAG debugger to an external JTAG chain |
 | CARFIELD_CONFIG | all       | Select the Carfield configuration to implement. See below for supported configs.                                                      |
 | VIVADO_MODE     | all       | `batch` Compile in Vivado shell<br>`gui` Compile in Vivado gui                                                                        |
+| XILINX_BOOT_ETH | all       | `0` Boot via SPI flash only (see [booting Linux](#booting_linux)) <br>`1` Boot via SPI flash and Ethernet                             |
 
 See below some typical building time for reference:
 
 | Config                                 | Board  | Duration   |
 |----------------------------------------|--------|------------|
-| carfield_l2dual_pulp_periph            | vcu128 | __ISSUE__  |
-| carfield_l2dual_safe_periph            | vcu128 | 3h49min    |
-| carfield_l2dual_spatz_periph           | vcu128 | 5h40min    |
+| carfield_l2dual_pulp_periph            | vcu128 | ~5h        |
+| carfield_l2dual_safe_periph            | vcu128 | ~5h        |
+| carfield_l2dual_spatz_periph           | vcu128 | ~5h        |
 | carfield_l2dual_secure_periph          | vcu128 | __ISSUE__  |
 
 You can find which sources are used by looking at `Bender.yml` (target `all(xilinx, fpga,
@@ -124,6 +125,10 @@ Note that the `make` command above will first package a Carfield ip before compi
 
 ## Board specificities
 
+### All
+> #### Ethernet
+> As the MAC address of each FPGA is unique (but reconfigurable), if you wish to use the Ethernet
+> IP (`bd` flavor) you will need to add the MAC address of your board in `sw/boot/mac_address.dtsi`.
 ### Xilinx VCU128
 > #### Bootmodes and VIOs
 >
@@ -198,10 +203,6 @@ Tbd
 
 Tbd
 
-### JTAG Preloading
-
-Tbd
-
 ## Booting Linux
 
 To boot Linux, we must load the *OpenSBI* firmware, which takes over M mode and launches the U-boot
@@ -211,8 +212,8 @@ Clone the `carfield` branch of CVA6 SDK at the root of this repository and build
 (OpenSBI + U-boot) and Linux images (*this will take about 30 minutes*):
 
 ```bash
-git clone https://github.com/pulp-platform/cva6-sdk.git --branch carfield
-make -C cva6-sdk images
+git submodule update --init --recursive sw/deps/cva6-sdk
+make -C sw/deps/cva6-sdk images
 ```
 
 In principle, we can boot Linux through JTAG by loading all images into memory, launching OpenSBI,
@@ -227,16 +228,14 @@ To create a full Linux disk image from the ZSL, device tree, firmware, and Linux
 
 ```bash
 # Place the cva6-sdk where they are expected:
-ln -s cva6-sdk/install64 sw/boot/install64
-# Optional: Pre-uild explicitely the image
+ln -s sw/deps/cva6-sdk/install64 sw/boot/install64
+# Optional: Pre-build explicitely the image
 make CAR_ROOT=. sw/boot/linux_carfield_bd_vcu128.gpt.bin
 ```
 
-You can now recompile the board, it should start booting automatically!
-
-### Xilinx VCU128
+### Via SPI flash
 >
-> This board does not offer a SD card reader. We need to load the image in the
+> Boards like VCU128 does not offer a SD card reader. We need to load the image in the
 integrated flash:
 >
 > ```
@@ -248,6 +247,21 @@ integrated flash:
 >
 > This script will erase your bitstream, once the flash has been written (c.a.
 10min) you will need to re-program the bitstream on the board.
+> You can attach the UART port of the FPGA to minicom and see the boot process! 
+### Via Ethernet
+>
+> As flashing and reading the kernel from SPI can take a few minutes, a faster way is to
+> [ask U-Boot to fetch the image from the network](https://www.emcraft.com/som/using-dhcp).
+> This feature can be enabled in the Carfield `bd` flavor. You will need to add the MAC
+> address of your FPGA in `sw/boot/mac_address.dtsi` and the path to your Linux image (on a FTP server)
+> in `sw/boot/remote_boot.dtsi`.
+> You will still need to flash u-boot but it will be now faster:
+> ```
+> make chs-xil-flash VIVADO_MODE=batch XILINX_BOARD=vcu128 XILINX_FLAVOR=bd XILINX_BOOT_ETH=1
+> ```
+### Via Ethernet
+
+Tbd
 
 ## Add your own board
 

hw/carfield.sv

@@ -1288,7 +1288,7 @@ else begin : gen_no_safety_island
   assign safed_secd_mbox_intr = '0;
 
   assign safed_dbg_reqs = '0;
-  assign jtag_safety_island_tdo_o = '0;
+  assign jtag_safety_island_tdo_o = jtag_safety_island_tdi_i;
 end
 
 // PULP integer cluster
@@ -1756,7 +1756,7 @@ end else begin : gen_no_secure_subsystem
   assign car_regs_hw2reg.security_island_isolate_status.d = '0;
   assign car_regs_hw2reg.security_island_isolate_status.de = '0;
 
-  assign jtag_ot_tdo_o = '0;
+  assign jtag_ot_tdo_o = jtag_ot_tdi_i;
 end
 
 // Mailbox unit

hw/configs/carfield_l2dual_safe_spatz_periph.sv

@@ -0,0 +1,84 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Yvan Tortorella <[email protected]>
+
+package carfield_configuration;
+
+import cheshire_pkg::*;
+/*********************
+ * AXI Configuration *
+ ********************/
+//L2, port 0
+localparam bit     L2Port0Enable = 1;
+localparam doub_bt L2Port0Base = 'h78000000;
+localparam doub_bt L2Port0Size = 'h00200000;
+// L2, port 1
+localparam bit     L2Port1Enable = 1;
+localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size;
+localparam doub_bt L2Port1Size = L2Port0Size;
+// Safety Island
+localparam bit     SafetyIslandEnable = 1;
+localparam doub_bt SafetyIslandBase = 'h60000000;
+localparam doub_bt SafetyIslandSize = 'h00800000;
+// Ethernet
+localparam bit     EthernetEnable = 0;
+localparam doub_bt EthernetBase = 'h20000000;
+localparam doub_bt EthernetSize = 'h00001000;
+// Peripherals
+localparam bit     PeriphEnable = 1;
+localparam doub_bt PeriphBase = 'h20001000;
+localparam doub_bt PeriphSize = 'h00009000;
+// Spatz cluster
+localparam bit     SpatzClusterEnable = 1;
+localparam doub_bt SpatzClusterBase = 'h51000000;
+localparam doub_bt SpatzClusterSize = 'h00800000;
+// PULP cluster
+localparam bit     PulpClusterEnable = 0;
+localparam doub_bt PulpClusterBase = 'h50000000;
+localparam doub_bt PulpClusterSize = 'h00800000;
+// Security Island
+localparam bit     SecurityIslandEnable = 0;
+localparam doub_bt SecurityIslandBase = 'h0;
+localparam doub_bt SecurityIslandSize = 'h0;
+// Mailbox
+localparam bit     MailboxEnable = 1;
+localparam doub_bt MailboxBase = 'h40000000;
+localparam doub_bt MailboxSize = 'h00001000;
+// Can
+localparam bit CanEnable = 0;
+localparam doub_bt CanBase = 'h20001000;
+localparam doub_bt CanSize = 'h00001000;
+// System Timer
+localparam doub_bt SystemTimerBase = 'h20004000;
+localparam doub_bt SystemTimerSize = 'h00001000;
+// System Advanced Timer
+localparam doub_bt SystemAdvancedTimerBase = 'h20005000;
+localparam doub_bt SystemAdvancedTimerSize = 'h00001000;
+// System Watchdog
+localparam doub_bt SystemWatchdogBase = 'h20007000;
+localparam doub_bt SystemWatchdogSize = 'h00001000;
+// Hyperbus Config
+localparam doub_bt HyperBusBase = 'h20009000;
+localparam doub_bt HyperBusSize = 'h00001000;
+/************************
+ * RegBus Configuration *
+ ***********************/
+// Platform control registers
+localparam doub_bt PcrsBase = 'h20010000;
+localparam doub_bt PcrsSize = 'h00001000;
+// PLL
+localparam bit     PllCfgEnable = 1;
+localparam doub_bt PllCfgBase = 'h20020000;
+localparam doub_bt PllCfgSize = 'h00001000;
+// Padframe
+localparam bit     PadframeCfgEnable = 1;
+localparam doub_bt PadframeCfgBase = 'h200A0000;
+localparam doub_bt PadframeCfgSize = 'h00001000;
+// L2 ECC
+localparam bit     L2EccCfgEnable = 1;
+localparam doub_bt L2EccCfgBase = 'h200B0000;
+localparam doub_bt L2EccCfgSize = 'h00001000;
+
+endpackage

sw/boot/carfield.dtsi

@@ -14,149 +14,11 @@
     stdout-path = "/soc/serial@3002000:38400";
   };
   memory@80000000 {
+    // Give 1GiB to Linux management
     device_type = "memory";
     reg = <0x0 0x80000000 0x0 0x40000000>;
   };
-  cpus {
-    #address-cells = <1>;
-    #size-cells = <0>;
-    timebase-frequency = <1000000>; // 1 MHz
-    CPU0: cpu@0 {
-      device_type = "cpu";
-      status = "okay";
-      compatible = "eth,ariane", "riscv";
-      clock-frequency = <50000000>; // 50 MHz
-      riscv,isa = "rv64imafdc";
-      mmu-type = "riscv,sv39";
-      tlb-split;
-      reg = <0>;
-      CPU0_intc: interrupt-controller {
-        #address-cells = <0>;
-        #interrupt-cells = <1>;
-        interrupt-controller;
-        compatible = "riscv,cpu-intc";
-      };
-    };
-  };
-  sysclk: virt_50mhz {
-    #clock-cells = <0>;
-    compatible = "fixed-clock";
-    clock-frequency = <50000000>;
-  };
-  soc: soc {
-    #address-cells = <2>;
-    #size-cells = <2>;
-    compatible = "eth,carfield-soc", "eth,cheshire-bare-soc", "simple-bus";
-    ranges;
-    debug@0 {
-      compatible = "riscv,debug-013";
-      reg-names = "control";
-      reg = <0x0 0x0 0x0 0x1000>;
-    };
-    ctrl-regs@3000000 {
-      compatible = "eth,control-regs";
-      reg = <0x0 0x3000000 0x0 0x1000>;
-    };
-    axi_llc@3001000 {
-      compatible = "eth,axi-llc";
-      reg = <0x0 0x3001000 0x0 0x5000>;
-    };
-    ddr_link: memory-controller@3006000 {
-      compatible = "eth,ddr-link";
-      reg = <0x0 0x3006000 0x0 0x1000>;
-    };
-    serial@3002000 {
-      compatible = "ns16550a";
-      clock-frequency = <50000000>; // 50 MHz
-      current-speed = <38400>;
-      interrupt-parent = <&PLIC0>;
-      interrupts = <1>;
-      reg = <0x0 0x3002000 0x0 0x1000>;
-      reg-shift = <2>; // regs are spaced on 32 bit boundary
-      reg-io-width = <4>; // only 32-bit access are supported
-    };
-    spi@3004000 {
-      compatible = "opentitan,spi-host", "lowrisc,spi";
-      interrupt-parent = <&PLIC0>;
-      interrupts = <17 18>;
-      reg = <0x0 0x3004000 0x0 0x1000>;
-      clock-frequency = <50000000>;
-      max-frequency = <20000000>;
-      #address-cells = <1>;
-      #size-cells = <0>;
-      boot-with = <1>;
-      nor@1 {
-        #address-cells = <0x1>;
-        #size-cells = <0x1>;
-        // Note : u-boot does not find mt25qu02g
-        compatible = "mt25qu02g", "jedec,spi-nor";
-        reg = <0x1>; // CS
-        spi-max-frequency = <20000000>;
-        spi-rx-bus-width = <0x1>;
-        spi-tx-bus-width = <0x1>;
-        disable-wp;
-        partition@0 {
-          label = "all";
-          reg = <0x0 0x6000000>; // 96 MB
-          read-only;
-        };
-      };
-    };
-    clint@2040000 {
-      compatible = "riscv,clint0";
-      interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
-      reg-names = "control";
-      reg = <0x0 0x2040000 0x0 0x040000>;
-    };
-    PLIC0: interrupt-controller@4000000 {
-      compatible = "riscv,plic0";
-      #address-cells = <0>;
-      #interrupt-cells = <1>;
-      interrupt-controller;
-      interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
-      riscv,max-priority = <7>;
-      riscv,ndev = <51>;
-      reg = <0x0 0x4000000 0x0 0x4000000>;
-    };
-    gpio@3005000 {
-      compatible = "gpio,carfield";
-      reg = <0x0 0x3005000 0x0 0x1000>;
-      interrupts-extended = <&PLIC0 19 &PLIC0 21 &PLIC0 22 &PLIC0 24>;
-    };
-    tcdm@10000000 {
-      reg = <0x0 0x10000000 0x0 0x400000>;
-    };
-    soc-ctrl@20010000 {
-      compatible = "soc-ctrl,carfield";
-      reg = <0x0 0x20010000 0x0 0x1000>;
-    };
-    l2-intl-0@78000000 {
-      compatible = "l2-intl,carfield";
-      reg = <0x0 0x78000000 0x0 0x100000>;
-    };
-    l2-cont-0@78100000 {
-      compatible = "l2-cont,carfield";
-      reg = <0x0 0x78100000 0x0 0x100000>;
-    };
-    l2-intl-1@78200000 {
-      compatible = "l2-intl,carfield";
-      reg = <0x0 0x78200000 0x0 0x100000>;
-    };
-    l2-cont-1@78300000 {
-      compatible = "l2-cont,carfield";
-      reg = <0x0 0x78300000 0x0 0x100000>;
-    };
-    safety-island@60000000 {
-      compatible = "safety-island,carfield";
-      reg = <0x0 0x60000000 0x0 0x800000>;
-    };
-    integer-cluster@50000000 {
-      compatible = "integer-cluster,carfield";
-      reg = <0x0 0x50000000 0x0 0x800000>;
-    };
-    spatz-cluster@51000000 {
-      compatible = "spatz-cluster,carfield";
-      reg = <0x0 0x51000000 0x0 0x800000>;
-    };
-  };
+
+  /include/ "carfield_soc.dtsi"
+
 };